1 //===-- PPCInstrHTM.td - The PowerPC Hardware Transactional Memory -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hardware Transactional Memory extension to the 11 // PowerPC instruction set. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 17 def HasHTM : Predicate<"PPCSubTarget->hasHTM()">; 18 19 def HTM_get_imm : SDNodeXForm<imm, [{ 20 return getI32Imm (N->getZExtValue(), SDLoc(N)); 21 }]>; 22 23 let hasSideEffects = 1, usesCustomInserter = 1 in { 24 def TCHECK_RET : Pseudo<(outs crrc:$out), (ins), "#TCHECK_RET", []>; 25 } 26 27 28 let Predicates = [HasHTM] in { 29 30 def TBEGIN : XForm_htm0 <31, 654, 31 (outs crrc0:$ret), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>; 32 33 def TEND : XForm_htm1 <31, 686, 34 (outs crrc0:$ret), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>; 35 36 def TABORT : XForm_base_r3xo <31, 910, 37 (outs crrc0:$ret), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR, 38 []>, isDOT { 39 let RST = 0; 40 let B = 0; 41 } 42 43 def TABORTWC : XForm_base_r3xo <31, 782, 44 (outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, gprc:$B), 45 "tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>, 46 isDOT; 47 48 def TABORTWCI : XForm_base_r3xo <31, 846, 49 (outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, u5imm:$B), 50 "tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>, 51 isDOT; 52 53 def TABORTDC : XForm_base_r3xo <31, 814, 54 (outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, gprc:$B), 55 "tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>, 56 isDOT; 57 58 def TABORTDCI : XForm_base_r3xo <31, 878, 59 (outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, u5imm:$B), 60 "tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>, 61 isDOT; 62 63 def TSR : XForm_htm2 <31, 750, 64 (outs crrc0:$ret), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>, 65 isDOT; 66 67 def TCHECK : XForm_htm3 <31, 718, 68 (outs), (ins crrc:$BF), "tcheck $BF", IIC_SprMTSPR, []>; 69 70 71 def TRECLAIM : XForm_base_r3xo <31, 942, 72 (outs crrc:$ret), (ins gprc:$A), "treclaim. $A", 73 IIC_SprMTSPR, []>, 74 isDOT { 75 let RST = 0; 76 let B = 0; 77 } 78 79 def TRECHKPT : XForm_base_r3xo <31, 1006, 80 (outs crrc:$ret), (ins), "trechkpt.", IIC_SprMTSPR, []>, 81 isDOT { 82 let RST = 0; 83 let A = 0; 84 let B = 0; 85 } 86 87 // Builtins 88 89 // All HTM instructions, with the exception of tcheck, set CR0 with the 90 // value of the MSR Transaction State (TS) bits that exist before the 91 // instruction is executed. For tbegin., the EQ bit in CR0 can be used 92 // to determine whether the transaction was successfully started (0) or 93 // failed (1). We use an XORI pattern to 'flip' the bit to match the 94 // tbegin builtin API which defines a return value of 1 as success. 95 96 def : Pat<(int_ppc_tbegin i32:$R), 97 (XORI 98 (EXTRACT_SUBREG ( 99 TBEGIN (HTM_get_imm imm:$R)), sub_eq), 100 1)>; 101 102 def : Pat<(int_ppc_tend i32:$R), 103 (TEND (HTM_get_imm imm:$R))>; 104 105 106 def : Pat<(int_ppc_tabort i32:$R), 107 (TABORT $R)>; 108 109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB), 110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>; 111 112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI), 113 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>; 114 115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB), 116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>; 117 118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI), 119 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>; 120 121 def : Pat<(int_ppc_tcheck), 122 (TCHECK_RET)>; 123 124 def : Pat<(int_ppc_treclaim i32:$RA), 125 (TRECLAIM $RA)>; 126 127 def : Pat<(int_ppc_trechkpt), 128 (TRECHKPT)>; 129 130 def : Pat<(int_ppc_tsr i32:$L), 131 (TSR (HTM_get_imm imm:$L))>; 132 133 def : Pat<(int_ppc_get_texasr), 134 (MFSPR8 130)>; 135 136 def : Pat<(int_ppc_get_texasru), 137 (MFSPR8 131)>; 138 139 def : Pat<(int_ppc_get_tfhar), 140 (MFSPR8 128)>; 141 142 def : Pat<(int_ppc_get_tfiar), 143 (MFSPR8 129)>; 144 145 146 def : Pat<(int_ppc_set_texasr i64:$V), 147 (MTSPR8 130, $V)>; 148 149 def : Pat<(int_ppc_set_texasru i64:$V), 150 (MTSPR8 131, $V)>; 151 152 def : Pat<(int_ppc_set_tfhar i64:$V), 153 (MTSPR8 128, $V)>; 154 155 def : Pat<(int_ppc_set_tfiar i64:$V), 156 (MTSPR8 129, $V)>; 157 158 159 // Extended mnemonics 160 def : Pat<(int_ppc_tendall), 161 (TEND 1)>; 162 163 def : Pat<(int_ppc_tresume), 164 (TSR 1)>; 165 166 def : Pat<(int_ppc_tsuspend), 167 (TSR 0)>; 168 169 def : Pat<(i64 (int_ppc_ttest)), 170 (RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>; 171 172 } // [HasHTM] 173
