1 2 To-do 3 ----- 4 5 * Keep the address of the constant pool in a register instead of forming its 6 address all of the time. 7 * We can fold small constant offsets into the %hi/%lo references to constant 8 pool addresses as well. 9 * When in V9 mode, register allocate %icc[0-3]. 10 * Add support for isel'ing UMUL_LOHI instead of marking it as Expand. 11 * Emit the 'Branch on Integer Register with Prediction' instructions. It's 12 not clear how to write a pattern for this though: 13 14 float %t1(int %a, int* %p) { 15 %C = seteq int %a, 0 16 br bool %C, label %T, label %F 17 T: 18 store int 123, int* %p 19 br label %F 20 F: 21 ret float undef 22 } 23 24 codegens to this: 25 26 t1: 27 save -96, %o6, %o6 28 1) subcc %i0, 0, %l0 29 1) bne .LBBt1_2 ! F 30 nop 31 .LBBt1_1: ! T 32 or %g0, 123, %l0 33 st %l0, [%i1] 34 .LBBt1_2: ! F 35 restore %g0, %g0, %g0 36 retl 37 nop 38 39 1) should be replaced with a brz in V9 mode. 40 41 * Same as above, but emit conditional move on register zero (p192) in V9 42 mode. Testcase: 43 44 int %t1(int %a, int %b) { 45 %C = seteq int %a, 0 46 %D = select bool %C, int %a, int %b 47 ret int %D 48 } 49 50 * Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 51 with the Y register, if they are faster. 52 53 * Codegen bswap(load)/store(bswap) -> load/store ASI 54 55 * Implement frame pointer elimination, e.g. eliminate save/restore for 56 leaf fns. 57 * Fill delay slots 58 59 * Use %g0 directly to materialize 0. No instruction is required. 60
