1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This describes the calling conventions for the X86-32 and X86-64 11 // architectures. 12 // 13 //===----------------------------------------------------------------------===// 14 15 /// CCIfSubtarget - Match if the current subtarget has a feature F. 16 class CCIfSubtarget<string F, CCAction A> 17 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 18 "(State.getMachineFunction().getSubtarget()).", F), 19 A>; 20 21 //===----------------------------------------------------------------------===// 22 // Return Value Calling Conventions 23 //===----------------------------------------------------------------------===// 24 25 // Return-value conventions common to all X86 CC's. 26 def RetCC_X86Common : CallingConv<[ 27 // Scalar values are returned in AX first, then DX. For i8, the ABI 28 // requires the values to be in AL and AH, however this code uses AL and DL 29 // instead. This is because using AH for the second register conflicts with 30 // the way LLVM does multiple return values -- a return of {i16,i8} would end 31 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 32 // for functions that return two i8 values are currently expected to pack the 33 // values into an i16 (which uses AX, and thus AL:AH). 34 // 35 // For code that doesn't care about the ABI, we allow returning more than two 36 // integer values in registers. 37 CCIfType<[i1], CCPromoteToType<i8>>, 38 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 39 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 40 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 42 43 // Boolean vectors of AVX-512 are returned in SIMD registers. 44 // The call from AVX to AVX-512 function should work, 45 // since the boolean types in AVX/AVX2 are promoted by default. 46 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 47 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 48 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 49 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 50 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 51 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 52 53 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 54 // can only be used by ABI non-compliant code. If the target doesn't have XMM 55 // registers, it won't have vector types. 56 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 57 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 58 59 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 60 // can only be used by ABI non-compliant code. This vector type is only 61 // supported while using the AVX target feature. 62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 63 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 64 65 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 66 // can only be used by ABI non-compliant code. This vector type is only 67 // supported while using the AVX-512 target feature. 68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 69 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 70 71 // MMX vector types are always returned in MM0. If the target doesn't have 72 // MM0, it doesn't support these vector types. 73 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 74 75 // Long double types are always returned in FP0 (even with SSE). 76 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>> 77 ]>; 78 79 // X86-32 C return-value convention. 80 def RetCC_X86_32_C : CallingConv<[ 81 // The X86-32 calling convention returns FP values in FP0, unless marked 82 // with "inreg" (used here to distinguish one kind of reg from another, 83 // weirdly; this is really the sse-regparm calling convention) in which 84 // case they use XMM0, otherwise it is the same as the common X86 calling 85 // conv. 86 CCIfInReg<CCIfSubtarget<"hasSSE2()", 87 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 88 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>, 89 CCDelegateTo<RetCC_X86Common> 90 ]>; 91 92 // X86-32 FastCC return-value convention. 93 def RetCC_X86_32_Fast : CallingConv<[ 94 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 95 // SSE2. 96 // This can happen when a float, 2 x float, or 3 x float vector is split by 97 // target lowering, and is returned in 1-3 sse regs. 98 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 99 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 100 101 // For integers, ECX can be used as an extra return register 102 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 103 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 104 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 105 106 // Otherwise, it is the same as the common X86 calling convention. 107 CCDelegateTo<RetCC_X86Common> 108 ]>; 109 110 // Intel_OCL_BI return-value convention. 111 def RetCC_Intel_OCL_BI : CallingConv<[ 112 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 113 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 114 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 115 116 // 256-bit FP vectors 117 // No more than 4 registers 118 CCIfType<[v8f32, v4f64, v8i32, v4i64], 119 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 120 121 // 512-bit FP vectors 122 CCIfType<[v16f32, v8f64, v16i32, v8i64], 123 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 124 125 // i32, i64 in the standard way 126 CCDelegateTo<RetCC_X86Common> 127 ]>; 128 129 // X86-32 HiPE return-value convention. 130 def RetCC_X86_32_HiPE : CallingConv<[ 131 // Promote all types to i32 132 CCIfType<[i8, i16], CCPromoteToType<i32>>, 133 134 // Return: HP, P, VAL1, VAL2 135 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 136 ]>; 137 138 // X86-32 HiPE return-value convention. 139 def RetCC_X86_32_VectorCall : CallingConv<[ 140 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 141 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 142 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 143 144 // 256-bit FP vectors 145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 146 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 147 148 // 512-bit FP vectors 149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 150 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 151 152 // Return integers in the standard way. 153 CCDelegateTo<RetCC_X86Common> 154 ]>; 155 156 // X86-64 C return-value convention. 157 def RetCC_X86_64_C : CallingConv<[ 158 // The X86-64 calling convention always returns FP values in XMM0. 159 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 160 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 161 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 162 163 // MMX vector types are always returned in XMM0. 164 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 165 CCDelegateTo<RetCC_X86Common> 166 ]>; 167 168 // X86-Win64 C return-value convention. 169 def RetCC_X86_Win64_C : CallingConv<[ 170 // The X86-Win64 calling convention always returns __m64 values in RAX. 171 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 172 173 // Otherwise, everything is the same as 'normal' X86-64 C CC. 174 CCDelegateTo<RetCC_X86_64_C> 175 ]>; 176 177 // X86-64 HiPE return-value convention. 178 def RetCC_X86_64_HiPE : CallingConv<[ 179 // Promote all types to i64 180 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 181 182 // Return: HP, P, VAL1, VAL2 183 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 184 ]>; 185 186 // X86-64 WebKit_JS return-value convention. 187 def RetCC_X86_64_WebKit_JS : CallingConv<[ 188 // Promote all types to i64 189 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 190 191 // Return: RAX 192 CCIfType<[i64], CCAssignToReg<[RAX]>> 193 ]>; 194 195 // X86-64 AnyReg return-value convention. No explicit register is specified for 196 // the return-value. The register allocator is allowed and expected to choose 197 // any free register. 198 // 199 // This calling convention is currently only supported by the stackmap and 200 // patchpoint intrinsics. All other uses will result in an assert on Debug 201 // builds. On Release builds we fallback to the X86 C calling convention. 202 def RetCC_X86_64_AnyReg : CallingConv<[ 203 CCCustom<"CC_X86_AnyReg_Error"> 204 ]>; 205 206 // X86-64 HHVM return-value convention. 207 def RetCC_X86_64_HHVM: CallingConv<[ 208 // Promote all types to i64 209 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 210 211 // Return: could return in any GP register save RSP and R12. 212 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, 213 RAX, R10, R11, R13, R14, R15]>> 214 ]>; 215 216 // This is the root return-value convention for the X86-32 backend. 217 def RetCC_X86_32 : CallingConv<[ 218 // If FastCC, use RetCC_X86_32_Fast. 219 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 220 // If HiPE, use RetCC_X86_32_HiPE. 221 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 222 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 223 224 // Otherwise, use RetCC_X86_32_C. 225 CCDelegateTo<RetCC_X86_32_C> 226 ]>; 227 228 // This is the root return-value convention for the X86-64 backend. 229 def RetCC_X86_64 : CallingConv<[ 230 // HiPE uses RetCC_X86_64_HiPE 231 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 232 233 // Handle JavaScript calls. 234 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>, 235 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 236 237 // Handle explicit CC selection 238 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 239 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 240 241 // Handle HHVM calls. 242 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>, 243 244 // Mingw64 and native Win64 use Win64 CC 245 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 246 247 // Otherwise, drop to normal X86-64 CC 248 CCDelegateTo<RetCC_X86_64_C> 249 ]>; 250 251 // This is the return-value convention used for the entire X86 backend. 252 def RetCC_X86 : CallingConv<[ 253 254 // Check if this is the Intel OpenCL built-ins calling convention 255 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 256 257 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 258 CCDelegateTo<RetCC_X86_32> 259 ]>; 260 261 //===----------------------------------------------------------------------===// 262 // X86-64 Argument Calling Conventions 263 //===----------------------------------------------------------------------===// 264 265 def CC_X86_64_C : CallingConv<[ 266 // Handles byval parameters. 267 CCIfByVal<CCPassByVal<8, 8>>, 268 269 // Promote i1/i8/i16 arguments to i32. 270 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 271 272 // The 'nest' parameter, if any, is passed in R10. 273 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 274 CCIfNest<CCAssignToReg<[R10]>>, 275 276 // The first 6 integer arguments are passed in integer registers. 277 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 278 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 279 280 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 281 CCIfType<[x86mmx], 282 CCIfSubtarget<"isTargetDarwin()", 283 CCIfSubtarget<"hasSSE2()", 284 CCPromoteToType<v2i64>>>>, 285 286 // Boolean vectors of AVX-512 are passed in SIMD registers. 287 // The call from AVX to AVX-512 function should work, 288 // since the boolean types in AVX/AVX2 are promoted by default. 289 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 290 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 291 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 292 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 293 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 294 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 295 296 // The first 8 FP/Vector arguments are passed in XMM registers. 297 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 298 CCIfSubtarget<"hasSSE1()", 299 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 300 301 // The first 8 256-bit vector arguments are passed in YMM registers, unless 302 // this is a vararg function. 303 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 304 // fixed arguments to vararg functions are supposed to be passed in 305 // registers. Actually modeling that would be a lot of work, though. 306 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 307 CCIfSubtarget<"hasFp256()", 308 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 309 YMM4, YMM5, YMM6, YMM7]>>>>, 310 311 // The first 8 512-bit vector arguments are passed in ZMM registers. 312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 313 CCIfSubtarget<"hasAVX512()", 314 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 315 316 // Integer/FP values get stored in stack slots that are 8 bytes in size and 317 // 8-byte aligned if there are no more registers to hold them. 318 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, 319 320 // Long doubles get stack slots whose size and alignment depends on the 321 // subtarget. 322 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 323 324 // Vectors get 16-byte stack slots that are 16-byte aligned. 325 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 326 327 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 328 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 329 CCAssignToStack<32, 32>>, 330 331 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 332 CCIfType<[v16i32, v8i64, v16f32, v8f64], 333 CCAssignToStack<64, 64>> 334 ]>; 335 336 // Calling convention for X86-64 HHVM. 337 def CC_X86_64_HHVM : CallingConv<[ 338 // Use all/any GP registers for args, except RSP. 339 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15, 340 RDI, RSI, RDX, RCX, R8, R9, 341 RAX, R10, R11, R13, R14]>> 342 ]>; 343 344 // Calling convention for helper functions in HHVM. 345 def CC_X86_64_HHVM_C : CallingConv<[ 346 // Pass the first argument in RBP. 347 CCIfType<[i64], CCAssignToReg<[RBP]>>, 348 349 // Otherwise it's the same as the regular C calling convention. 350 CCDelegateTo<CC_X86_64_C> 351 ]>; 352 353 // Calling convention used on Win64 354 def CC_X86_Win64_C : CallingConv<[ 355 // FIXME: Handle byval stuff. 356 // FIXME: Handle varargs. 357 358 // Promote i1/i8/i16 arguments to i32. 359 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 360 361 // The 'nest' parameter, if any, is passed in R10. 362 CCIfNest<CCAssignToReg<[R10]>>, 363 364 // 128 bit vectors are passed by pointer 365 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>, 366 367 368 // 256 bit vectors are passed by pointer 369 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>, 370 371 // 512 bit vectors are passed by pointer 372 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 373 374 // The first 4 MMX vector arguments are passed in GPRs. 375 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 376 377 // The first 4 integer arguments are passed in integer registers. 378 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 379 [XMM0, XMM1, XMM2, XMM3]>>, 380 381 // Do not pass the sret argument in RCX, the Win64 thiscall calling 382 // convention requires "this" to be passed in RCX. 383 CCIfCC<"CallingConv::X86_ThisCall", 384 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 385 [XMM1, XMM2, XMM3]>>>>, 386 387 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 388 [XMM0, XMM1, XMM2, XMM3]>>, 389 390 // The first 4 FP/Vector arguments are passed in XMM registers. 391 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 392 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 393 [RCX , RDX , R8 , R9 ]>>, 394 395 // Integer/FP values get stored in stack slots that are 8 bytes in size and 396 // 8-byte aligned if there are no more registers to hold them. 397 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>, 398 399 // Long doubles get stack slots whose size and alignment depends on the 400 // subtarget. 401 CCIfType<[f80], CCAssignToStack<0, 0>> 402 ]>; 403 404 def CC_X86_Win64_VectorCall : CallingConv<[ 405 // The first 6 floating point and vector types of 128 bits or less use 406 // XMM0-XMM5. 407 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 408 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>, 409 410 // 256-bit vectors use YMM registers. 411 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 412 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>, 413 414 // 512-bit vectors use ZMM registers. 415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 416 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>, 417 418 // Delegate to fastcall to handle integer types. 419 CCDelegateTo<CC_X86_Win64_C> 420 ]>; 421 422 423 def CC_X86_64_GHC : CallingConv<[ 424 // Promote i8/i16/i32 arguments to i64. 425 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 426 427 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 428 CCIfType<[i64], 429 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 430 431 // Pass in STG registers: F1, F2, F3, F4, D1, D2 432 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 433 CCIfSubtarget<"hasSSE1()", 434 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>> 435 ]>; 436 437 def CC_X86_64_HiPE : CallingConv<[ 438 // Promote i8/i16/i32 arguments to i64. 439 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 440 441 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 442 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 443 444 // Integer/FP values get stored in stack slots that are 8 bytes in size and 445 // 8-byte aligned if there are no more registers to hold them. 446 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 447 ]>; 448 449 def CC_X86_64_WebKit_JS : CallingConv<[ 450 // Promote i8/i16 arguments to i32. 451 CCIfType<[i8, i16], CCPromoteToType<i32>>, 452 453 // Only the first integer argument is passed in register. 454 CCIfType<[i32], CCAssignToReg<[EAX]>>, 455 CCIfType<[i64], CCAssignToReg<[RAX]>>, 456 457 // The remaining integer arguments are passed on the stack. 32bit integer and 458 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. 459 // 64bit integer and floating-point arguments are aligned to 8 byte and stored 460 // in 8 byte stack slots. 461 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 462 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 463 ]>; 464 465 // No explicit register is specified for the AnyReg calling convention. The 466 // register allocator may assign the arguments to any free register. 467 // 468 // This calling convention is currently only supported by the stackmap and 469 // patchpoint intrinsics. All other uses will result in an assert on Debug 470 // builds. On Release builds we fallback to the X86 C calling convention. 471 def CC_X86_64_AnyReg : CallingConv<[ 472 CCCustom<"CC_X86_AnyReg_Error"> 473 ]>; 474 475 //===----------------------------------------------------------------------===// 476 // X86 C Calling Convention 477 //===----------------------------------------------------------------------===// 478 479 /// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 480 /// values are spilled on the stack. 481 def CC_X86_32_Vector_Common : CallingConv<[ 482 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 483 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>, 484 485 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 486 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 487 CCAssignToStack<32, 32>>, 488 489 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 491 CCAssignToStack<64, 64>> 492 ]>; 493 494 // CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 495 // vector registers 496 def CC_X86_32_Vector_Standard : CallingConv<[ 497 // SSE vector arguments are passed in XMM registers. 498 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 499 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 500 501 // AVX 256-bit vector arguments are passed in YMM registers. 502 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 503 CCIfSubtarget<"hasFp256()", 504 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 505 506 // AVX 512-bit vector arguments are passed in ZMM registers. 507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 508 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 509 510 CCDelegateTo<CC_X86_32_Vector_Common> 511 ]>; 512 513 // CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 514 // vector registers. 515 def CC_X86_32_Vector_Darwin : CallingConv<[ 516 // SSE vector arguments are passed in XMM registers. 517 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 518 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 519 520 // AVX 256-bit vector arguments are passed in YMM registers. 521 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 522 CCIfSubtarget<"hasFp256()", 523 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 524 525 // AVX 512-bit vector arguments are passed in ZMM registers. 526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 527 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 528 529 CCDelegateTo<CC_X86_32_Vector_Common> 530 ]>; 531 532 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 533 /// values are spilled on the stack. 534 def CC_X86_32_Common : CallingConv<[ 535 // Handles byval parameters. 536 CCIfByVal<CCPassByVal<4, 4>>, 537 538 // The first 3 float or double arguments, if marked 'inreg' and if the call 539 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 540 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 541 CCIfSubtarget<"hasSSE2()", 542 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 543 544 // The first 3 __m64 vector arguments are passed in mmx registers if the 545 // call is not a vararg call. 546 CCIfNotVarArg<CCIfType<[x86mmx], 547 CCAssignToReg<[MM0, MM1, MM2]>>>, 548 549 // Integer/Float values get stored in stack slots that are 4 bytes in 550 // size and 4-byte aligned. 551 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 552 553 // Doubles get 8-byte slots that are 4-byte aligned. 554 CCIfType<[f64], CCAssignToStack<8, 4>>, 555 556 // Long doubles get slots whose size depends on the subtarget. 557 CCIfType<[f80], CCAssignToStack<0, 4>>, 558 559 // Boolean vectors of AVX-512 are passed in SIMD registers. 560 // The call from AVX to AVX-512 function should work, 561 // since the boolean types in AVX/AVX2 are promoted by default. 562 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 563 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 564 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 565 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 566 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 567 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 568 569 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 570 // passed in the parameter area. 571 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 572 573 // Darwin passes vectors in a form that differs from the i386 psABI 574 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 575 576 // Otherwise, drop to 'normal' X86-32 CC 577 CCDelegateTo<CC_X86_32_Vector_Standard> 578 ]>; 579 580 def CC_X86_32_C : CallingConv<[ 581 // Promote i1/i8/i16 arguments to i32. 582 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 583 584 // The 'nest' parameter, if any, is passed in ECX. 585 CCIfNest<CCAssignToReg<[ECX]>>, 586 587 // The first 3 integer arguments, if marked 'inreg' and if the call is not 588 // a vararg call, are passed in integer registers. 589 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 590 591 // Otherwise, same as everything else. 592 CCDelegateTo<CC_X86_32_Common> 593 ]>; 594 595 def CC_X86_32_FastCall : CallingConv<[ 596 // Promote i1/i8/i16 arguments to i32. 597 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 598 599 // The 'nest' parameter, if any, is passed in EAX. 600 CCIfNest<CCAssignToReg<[EAX]>>, 601 602 // The first 2 integer arguments are passed in ECX/EDX 603 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 604 605 // Otherwise, same as everything else. 606 CCDelegateTo<CC_X86_32_Common> 607 ]>; 608 609 def CC_X86_32_VectorCall : CallingConv<[ 610 // The first 6 floating point and vector types of 128 bits or less use 611 // XMM0-XMM5. 612 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 613 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>, 614 615 // 256-bit vectors use YMM registers. 616 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 617 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>, 618 619 // 512-bit vectors use ZMM registers. 620 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 621 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>, 622 623 // Otherwise, pass it indirectly. 624 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, 625 v32i8, v16i16, v8i32, v4i64, v8f32, v4f64, 626 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 627 CCCustom<"CC_X86_32_VectorCallIndirect">>, 628 629 // Delegate to fastcall to handle integer types. 630 CCDelegateTo<CC_X86_32_FastCall> 631 ]>; 632 633 def CC_X86_32_ThisCall_Common : CallingConv<[ 634 // The first integer argument is passed in ECX 635 CCIfType<[i32], CCAssignToReg<[ECX]>>, 636 637 // Otherwise, same as everything else. 638 CCDelegateTo<CC_X86_32_Common> 639 ]>; 640 641 def CC_X86_32_ThisCall_Mingw : CallingConv<[ 642 // Promote i1/i8/i16 arguments to i32. 643 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 644 645 CCDelegateTo<CC_X86_32_ThisCall_Common> 646 ]>; 647 648 def CC_X86_32_ThisCall_Win : CallingConv<[ 649 // Promote i1/i8/i16 arguments to i32. 650 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 651 652 // Pass sret arguments indirectly through stack. 653 CCIfSRet<CCAssignToStack<4, 4>>, 654 655 CCDelegateTo<CC_X86_32_ThisCall_Common> 656 ]>; 657 658 def CC_X86_32_ThisCall : CallingConv<[ 659 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 660 CCDelegateTo<CC_X86_32_ThisCall_Win> 661 ]>; 662 663 def CC_X86_32_FastCC : CallingConv<[ 664 // Handles byval parameters. Note that we can't rely on the delegation 665 // to CC_X86_32_Common for this because that happens after code that 666 // puts arguments in registers. 667 CCIfByVal<CCPassByVal<4, 4>>, 668 669 // Promote i1/i8/i16 arguments to i32. 670 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 671 672 // The 'nest' parameter, if any, is passed in EAX. 673 CCIfNest<CCAssignToReg<[EAX]>>, 674 675 // The first 2 integer arguments are passed in ECX/EDX 676 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 677 678 // The first 3 float or double arguments, if the call is not a vararg 679 // call and if SSE2 is available, are passed in SSE registers. 680 CCIfNotVarArg<CCIfType<[f32,f64], 681 CCIfSubtarget<"hasSSE2()", 682 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 683 684 // Doubles get 8-byte slots that are 8-byte aligned. 685 CCIfType<[f64], CCAssignToStack<8, 8>>, 686 687 // Otherwise, same as everything else. 688 CCDelegateTo<CC_X86_32_Common> 689 ]>; 690 691 def CC_X86_32_GHC : CallingConv<[ 692 // Promote i8/i16 arguments to i32. 693 CCIfType<[i8, i16], CCPromoteToType<i32>>, 694 695 // Pass in STG registers: Base, Sp, Hp, R1 696 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 697 ]>; 698 699 def CC_X86_32_HiPE : CallingConv<[ 700 // Promote i8/i16 arguments to i32. 701 CCIfType<[i8, i16], CCPromoteToType<i32>>, 702 703 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 704 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 705 706 // Integer/Float values get stored in stack slots that are 4 bytes in 707 // size and 4-byte aligned. 708 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 709 ]>; 710 711 // X86-64 Intel OpenCL built-ins calling convention. 712 def CC_Intel_OCL_BI : CallingConv<[ 713 714 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 715 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 716 717 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 718 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 719 720 CCIfType<[i32], CCAssignToStack<4, 4>>, 721 722 // The SSE vector arguments are passed in XMM registers. 723 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 724 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 725 726 // The 256-bit vector arguments are passed in YMM registers. 727 CCIfType<[v8f32, v4f64, v8i32, v4i64], 728 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 729 730 // The 512-bit vector arguments are passed in ZMM registers. 731 CCIfType<[v16f32, v8f64, v16i32, v8i64], 732 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 733 734 // Pass masks in mask registers 735 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 736 737 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 738 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 739 CCDelegateTo<CC_X86_32_C> 740 ]>; 741 742 def CC_X86_32_Intr : CallingConv<[ 743 CCAssignToStack<4, 4> 744 ]>; 745 746 def CC_X86_64_Intr : CallingConv<[ 747 CCAssignToStack<8, 8> 748 ]>; 749 750 //===----------------------------------------------------------------------===// 751 // X86 Root Argument Calling Conventions 752 //===----------------------------------------------------------------------===// 753 754 // This is the root argument convention for the X86-32 backend. 755 def CC_X86_32 : CallingConv<[ 756 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 757 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_32_VectorCall>>, 758 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 759 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 760 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 761 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 762 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_32_Intr>>, 763 764 // Otherwise, drop to normal X86-32 CC 765 CCDelegateTo<CC_X86_32_C> 766 ]>; 767 768 // This is the root argument convention for the X86-64 backend. 769 def CC_X86_64 : CallingConv<[ 770 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 771 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 772 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>, 773 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 774 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>, 775 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 776 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 777 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>, 778 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>, 779 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_64_Intr>>, 780 781 // Mingw64 and native Win64 use Win64 CC 782 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 783 784 // Otherwise, drop to normal X86-64 CC 785 CCDelegateTo<CC_X86_64_C> 786 ]>; 787 788 // This is the argument convention used for the entire X86 backend. 789 def CC_X86 : CallingConv<[ 790 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 791 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 792 CCDelegateTo<CC_X86_32> 793 ]>; 794 795 //===----------------------------------------------------------------------===// 796 // Callee-saved Registers. 797 //===----------------------------------------------------------------------===// 798 799 def CSR_NoRegs : CalleeSavedRegs<(add)>; 800 801 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 802 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 803 804 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 805 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 806 807 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15, 808 (sequence "XMM%u", 6, 15))>; 809 810 // The function used by Darwin to obtain the address of a thread-local variable 811 // uses rdi to pass a single parameter and rax for the return value. All other 812 // GPRs are preserved. 813 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 814 R8, R9, R10, R11)>; 815 816 // All GPRs - except r11 817 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 818 R8, R9, R10, RSP)>; 819 820 // All registers - except r11 821 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 822 (sequence "XMM%u", 0, 15))>; 823 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 824 (sequence "YMM%u", 0, 15))>; 825 826 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 827 R11, R12, R13, R14, R15, RBP, 828 (sequence "XMM%u", 0, 15))>; 829 830 def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 831 EDI, ESP)>; 832 def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 833 (sequence "XMM%u", 0, 7))>; 834 835 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP, 836 (sequence "XMM%u", 16, 31))>; 837 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP, 838 (sequence "YMM%u", 0, 31)), 839 (sequence "XMM%u", 0, 15))>; 840 841 // Standard C + YMM6-15 842 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 843 R13, R14, R15, 844 (sequence "YMM%u", 6, 15))>; 845 846 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 847 R12, R13, R14, R15, 848 (sequence "ZMM%u", 6, 21), 849 K4, K5, K6, K7)>; 850 //Standard C + XMM 8-15 851 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 852 (sequence "XMM%u", 8, 15))>; 853 854 //Standard C + YMM 8-15 855 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 856 (sequence "YMM%u", 8, 15))>; 857 858 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15, 859 (sequence "ZMM%u", 16, 31), 860 K4, K5, K6, K7)>; 861 862 // Only R12 is preserved for PHP calls in HHVM. 863 def CSR_64_HHVM : CalleeSavedRegs<(add R12)>; 864
