1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the various pseudo instructions used by the compiler, 11 // as well as Pat patterns used during instruction selection. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // Pattern Matching Support 17 18 def GetLo32XForm : SDNodeXForm<imm, [{ 19 // Transformation function: get the low 32 bits. 20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N)); 21 }]>; 22 23 def GetLo8XForm : SDNodeXForm<imm, [{ 24 // Transformation function: get the low 8 bits. 25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N)); 26 }]>; 27 28 29 //===----------------------------------------------------------------------===// 30 // Random Pseudo Instructions. 31 32 // PIC base construction. This expands to code that looks like this: 33 // call $next_inst 34 // popl %destreg" 35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in 36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label), 37 "", []>; 38 39 40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 41 // a stack adjustment and the codegen must know that they may modify the stack 42 // pointer before prolog-epilog rewriting occurs. 43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 44 // sub / add which can clobber EFLAGS. 45 let Defs = [ESP, EFLAGS], Uses = [ESP] in { 46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 47 "#ADJCALLSTACKDOWN", 48 []>, 49 Requires<[NotLP64]>; 50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 51 "#ADJCALLSTACKUP", 52 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 53 Requires<[NotLP64]>; 54 } 55 def : Pat<(X86callseq_start timm:$amt1), 56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>; 57 58 59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into 60 // a stack adjustment and the codegen must know that they may modify the stack 61 // pointer before prolog-epilog rewriting occurs. 62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 63 // sub / add which can clobber EFLAGS. 64 let Defs = [RSP, EFLAGS], Uses = [RSP] in { 65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 66 "#ADJCALLSTACKDOWN", 67 []>, 68 Requires<[IsLP64]>; 69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2), 70 "#ADJCALLSTACKUP", 71 [(X86callseq_end timm:$amt1, timm:$amt2)]>, 72 Requires<[IsLP64]>; 73 } 74 def : Pat<(X86callseq_start timm:$amt1), 75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>; 76 77 78 // x86-64 va_start lowering magic. 79 let usesCustomInserter = 1, Defs = [EFLAGS] in { 80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo, 81 (outs), 82 (ins GR8:$al, 83 i64imm:$regsavefi, i64imm:$offset, 84 variable_ops), 85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset", 86 [(X86vastart_save_xmm_regs GR8:$al, 87 imm:$regsavefi, 88 imm:$offset), 89 (implicit EFLAGS)]>; 90 91 // The VAARG_64 pseudo-instruction takes the address of the va_list, 92 // and places the address of the next argument into a register. 93 let Defs = [EFLAGS] in 94 def VAARG_64 : I<0, Pseudo, 95 (outs GR64:$dst), 96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align), 97 "#VAARG_64 $dst, $ap, $size, $mode, $align", 98 [(set GR64:$dst, 99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)), 100 (implicit EFLAGS)]>; 101 102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows 103 // targets. These calls are needed to probe the stack when allocating more than 104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to 105 // ensure that the guard pages used by the OS virtual memory manager are 106 // allocated in correct sequence. 107 // The main point of having separate instruction are extra unmodelled effects 108 // (compared to ordinary calls) like stack pointer change. 109 110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins), 112 "# dynamic stack allocation", 113 [(X86WinAlloca)]>; 114 115 // When using segmented stacks these are lowered into instructions which first 116 // check if the current stacklet has enough free memory. If it does, memory is 117 // allocated by bumping the stack pointer. Otherwise memory is allocated from 118 // the heap. 119 120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size), 122 "# variable sized alloca for segmented stacks", 123 [(set GR32:$dst, 124 (X86SegAlloca GR32:$size))]>, 125 Requires<[NotLP64]>; 126 127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in 128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size), 129 "# variable sized alloca for segmented stacks", 130 [(set GR64:$dst, 131 (X86SegAlloca GR64:$size))]>, 132 Requires<[In64BitMode]>; 133 } 134 135 //===----------------------------------------------------------------------===// 136 // EH Pseudo Instructions 137 // 138 let SchedRW = [WriteSystem] in { 139 let isTerminator = 1, isReturn = 1, isBarrier = 1, 140 hasCtrlDep = 1, isCodeGenOnly = 1 in { 141 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), 142 "ret\t#eh_return, addr: $addr", 143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 144 145 } 146 147 let isTerminator = 1, isReturn = 1, isBarrier = 1, 148 hasCtrlDep = 1, isCodeGenOnly = 1 in { 149 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr), 150 "ret\t#eh_return, addr: $addr", 151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>; 152 153 } 154 155 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, 156 isCodeGenOnly = 1, isReturn = 1 in { 157 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>; 158 159 // CATCHRET needs a custom inserter for SEH. 160 let usesCustomInserter = 1 in 161 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from), 162 "# CATCHRET", 163 [(catchret bb:$dst, bb:$from)]>; 164 } 165 166 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1, 167 usesCustomInserter = 1 in 168 def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>; 169 170 // This instruction is responsible for re-establishing stack pointers after an 171 // exception has been caught and we are rejoining normal control flow in the 172 // parent function or funclet. It generally sets ESP and EBP, and optionally 173 // ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us 174 // elsewhere. 175 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in 176 def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>; 177 178 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 179 usesCustomInserter = 1 in { 180 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf), 181 "#EH_SJLJ_SETJMP32", 182 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 183 Requires<[Not64BitMode]>; 184 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf), 185 "#EH_SJLJ_SETJMP64", 186 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>, 187 Requires<[In64BitMode]>; 188 let isTerminator = 1 in { 189 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf), 190 "#EH_SJLJ_LONGJMP32", 191 [(X86eh_sjlj_longjmp addr:$buf)]>, 192 Requires<[Not64BitMode]>; 193 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf), 194 "#EH_SJLJ_LONGJMP64", 195 [(X86eh_sjlj_longjmp addr:$buf)]>, 196 Requires<[In64BitMode]>; 197 } 198 } 199 } // SchedRW 200 201 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in { 202 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst), 203 "#EH_SjLj_Setup\t$dst", []>; 204 } 205 206 //===----------------------------------------------------------------------===// 207 // Pseudo instructions used by unwind info. 208 // 209 let isPseudo = 1 in { 210 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg), 211 "#SEH_PushReg $reg", []>; 212 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 213 "#SEH_SaveReg $reg, $dst", []>; 214 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst), 215 "#SEH_SaveXMM $reg, $dst", []>; 216 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size), 217 "#SEH_StackAlloc $size", []>; 218 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset), 219 "#SEH_SetFrame $reg, $offset", []>; 220 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode), 221 "#SEH_PushFrame $mode", []>; 222 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins), 223 "#SEH_EndPrologue", []>; 224 def SEH_Epilogue : I<0, Pseudo, (outs), (ins), 225 "#SEH_Epilogue", []>; 226 } 227 228 //===----------------------------------------------------------------------===// 229 // Pseudo instructions used by segmented stacks. 230 // 231 232 // This is lowered into a RET instruction by MCInstLower. We need 233 // this so that we don't have to have a MachineBasicBlock which ends 234 // with a RET and also has successors. 235 let isPseudo = 1 in { 236 def MORESTACK_RET: I<0, Pseudo, (outs), (ins), 237 "", []>; 238 239 // This instruction is lowered to a RET followed by a MOV. The two 240 // instructions are not generated on a higher level since then the 241 // verifier sees a MachineBasicBlock ending with a non-terminator. 242 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), 243 "", []>; 244 } 245 246 //===----------------------------------------------------------------------===// 247 // Alias Instructions 248 //===----------------------------------------------------------------------===// 249 250 // Alias instruction mapping movr0 to xor. 251 // FIXME: remove when we can teach regalloc that xor reg, reg is ok. 252 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1, 253 isPseudo = 1, AddedComplexity = 20 in 254 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 255 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>; 256 257 // Other widths can also make use of the 32-bit xor, which may have a smaller 258 // encoding and avoid partial register updates. 259 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; 260 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; 261 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> { 262 let AddedComplexity = 20; 263 } 264 265 let Predicates = [OptForSize, NotSlowIncDec, Not64BitMode], 266 AddedComplexity = 15 in { 267 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC, 268 // which only require 3 bytes compared to MOV32ri which requires 5. 269 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in { 270 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 271 [(set GR32:$dst, 1)]>; 272 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "", 273 [(set GR32:$dst, -1)]>; 274 } 275 276 // MOV16ri is 4 bytes, so the instructions above are smaller. 277 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>; 278 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>; 279 } 280 281 let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 10 in { 282 // AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1. 283 // FIXME: Add itinerary class and Schedule. 284 def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "", 285 [(set GR32:$dst, i32immSExt8:$src)]>, 286 Requires<[OptForMinSize]>; 287 def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "", 288 [(set GR64:$dst, i64immSExt8:$src)]>, 289 Requires<[OptForMinSize, NotWin64WithoutFP]>; 290 } 291 292 // Materialize i64 constant where top 32-bits are zero. This could theoretically 293 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however 294 // that would make it more difficult to rematerialize. 295 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, 296 isCodeGenOnly = 1, hasSideEffects = 0 in 297 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src), 298 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>; 299 300 // This 64-bit pseudo-move can be used for both a 64-bit constant that is 301 // actually the zero-extension of a 32-bit constant and for labels in the 302 // x86-64 small code model. 303 def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>; 304 305 let AddedComplexity = 1 in 306 def : Pat<(i64 mov64imm32:$src), 307 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>; 308 309 // Use sbb to materialize carry bit. 310 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in { 311 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns. 312 // However, Pat<> can't replicate the destination reg into the inputs of the 313 // result. 314 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "", 315 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 316 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "", 317 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 318 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", 319 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 320 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", 321 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; 322 } // isCodeGenOnly 323 324 325 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 326 (SETB_C16r)>; 327 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 328 (SETB_C32r)>; 329 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 330 (SETB_C64r)>; 331 332 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 333 (SETB_C16r)>; 334 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 335 (SETB_C32r)>; 336 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 337 (SETB_C64r)>; 338 339 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and 340 // will be eliminated and that the sbb can be extended up to a wider type. When 341 // this happens, it is great. However, if we are left with an 8-bit sbb and an 342 // and, we might as well just match it as a setb. 343 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), 344 (SETBr)>; 345 346 // (add OP, SETB) -> (adc OP, 0) 347 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op), 348 (ADC8ri GR8:$op, 0)>; 349 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op), 350 (ADC32ri8 GR32:$op, 0)>; 351 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op), 352 (ADC64ri8 GR64:$op, 0)>; 353 354 // (sub OP, SETB) -> (sbb OP, 0) 355 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 356 (SBB8ri GR8:$op, 0)>; 357 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 358 (SBB32ri8 GR32:$op, 0)>; 359 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)), 360 (SBB64ri8 GR64:$op, 0)>; 361 362 // (sub OP, SETCC_CARRY) -> (adc OP, 0) 363 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))), 364 (ADC8ri GR8:$op, 0)>; 365 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))), 366 (ADC32ri8 GR32:$op, 0)>; 367 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))), 368 (ADC64ri8 GR64:$op, 0)>; 369 370 //===----------------------------------------------------------------------===// 371 // String Pseudo Instructions 372 // 373 let SchedRW = [WriteMicrocoded] in { 374 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in { 375 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 376 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 377 Requires<[Not64BitMode]>; 378 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 379 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 380 Requires<[Not64BitMode]>; 381 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 382 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 383 Requires<[Not64BitMode]>; 384 } 385 386 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in { 387 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}", 388 [(X86rep_movs i8)], IIC_REP_MOVS>, REP, 389 Requires<[In64BitMode]>; 390 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}", 391 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16, 392 Requires<[In64BitMode]>; 393 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}", 394 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32, 395 Requires<[In64BitMode]>; 396 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", 397 [(X86rep_movs i64)], IIC_REP_MOVS>, REP, 398 Requires<[In64BitMode]>; 399 } 400 401 // FIXME: Should use "(X86rep_stos AL)" as the pattern. 402 let Defs = [ECX,EDI], isCodeGenOnly = 1 in { 403 let Uses = [AL,ECX,EDI] in 404 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 405 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 406 Requires<[Not64BitMode]>; 407 let Uses = [AX,ECX,EDI] in 408 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 409 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 410 Requires<[Not64BitMode]>; 411 let Uses = [EAX,ECX,EDI] in 412 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 413 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 414 Requires<[Not64BitMode]>; 415 } 416 417 let Defs = [RCX,RDI], isCodeGenOnly = 1 in { 418 let Uses = [AL,RCX,RDI] in 419 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}", 420 [(X86rep_stos i8)], IIC_REP_STOS>, REP, 421 Requires<[In64BitMode]>; 422 let Uses = [AX,RCX,RDI] in 423 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}", 424 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16, 425 Requires<[In64BitMode]>; 426 let Uses = [RAX,RCX,RDI] in 427 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}", 428 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32, 429 Requires<[In64BitMode]>; 430 431 let Uses = [RAX,RCX,RDI] in 432 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", 433 [(X86rep_stos i64)], IIC_REP_STOS>, REP, 434 Requires<[In64BitMode]>; 435 } 436 } // SchedRW 437 438 //===----------------------------------------------------------------------===// 439 // Thread Local Storage Instructions 440 // 441 442 // ELF TLS Support 443 // All calls clobber the non-callee saved registers. ESP is marked as 444 // a use to prevent stack-pointer assignments that appear immediately 445 // before calls from potentially appearing dead. 446 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 447 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 448 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 449 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 450 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 451 Uses = [ESP] in { 452 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 453 "# TLS_addr32", 454 [(X86tlsaddr tls32addr:$sym)]>, 455 Requires<[Not64BitMode]>; 456 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 457 "# TLS_base_addr32", 458 [(X86tlsbaseaddr tls32baseaddr:$sym)]>, 459 Requires<[Not64BitMode]>; 460 } 461 462 // All calls clobber the non-callee saved registers. RSP is marked as 463 // a use to prevent stack-pointer assignments that appear immediately 464 // before calls from potentially appearing dead. 465 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 466 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, 467 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, 468 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, 469 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 470 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], 471 Uses = [RSP] in { 472 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 473 "# TLS_addr64", 474 [(X86tlsaddr tls64addr:$sym)]>, 475 Requires<[In64BitMode]>; 476 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 477 "# TLS_base_addr64", 478 [(X86tlsbaseaddr tls64baseaddr:$sym)]>, 479 Requires<[In64BitMode]>; 480 } 481 482 // Darwin TLS Support 483 // For i386, the address of the thunk is passed on the stack, on return the 484 // address of the variable is in %eax. %ecx is trashed during the function 485 // call. All other registers are preserved. 486 let Defs = [EAX, ECX, EFLAGS], 487 Uses = [ESP], 488 usesCustomInserter = 1 in 489 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym), 490 "# TLSCall_32", 491 [(X86TLSCall addr:$sym)]>, 492 Requires<[Not64BitMode]>; 493 494 // For x86_64, the address of the thunk is passed in %rdi, on return 495 // the address of the variable is in %rax. All other registers are preserved. 496 let Defs = [RAX, EFLAGS], 497 Uses = [RSP, RDI], 498 usesCustomInserter = 1 in 499 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym), 500 "# TLSCall_64", 501 [(X86TLSCall addr:$sym)]>, 502 Requires<[In64BitMode]>; 503 504 505 //===----------------------------------------------------------------------===// 506 // Conditional Move Pseudo Instructions 507 508 // CMOV* - Used to implement the SELECT DAG operation. Expanded after 509 // instruction selection into a branch sequence. 510 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> { 511 def CMOV#NAME : I<0, Pseudo, 512 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond), 513 "#CMOV_"#NAME#" PSEUDO!", 514 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond, 515 EFLAGS)))]>; 516 } 517 518 let usesCustomInserter = 1, Uses = [EFLAGS] in { 519 // X86 doesn't have 8-bit conditional moves. Use a customInserter to 520 // emit control flow. An alternative to this is to mark i8 SELECT as Promote, 521 // however that requires promoting the operands, and can induce additional 522 // i8 register pressure. 523 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>; 524 525 let Predicates = [NoCMov] in { 526 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>; 527 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>; 528 } // Predicates = [NoCMov] 529 530 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no 531 // SSE1/SSE2. 532 let Predicates = [FPStackf32] in 533 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>; 534 535 let Predicates = [FPStackf64] in 536 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>; 537 538 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>; 539 540 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>; 541 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>; 542 defm _FR128 : CMOVrr_PSEUDO<FR128, f128>; 543 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>; 544 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>; 545 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>; 546 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>; 547 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>; 548 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>; 549 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>; 550 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>; 551 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>; 552 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>; 553 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>; 554 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>; 555 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>; 556 } // usesCustomInserter = 1, Uses = [EFLAGS] 557 558 //===----------------------------------------------------------------------===// 559 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions 560 //===----------------------------------------------------------------------===// 561 562 // FIXME: Use normal instructions and add lock prefix dynamically. 563 564 // Memory barriers 565 566 // TODO: Get this to fold the constant into the instruction. 567 let isCodeGenOnly = 1, Defs = [EFLAGS] in 568 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero), 569 "or{l}\t{$zero, $dst|$dst, $zero}", 570 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK, 571 Sched<[WriteALULd, WriteRMW]>; 572 573 let hasSideEffects = 1 in 574 def Int_MemBarrier : I<0, Pseudo, (outs), (ins), 575 "#MEMBARRIER", 576 [(X86MemBarrier)]>, Sched<[WriteLoad]>; 577 578 // RegOpc corresponds to the mr version of the instruction 579 // ImmOpc corresponds to the mi version of the instruction 580 // ImmOpc8 corresponds to the mi8 version of the instruction 581 // ImmMod corresponds to the instruction format of the mi and mi8 versions 582 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8, 583 Format ImmMod, string mnemonic> { 584 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 585 SchedRW = [WriteALULd, WriteRMW] in { 586 587 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 588 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 }, 589 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2), 590 !strconcat(mnemonic, "{b}\t", 591 "{$src2, $dst|$dst, $src2}"), 592 [], IIC_ALU_NONMEM>, LOCK; 593 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 594 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 595 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), 596 !strconcat(mnemonic, "{w}\t", 597 "{$src2, $dst|$dst, $src2}"), 598 [], IIC_ALU_NONMEM>, OpSize16, LOCK; 599 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 600 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 601 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), 602 !strconcat(mnemonic, "{l}\t", 603 "{$src2, $dst|$dst, $src2}"), 604 [], IIC_ALU_NONMEM>, OpSize32, LOCK; 605 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4}, 606 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 }, 607 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), 608 !strconcat(mnemonic, "{q}\t", 609 "{$src2, $dst|$dst, $src2}"), 610 [], IIC_ALU_NONMEM>, LOCK; 611 612 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 613 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 }, 614 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2), 615 !strconcat(mnemonic, "{b}\t", 616 "{$src2, $dst|$dst, $src2}"), 617 [], IIC_ALU_MEM>, LOCK; 618 619 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 620 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 621 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2), 622 !strconcat(mnemonic, "{w}\t", 623 "{$src2, $dst|$dst, $src2}"), 624 [], IIC_ALU_MEM>, OpSize16, LOCK; 625 626 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 627 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 628 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2), 629 !strconcat(mnemonic, "{l}\t", 630 "{$src2, $dst|$dst, $src2}"), 631 [], IIC_ALU_MEM>, OpSize32, LOCK; 632 633 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4}, 634 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 }, 635 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2), 636 !strconcat(mnemonic, "{q}\t", 637 "{$src2, $dst|$dst, $src2}"), 638 [], IIC_ALU_MEM>, LOCK; 639 640 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 641 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 642 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2), 643 !strconcat(mnemonic, "{w}\t", 644 "{$src2, $dst|$dst, $src2}"), 645 [], IIC_ALU_MEM>, OpSize16, LOCK; 646 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 647 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 648 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2), 649 !strconcat(mnemonic, "{l}\t", 650 "{$src2, $dst|$dst, $src2}"), 651 [], IIC_ALU_MEM>, OpSize32, LOCK; 652 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4}, 653 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 }, 654 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2), 655 !strconcat(mnemonic, "{q}\t", 656 "{$src2, $dst|$dst, $src2}"), 657 [], IIC_ALU_MEM>, LOCK; 658 659 } 660 661 } 662 663 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; 664 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; 665 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; 666 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">; 667 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">; 668 669 // Optimized codegen when the non-memory output is not used. 670 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form, 671 string mnemonic> { 672 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1, 673 SchedRW = [WriteALULd, WriteRMW] in { 674 675 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst), 676 !strconcat(mnemonic, "{b}\t$dst"), 677 [], IIC_UNARY_MEM>, LOCK; 678 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst), 679 !strconcat(mnemonic, "{w}\t$dst"), 680 [], IIC_UNARY_MEM>, OpSize16, LOCK; 681 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst), 682 !strconcat(mnemonic, "{l}\t$dst"), 683 [], IIC_UNARY_MEM>, OpSize32, LOCK; 684 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst), 685 !strconcat(mnemonic, "{q}\t$dst"), 686 [], IIC_UNARY_MEM>, LOCK; 687 } 688 } 689 690 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">; 691 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">; 692 693 // Atomic compare and swap. 694 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic, 695 SDPatternOperator frag, X86MemOperand x86memop, 696 InstrItinClass itin> { 697 let isCodeGenOnly = 1 in { 698 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr), 699 !strconcat(mnemonic, "\t$ptr"), 700 [(frag addr:$ptr)], itin>, TB, LOCK; 701 } 702 } 703 704 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form, 705 string mnemonic, SDPatternOperator frag, 706 InstrItinClass itin8, InstrItinClass itin> { 707 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in { 708 let Defs = [AL, EFLAGS], Uses = [AL] in 709 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap), 710 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"), 711 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK; 712 let Defs = [AX, EFLAGS], Uses = [AX] in 713 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap), 714 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"), 715 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK; 716 let Defs = [EAX, EFLAGS], Uses = [EAX] in 717 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap), 718 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"), 719 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK; 720 let Defs = [RAX, EFLAGS], Uses = [RAX] in 721 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap), 722 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"), 723 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK; 724 } 725 } 726 727 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX], 728 SchedRW = [WriteALULd, WriteRMW] in { 729 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", 730 X86cas8, i64mem, 731 IIC_CMPX_LOCK_8B>; 732 } 733 734 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX], 735 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in { 736 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b", 737 X86cas16, i128mem, 738 IIC_CMPX_LOCK_16B>, REX_W; 739 } 740 741 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", 742 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>; 743 744 // Atomic exchange and add 745 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic, 746 string frag, 747 InstrItinClass itin8, InstrItinClass itin> { 748 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1, 749 SchedRW = [WriteALULd, WriteRMW] in { 750 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst), 751 (ins GR8:$val, i8mem:$ptr), 752 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 753 [(set GR8:$dst, 754 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 755 itin8>; 756 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst), 757 (ins GR16:$val, i16mem:$ptr), 758 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 759 [(set 760 GR16:$dst, 761 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 762 itin>, OpSize16; 763 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst), 764 (ins GR32:$val, i32mem:$ptr), 765 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 766 [(set 767 GR32:$dst, 768 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 769 itin>, OpSize32; 770 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst), 771 (ins GR64:$val, i64mem:$ptr), 772 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 773 [(set 774 GR64:$dst, 775 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 776 itin>; 777 } 778 } 779 780 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add", 781 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>, 782 TB, LOCK; 783 784 /* The following multiclass tries to make sure that in code like 785 * x.store (immediate op x.load(acquire), release) 786 * and 787 * x.store (register op x.load(acquire), release) 788 * an operation directly on memory is generated instead of wasting a register. 789 * It is not automatic as atomic_store/load are only lowered to MOV instructions 790 * extremely late to prevent them from being accidentally reordered in the backend 791 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions) 792 */ 793 multiclass RELEASE_BINOP_MI<SDNode op> { 794 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 795 "#BINOP "#NAME#"8mi PSEUDO!", 796 [(atomic_store_8 addr:$dst, (op 797 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>; 798 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src), 799 "#BINOP "#NAME#"8mr PSEUDO!", 800 [(atomic_store_8 addr:$dst, (op 801 (atomic_load_8 addr:$dst), GR8:$src))]>; 802 // NAME#16 is not generated as 16-bit arithmetic instructions are considered 803 // costly and avoided as far as possible by this backend anyway 804 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 805 "#BINOP "#NAME#"32mi PSEUDO!", 806 [(atomic_store_32 addr:$dst, (op 807 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>; 808 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 809 "#BINOP "#NAME#"32mr PSEUDO!", 810 [(atomic_store_32 addr:$dst, (op 811 (atomic_load_32 addr:$dst), GR32:$src))]>; 812 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 813 "#BINOP "#NAME#"64mi32 PSEUDO!", 814 [(atomic_store_64 addr:$dst, (op 815 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>; 816 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 817 "#BINOP "#NAME#"64mr PSEUDO!", 818 [(atomic_store_64 addr:$dst, (op 819 (atomic_load_64 addr:$dst), GR64:$src))]>; 820 } 821 let Defs = [EFLAGS] in { 822 defm RELEASE_ADD : RELEASE_BINOP_MI<add>; 823 defm RELEASE_AND : RELEASE_BINOP_MI<and>; 824 defm RELEASE_OR : RELEASE_BINOP_MI<or>; 825 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>; 826 // Note: we don't deal with sub, because substractions of constants are 827 // optimized into additions before this code can run. 828 } 829 830 // Same as above, but for floating-point. 831 // FIXME: imm version. 832 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS. 833 // FIXME: This could also handle SIMD operations with *ps and *pd instructions. 834 let usesCustomInserter = 1 in { 835 multiclass RELEASE_FP_BINOP_MI<SDNode op> { 836 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src), 837 "#BINOP "#NAME#"32mr PSEUDO!", 838 [(atomic_store_32 addr:$dst, 839 (i32 (bitconvert (op 840 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))), 841 FR32:$src))))]>, Requires<[HasSSE1]>; 842 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src), 843 "#BINOP "#NAME#"64mr PSEUDO!", 844 [(atomic_store_64 addr:$dst, 845 (i64 (bitconvert (op 846 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))), 847 FR64:$src))))]>, Requires<[HasSSE2]>; 848 } 849 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>; 850 // FIXME: Add fsub, fmul, fdiv, ... 851 } 852 853 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> { 854 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst), 855 "#UNOP "#NAME#"8m PSEUDO!", 856 [(atomic_store_8 addr:$dst, dag8)]>; 857 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst), 858 "#UNOP "#NAME#"16m PSEUDO!", 859 [(atomic_store_16 addr:$dst, dag16)]>; 860 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst), 861 "#UNOP "#NAME#"32m PSEUDO!", 862 [(atomic_store_32 addr:$dst, dag32)]>; 863 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst), 864 "#UNOP "#NAME#"64m PSEUDO!", 865 [(atomic_store_64 addr:$dst, dag64)]>; 866 } 867 868 let Defs = [EFLAGS] in { 869 defm RELEASE_INC : RELEASE_UNOP< 870 (add (atomic_load_8 addr:$dst), (i8 1)), 871 (add (atomic_load_16 addr:$dst), (i16 1)), 872 (add (atomic_load_32 addr:$dst), (i32 1)), 873 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>; 874 defm RELEASE_DEC : RELEASE_UNOP< 875 (add (atomic_load_8 addr:$dst), (i8 -1)), 876 (add (atomic_load_16 addr:$dst), (i16 -1)), 877 (add (atomic_load_32 addr:$dst), (i32 -1)), 878 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>; 879 } 880 /* 881 TODO: These don't work because the type inference of TableGen fails. 882 TODO: find a way to fix it. 883 let Defs = [EFLAGS] in { 884 defm RELEASE_NEG : RELEASE_UNOP< 885 (ineg (atomic_load_8 addr:$dst)), 886 (ineg (atomic_load_16 addr:$dst)), 887 (ineg (atomic_load_32 addr:$dst)), 888 (ineg (atomic_load_64 addr:$dst))>; 889 } 890 // NOT doesn't set flags. 891 defm RELEASE_NOT : RELEASE_UNOP< 892 (not (atomic_load_8 addr:$dst)), 893 (not (atomic_load_16 addr:$dst)), 894 (not (atomic_load_32 addr:$dst)), 895 (not (atomic_load_64 addr:$dst))>; 896 */ 897 898 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src), 899 "#RELEASE_MOV8mi PSEUDO!", 900 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>; 901 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src), 902 "#RELEASE_MOV16mi PSEUDO!", 903 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>; 904 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src), 905 "#RELEASE_MOV32mi PSEUDO!", 906 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>; 907 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src), 908 "#RELEASE_MOV64mi32 PSEUDO!", 909 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>; 910 911 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), 912 "#RELEASE_MOV8mr PSEUDO!", 913 [(atomic_store_8 addr:$dst, GR8 :$src)]>; 914 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), 915 "#RELEASE_MOV16mr PSEUDO!", 916 [(atomic_store_16 addr:$dst, GR16:$src)]>; 917 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), 918 "#RELEASE_MOV32mr PSEUDO!", 919 [(atomic_store_32 addr:$dst, GR32:$src)]>; 920 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), 921 "#RELEASE_MOV64mr PSEUDO!", 922 [(atomic_store_64 addr:$dst, GR64:$src)]>; 923 924 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), 925 "#ACQUIRE_MOV8rm PSEUDO!", 926 [(set GR8:$dst, (atomic_load_8 addr:$src))]>; 927 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), 928 "#ACQUIRE_MOV16rm PSEUDO!", 929 [(set GR16:$dst, (atomic_load_16 addr:$src))]>; 930 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), 931 "#ACQUIRE_MOV32rm PSEUDO!", 932 [(set GR32:$dst, (atomic_load_32 addr:$src))]>; 933 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), 934 "#ACQUIRE_MOV64rm PSEUDO!", 935 [(set GR64:$dst, (atomic_load_64 addr:$src))]>; 936 937 //===----------------------------------------------------------------------===// 938 // DAG Pattern Matching Rules 939 //===----------------------------------------------------------------------===// 940 941 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable 942 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; 943 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>; 944 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>; 945 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; 946 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; 947 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>; 948 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>; 949 950 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), 951 (ADD32ri GR32:$src1, tconstpool:$src2)>; 952 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), 953 (ADD32ri GR32:$src1, tjumptable:$src2)>; 954 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), 955 (ADD32ri GR32:$src1, tglobaladdr:$src2)>; 956 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), 957 (ADD32ri GR32:$src1, texternalsym:$src2)>; 958 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)), 959 (ADD32ri GR32:$src1, mcsym:$src2)>; 960 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)), 961 (ADD32ri GR32:$src1, tblockaddress:$src2)>; 962 963 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), 964 (MOV32mi addr:$dst, tglobaladdr:$src)>; 965 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), 966 (MOV32mi addr:$dst, texternalsym:$src)>; 967 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst), 968 (MOV32mi addr:$dst, mcsym:$src)>; 969 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst), 970 (MOV32mi addr:$dst, tblockaddress:$src)>; 971 972 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small 973 // code model mode, should use 'movabs'. FIXME: This is really a hack, the 974 // 'movabs' predicate should handle this sort of thing. 975 def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 976 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>; 977 def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 978 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>; 979 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 980 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>; 981 def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 982 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>; 983 def : Pat<(i64 (X86Wrapper mcsym:$dst)), 984 (MOV64ri mcsym:$dst)>, Requires<[FarData]>; 985 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 986 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>; 987 988 // In kernel code model, we can get the address of a label 989 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of 990 // the MOV64ri32 should accept these. 991 def : Pat<(i64 (X86Wrapper tconstpool :$dst)), 992 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>; 993 def : Pat<(i64 (X86Wrapper tjumptable :$dst)), 994 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>; 995 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), 996 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>; 997 def : Pat<(i64 (X86Wrapper texternalsym:$dst)), 998 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>; 999 def : Pat<(i64 (X86Wrapper mcsym:$dst)), 1000 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>; 1001 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)), 1002 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>; 1003 1004 // If we have small model and -static mode, it is safe to store global addresses 1005 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate 1006 // for MOV64mi32 should handle this sort of thing. 1007 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), 1008 (MOV64mi32 addr:$dst, tconstpool:$src)>, 1009 Requires<[NearData, IsStatic]>; 1010 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), 1011 (MOV64mi32 addr:$dst, tjumptable:$src)>, 1012 Requires<[NearData, IsStatic]>; 1013 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), 1014 (MOV64mi32 addr:$dst, tglobaladdr:$src)>, 1015 Requires<[NearData, IsStatic]>; 1016 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), 1017 (MOV64mi32 addr:$dst, texternalsym:$src)>, 1018 Requires<[NearData, IsStatic]>; 1019 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst), 1020 (MOV64mi32 addr:$dst, mcsym:$src)>, 1021 Requires<[NearData, IsStatic]>; 1022 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst), 1023 (MOV64mi32 addr:$dst, tblockaddress:$src)>, 1024 Requires<[NearData, IsStatic]>; 1025 1026 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>; 1027 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>; 1028 1029 // Calls 1030 1031 // tls has some funny stuff here... 1032 // This corresponds to movabs $foo@tpoff, %rax 1033 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)), 1034 (MOV64ri32 tglobaltlsaddr :$dst)>; 1035 // This corresponds to add $foo@tpoff, %rax 1036 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)), 1037 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>; 1038 1039 1040 // Direct PC relative function call for small code model. 32-bit displacement 1041 // sign extended to 64-bit. 1042 def : Pat<(X86call (i64 tglobaladdr:$dst)), 1043 (CALL64pcrel32 tglobaladdr:$dst)>; 1044 def : Pat<(X86call (i64 texternalsym:$dst)), 1045 (CALL64pcrel32 texternalsym:$dst)>; 1046 1047 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they 1048 // can never use callee-saved registers. That is the purpose of the GR64_TC 1049 // register classes. 1050 // 1051 // The only volatile register that is never used by the calling convention is 1052 // %r11. This happens when calling a vararg function with 6 arguments. 1053 // 1054 // Match an X86tcret that uses less than 7 volatile registers. 1055 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 1056 (X86tcret node:$ptr, node:$off), [{ 1057 // X86tcret args: (*chain, ptr, imm, regs..., glue) 1058 unsigned NumRegs = 0; 1059 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 1060 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 1061 return false; 1062 return true; 1063 }]>; 1064 1065 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1066 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>, 1067 Requires<[Not64BitMode]>; 1068 1069 // FIXME: This is disabled for 32-bit PIC mode because the global base 1070 // register which is part of the address mode may be assigned a 1071 // callee-saved register. 1072 def : Pat<(X86tcret (load addr:$dst), imm:$off), 1073 (TCRETURNmi addr:$dst, imm:$off)>, 1074 Requires<[Not64BitMode, IsNotPIC]>; 1075 1076 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), 1077 (TCRETURNdi tglobaladdr:$dst, imm:$off)>, 1078 Requires<[NotLP64]>; 1079 1080 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), 1081 (TCRETURNdi texternalsym:$dst, imm:$off)>, 1082 Requires<[NotLP64]>; 1083 1084 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), 1085 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, 1086 Requires<[In64BitMode]>; 1087 1088 // Don't fold loads into X86tcret requiring more than 6 regs. 1089 // There wouldn't be enough scratch registers for base+index. 1090 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off), 1091 (TCRETURNmi64 addr:$dst, imm:$off)>, 1092 Requires<[In64BitMode]>; 1093 1094 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), 1095 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, 1096 Requires<[IsLP64]>; 1097 1098 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), 1099 (TCRETURNdi64 texternalsym:$dst, imm:$off)>, 1100 Requires<[IsLP64]>; 1101 1102 // Normal calls, with various flavors of addresses. 1103 def : Pat<(X86call (i32 tglobaladdr:$dst)), 1104 (CALLpcrel32 tglobaladdr:$dst)>; 1105 def : Pat<(X86call (i32 texternalsym:$dst)), 1106 (CALLpcrel32 texternalsym:$dst)>; 1107 def : Pat<(X86call (i32 imm:$dst)), 1108 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>; 1109 1110 // Comparisons. 1111 1112 // TEST R,R is smaller than CMP R,0 1113 def : Pat<(X86cmp GR8:$src1, 0), 1114 (TEST8rr GR8:$src1, GR8:$src1)>; 1115 def : Pat<(X86cmp GR16:$src1, 0), 1116 (TEST16rr GR16:$src1, GR16:$src1)>; 1117 def : Pat<(X86cmp GR32:$src1, 0), 1118 (TEST32rr GR32:$src1, GR32:$src1)>; 1119 def : Pat<(X86cmp GR64:$src1, 0), 1120 (TEST64rr GR64:$src1, GR64:$src1)>; 1121 1122 // Conditional moves with folded loads with operands swapped and conditions 1123 // inverted. 1124 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32, 1125 Instruction Inst64> { 1126 let Predicates = [HasCMov] in { 1127 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS), 1128 (Inst16 GR16:$src2, addr:$src1)>; 1129 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS), 1130 (Inst32 GR32:$src2, addr:$src1)>; 1131 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS), 1132 (Inst64 GR64:$src2, addr:$src1)>; 1133 } 1134 } 1135 1136 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>; 1137 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>; 1138 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>; 1139 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>; 1140 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>; 1141 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>; 1142 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>; 1143 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>; 1144 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>; 1145 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>; 1146 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>; 1147 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>; 1148 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>; 1149 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>; 1150 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>; 1151 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>; 1152 1153 // zextload bool -> zextload byte 1154 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>; 1155 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>; 1156 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>; 1157 def : Pat<(zextloadi64i1 addr:$src), 1158 (SUBREG_TO_REG (i64 0), 1159 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>; 1160 1161 // extload bool -> extload byte 1162 // When extloading from 16-bit and smaller memory locations into 64-bit 1163 // registers, use zero-extending loads so that the entire 64-bit register is 1164 // defined, avoiding partial-register updates. 1165 1166 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; 1167 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; 1168 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 1169 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; 1170 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; 1171 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; 1172 1173 // For other extloads, use subregs, since the high contents of the register are 1174 // defined after an extload. 1175 def : Pat<(extloadi64i1 addr:$src), 1176 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1177 def : Pat<(extloadi64i8 addr:$src), 1178 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; 1179 def : Pat<(extloadi64i16 addr:$src), 1180 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; 1181 def : Pat<(extloadi64i32 addr:$src), 1182 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; 1183 1184 // anyext. Define these to do an explicit zero-extend to 1185 // avoid partial-register updates. 1186 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG 1187 (MOVZX32rr8 GR8 :$src), sub_16bit)>; 1188 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; 1189 1190 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. 1191 def : Pat<(i32 (anyext GR16:$src)), 1192 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; 1193 1194 def : Pat<(i64 (anyext GR8 :$src)), 1195 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; 1196 def : Pat<(i64 (anyext GR16:$src)), 1197 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; 1198 def : Pat<(i64 (anyext GR32:$src)), 1199 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1200 1201 1202 // Any instruction that defines a 32-bit result leaves the high half of the 1203 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 1204 // be copying from a truncate. And x86's cmov doesn't do anything if the 1205 // condition is false. But any other 32-bit operation will zero-extend 1206 // up to 64 bits. 1207 def def32 : PatLeaf<(i32 GR32:$src), [{ 1208 return N->getOpcode() != ISD::TRUNCATE && 1209 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 1210 N->getOpcode() != ISD::CopyFromReg && 1211 N->getOpcode() != ISD::AssertSext && 1212 N->getOpcode() != X86ISD::CMOV; 1213 }]>; 1214 1215 // In the case of a 32-bit def that is known to implicitly zero-extend, 1216 // we can use a SUBREG_TO_REG. 1217 def : Pat<(i64 (zext def32:$src)), 1218 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; 1219 1220 //===----------------------------------------------------------------------===// 1221 // Pattern match OR as ADD 1222 //===----------------------------------------------------------------------===// 1223 1224 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be 1225 // 3-addressified into an LEA instruction to avoid copies. However, we also 1226 // want to finally emit these instructions as an or at the end of the code 1227 // generator to make the generated code easier to read. To do this, we select 1228 // into "disjoint bits" pseudo ops. 1229 1230 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 1231 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 1232 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1233 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 1234 1235 APInt KnownZero0, KnownOne0; 1236 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0); 1237 APInt KnownZero1, KnownOne1; 1238 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0); 1239 return (~KnownZero0 & ~KnownZero1) == 0; 1240 }]>; 1241 1242 1243 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits. 1244 // Try this before the selecting to OR. 1245 let AddedComplexity = 5, SchedRW = [WriteALU] in { 1246 1247 let isConvertibleToThreeAddress = 1, 1248 Constraints = "$src1 = $dst", Defs = [EFLAGS] in { 1249 let isCommutable = 1 in { 1250 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1251 "", // orw/addw REG, REG 1252 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>; 1253 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1254 "", // orl/addl REG, REG 1255 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>; 1256 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1257 "", // orq/addq REG, REG 1258 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>; 1259 } // isCommutable 1260 1261 // NOTE: These are order specific, we want the ri8 forms to be listed 1262 // first so that they are slightly preferred to the ri forms. 1263 1264 def ADD16ri8_DB : I<0, Pseudo, 1265 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), 1266 "", // orw/addw REG, imm8 1267 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>; 1268 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), 1269 "", // orw/addw REG, imm 1270 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>; 1271 1272 def ADD32ri8_DB : I<0, Pseudo, 1273 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), 1274 "", // orl/addl REG, imm8 1275 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>; 1276 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), 1277 "", // orl/addl REG, imm 1278 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>; 1279 1280 1281 def ADD64ri8_DB : I<0, Pseudo, 1282 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), 1283 "", // orq/addq REG, imm8 1284 [(set GR64:$dst, (or_is_add GR64:$src1, 1285 i64immSExt8:$src2))]>; 1286 def ADD64ri32_DB : I<0, Pseudo, 1287 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), 1288 "", // orq/addq REG, imm 1289 [(set GR64:$dst, (or_is_add GR64:$src1, 1290 i64immSExt32:$src2))]>; 1291 } 1292 } // AddedComplexity, SchedRW 1293 1294 1295 //===----------------------------------------------------------------------===// 1296 // Some peepholes 1297 //===----------------------------------------------------------------------===// 1298 1299 // Odd encoding trick: -128 fits into an 8-bit immediate field while 1300 // +128 doesn't, so in this special case use a sub instead of an add. 1301 def : Pat<(add GR16:$src1, 128), 1302 (SUB16ri8 GR16:$src1, -128)>; 1303 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst), 1304 (SUB16mi8 addr:$dst, -128)>; 1305 1306 def : Pat<(add GR32:$src1, 128), 1307 (SUB32ri8 GR32:$src1, -128)>; 1308 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst), 1309 (SUB32mi8 addr:$dst, -128)>; 1310 1311 def : Pat<(add GR64:$src1, 128), 1312 (SUB64ri8 GR64:$src1, -128)>; 1313 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst), 1314 (SUB64mi8 addr:$dst, -128)>; 1315 1316 // The same trick applies for 32-bit immediate fields in 64-bit 1317 // instructions. 1318 def : Pat<(add GR64:$src1, 0x0000000080000000), 1319 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>; 1320 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst), 1321 (SUB64mi32 addr:$dst, 0xffffffff80000000)>; 1322 1323 // To avoid needing to materialize an immediate in a register, use a 32-bit and 1324 // with implicit zero-extension instead of a 64-bit and if the immediate has at 1325 // least 32 bits of leading zeros. If in addition the last 32 bits can be 1326 // represented with a sign extension of a 8 bit constant, use that. 1327 // This can also reduce instruction size by eliminating the need for the REX 1328 // prefix. 1329 1330 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32. 1331 let AddedComplexity = 1 in { 1332 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm), 1333 (SUBREG_TO_REG 1334 (i64 0), 1335 (AND32ri8 1336 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1337 (i32 (GetLo8XForm imm:$imm))), 1338 sub_32bit)>; 1339 1340 def : Pat<(and GR64:$src, i64immZExt32:$imm), 1341 (SUBREG_TO_REG 1342 (i64 0), 1343 (AND32ri 1344 (EXTRACT_SUBREG GR64:$src, sub_32bit), 1345 (i32 (GetLo32XForm imm:$imm))), 1346 sub_32bit)>; 1347 } // AddedComplexity = 1 1348 1349 1350 // AddedComplexity is needed due to the increased complexity on the 1351 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all 1352 // the MOVZX patterns keeps thems together in DAGIsel tables. 1353 let AddedComplexity = 1 in { 1354 // r & (2^16-1) ==> movz 1355 def : Pat<(and GR32:$src1, 0xffff), 1356 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>; 1357 // r & (2^8-1) ==> movz 1358 def : Pat<(and GR32:$src1, 0xff), 1359 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1, 1360 GR32_ABCD)), 1361 sub_8bit))>, 1362 Requires<[Not64BitMode]>; 1363 // r & (2^8-1) ==> movz 1364 def : Pat<(and GR16:$src1, 0xff), 1365 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG 1366 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), 1367 sub_16bit)>, 1368 Requires<[Not64BitMode]>; 1369 1370 // r & (2^32-1) ==> movz 1371 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), 1372 (SUBREG_TO_REG (i64 0), 1373 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), 1374 sub_32bit)>; 1375 // r & (2^16-1) ==> movz 1376 def : Pat<(and GR64:$src, 0xffff), 1377 (SUBREG_TO_REG (i64 0), 1378 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), 1379 sub_32bit)>; 1380 // r & (2^8-1) ==> movz 1381 def : Pat<(and GR64:$src, 0xff), 1382 (SUBREG_TO_REG (i64 0), 1383 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), 1384 sub_32bit)>; 1385 // r & (2^8-1) ==> movz 1386 def : Pat<(and GR32:$src1, 0xff), 1387 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>, 1388 Requires<[In64BitMode]>; 1389 // r & (2^8-1) ==> movz 1390 def : Pat<(and GR16:$src1, 0xff), 1391 (EXTRACT_SUBREG (MOVZX32rr8 (i8 1392 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, 1393 Requires<[In64BitMode]>; 1394 } // AddedComplexity = 1 1395 1396 1397 // sext_inreg patterns 1398 def : Pat<(sext_inreg GR32:$src, i16), 1399 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>; 1400 def : Pat<(sext_inreg GR32:$src, i8), 1401 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1402 GR32_ABCD)), 1403 sub_8bit))>, 1404 Requires<[Not64BitMode]>; 1405 1406 def : Pat<(sext_inreg GR16:$src, i8), 1407 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG 1408 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), 1409 sub_16bit)>, 1410 Requires<[Not64BitMode]>; 1411 1412 def : Pat<(sext_inreg GR64:$src, i32), 1413 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>; 1414 def : Pat<(sext_inreg GR64:$src, i16), 1415 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>; 1416 def : Pat<(sext_inreg GR64:$src, i8), 1417 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>; 1418 def : Pat<(sext_inreg GR32:$src, i8), 1419 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, 1420 Requires<[In64BitMode]>; 1421 def : Pat<(sext_inreg GR16:$src, i8), 1422 (EXTRACT_SUBREG (MOVSX32rr8 1423 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, 1424 Requires<[In64BitMode]>; 1425 1426 // sext, sext_load, zext, zext_load 1427 def: Pat<(i16 (sext GR8:$src)), 1428 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>; 1429 def: Pat<(sextloadi16i8 addr:$src), 1430 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>; 1431 def: Pat<(i16 (zext GR8:$src)), 1432 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>; 1433 def: Pat<(zextloadi16i8 addr:$src), 1434 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; 1435 1436 // trunc patterns 1437 def : Pat<(i16 (trunc GR32:$src)), 1438 (EXTRACT_SUBREG GR32:$src, sub_16bit)>; 1439 def : Pat<(i8 (trunc GR32:$src)), 1440 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1441 sub_8bit)>, 1442 Requires<[Not64BitMode]>; 1443 def : Pat<(i8 (trunc GR16:$src)), 1444 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1445 sub_8bit)>, 1446 Requires<[Not64BitMode]>; 1447 def : Pat<(i32 (trunc GR64:$src)), 1448 (EXTRACT_SUBREG GR64:$src, sub_32bit)>; 1449 def : Pat<(i16 (trunc GR64:$src)), 1450 (EXTRACT_SUBREG GR64:$src, sub_16bit)>; 1451 def : Pat<(i8 (trunc GR64:$src)), 1452 (EXTRACT_SUBREG GR64:$src, sub_8bit)>; 1453 def : Pat<(i8 (trunc GR32:$src)), 1454 (EXTRACT_SUBREG GR32:$src, sub_8bit)>, 1455 Requires<[In64BitMode]>; 1456 def : Pat<(i8 (trunc GR16:$src)), 1457 (EXTRACT_SUBREG GR16:$src, sub_8bit)>, 1458 Requires<[In64BitMode]>; 1459 1460 // h-register tricks 1461 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), 1462 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1463 sub_8bit_hi)>, 1464 Requires<[Not64BitMode]>; 1465 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), 1466 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1467 sub_8bit_hi)>, 1468 Requires<[Not64BitMode]>; 1469 def : Pat<(srl GR16:$src, (i8 8)), 1470 (EXTRACT_SUBREG 1471 (MOVZX32rr8 1472 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1473 sub_8bit_hi)), 1474 sub_16bit)>, 1475 Requires<[Not64BitMode]>; 1476 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1477 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1478 GR16_ABCD)), 1479 sub_8bit_hi))>, 1480 Requires<[Not64BitMode]>; 1481 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1482 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, 1483 GR16_ABCD)), 1484 sub_8bit_hi))>, 1485 Requires<[Not64BitMode]>; 1486 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1487 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1488 GR32_ABCD)), 1489 sub_8bit_hi))>, 1490 Requires<[Not64BitMode]>; 1491 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1492 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1493 GR32_ABCD)), 1494 sub_8bit_hi))>, 1495 Requires<[Not64BitMode]>; 1496 1497 // h-register tricks. 1498 // For now, be conservative on x86-64 and use an h-register extract only if the 1499 // value is immediately zero-extended or stored, which are somewhat common 1500 // cases. This uses a bunch of code to prevent a register requiring a REX prefix 1501 // from being allocated in the same instruction as the h register, as there's 1502 // currently no way to describe this requirement to the register allocator. 1503 1504 // h-register extract and zero-extend. 1505 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), 1506 (SUBREG_TO_REG 1507 (i64 0), 1508 (MOVZX32_NOREXrr8 1509 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1510 sub_8bit_hi)), 1511 sub_32bit)>; 1512 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), 1513 (MOVZX32_NOREXrr8 1514 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1515 sub_8bit_hi))>, 1516 Requires<[In64BitMode]>; 1517 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), 1518 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, 1519 GR32_ABCD)), 1520 sub_8bit_hi))>, 1521 Requires<[In64BitMode]>; 1522 def : Pat<(srl GR16:$src, (i8 8)), 1523 (EXTRACT_SUBREG 1524 (MOVZX32_NOREXrr8 1525 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1526 sub_8bit_hi)), 1527 sub_16bit)>, 1528 Requires<[In64BitMode]>; 1529 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), 1530 (MOVZX32_NOREXrr8 1531 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1532 sub_8bit_hi))>, 1533 Requires<[In64BitMode]>; 1534 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), 1535 (MOVZX32_NOREXrr8 1536 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1537 sub_8bit_hi))>, 1538 Requires<[In64BitMode]>; 1539 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), 1540 (SUBREG_TO_REG 1541 (i64 0), 1542 (MOVZX32_NOREXrr8 1543 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1544 sub_8bit_hi)), 1545 sub_32bit)>; 1546 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), 1547 (SUBREG_TO_REG 1548 (i64 0), 1549 (MOVZX32_NOREXrr8 1550 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1551 sub_8bit_hi)), 1552 sub_32bit)>; 1553 1554 // h-register extract and store. 1555 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), 1556 (MOV8mr_NOREX 1557 addr:$dst, 1558 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), 1559 sub_8bit_hi))>; 1560 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), 1561 (MOV8mr_NOREX 1562 addr:$dst, 1563 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), 1564 sub_8bit_hi))>, 1565 Requires<[In64BitMode]>; 1566 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), 1567 (MOV8mr_NOREX 1568 addr:$dst, 1569 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), 1570 sub_8bit_hi))>, 1571 Requires<[In64BitMode]>; 1572 1573 1574 // (shl x, 1) ==> (add x, x) 1575 // Note that if x is undef (immediate or otherwise), we could theoretically 1576 // end up with the two uses of x getting different values, producing a result 1577 // where the least significant bit is not 0. However, the probability of this 1578 // happening is considered low enough that this is officially not a 1579 // "real problem". 1580 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; 1581 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; 1582 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; 1583 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; 1584 1585 // Helper imms that check if a mask doesn't change significant shift bits. 1586 def immShift32 : ImmLeaf<i8, [{ 1587 return countTrailingOnes<uint64_t>(Imm) >= 5; 1588 }]>; 1589 def immShift64 : ImmLeaf<i8, [{ 1590 return countTrailingOnes<uint64_t>(Imm) >= 6; 1591 }]>; 1592 1593 // Shift amount is implicitly masked. 1594 multiclass MaskedShiftAmountPats<SDNode frag, string name> { 1595 // (shift x (and y, 31)) ==> (shift x, y) 1596 def : Pat<(frag GR8:$src1, (and CL, immShift32)), 1597 (!cast<Instruction>(name # "8rCL") GR8:$src1)>; 1598 def : Pat<(frag GR16:$src1, (and CL, immShift32)), 1599 (!cast<Instruction>(name # "16rCL") GR16:$src1)>; 1600 def : Pat<(frag GR32:$src1, (and CL, immShift32)), 1601 (!cast<Instruction>(name # "32rCL") GR32:$src1)>; 1602 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst), 1603 (!cast<Instruction>(name # "8mCL") addr:$dst)>; 1604 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst), 1605 (!cast<Instruction>(name # "16mCL") addr:$dst)>; 1606 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst), 1607 (!cast<Instruction>(name # "32mCL") addr:$dst)>; 1608 1609 // (shift x (and y, 63)) ==> (shift x, y) 1610 def : Pat<(frag GR64:$src1, (and CL, immShift64)), 1611 (!cast<Instruction>(name # "64rCL") GR64:$src1)>; 1612 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst), 1613 (!cast<Instruction>(name # "64mCL") addr:$dst)>; 1614 } 1615 1616 defm : MaskedShiftAmountPats<shl, "SHL">; 1617 defm : MaskedShiftAmountPats<srl, "SHR">; 1618 defm : MaskedShiftAmountPats<sra, "SAR">; 1619 defm : MaskedShiftAmountPats<rotl, "ROL">; 1620 defm : MaskedShiftAmountPats<rotr, "ROR">; 1621 1622 // (anyext (setcc_carry)) -> (setcc_carry) 1623 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1624 (SETB_C16r)>; 1625 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), 1626 (SETB_C32r)>; 1627 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))), 1628 (SETB_C32r)>; 1629 1630 1631 1632 1633 //===----------------------------------------------------------------------===// 1634 // EFLAGS-defining Patterns 1635 //===----------------------------------------------------------------------===// 1636 1637 // add reg, reg 1638 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>; 1639 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>; 1640 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>; 1641 1642 // add reg, mem 1643 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)), 1644 (ADD8rm GR8:$src1, addr:$src2)>; 1645 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)), 1646 (ADD16rm GR16:$src1, addr:$src2)>; 1647 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)), 1648 (ADD32rm GR32:$src1, addr:$src2)>; 1649 1650 // add reg, imm 1651 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>; 1652 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>; 1653 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>; 1654 def : Pat<(add GR16:$src1, i16immSExt8:$src2), 1655 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>; 1656 def : Pat<(add GR32:$src1, i32immSExt8:$src2), 1657 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; 1658 1659 // sub reg, reg 1660 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>; 1661 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>; 1662 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>; 1663 1664 // sub reg, mem 1665 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)), 1666 (SUB8rm GR8:$src1, addr:$src2)>; 1667 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)), 1668 (SUB16rm GR16:$src1, addr:$src2)>; 1669 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)), 1670 (SUB32rm GR32:$src1, addr:$src2)>; 1671 1672 // sub reg, imm 1673 def : Pat<(sub GR8:$src1, imm:$src2), 1674 (SUB8ri GR8:$src1, imm:$src2)>; 1675 def : Pat<(sub GR16:$src1, imm:$src2), 1676 (SUB16ri GR16:$src1, imm:$src2)>; 1677 def : Pat<(sub GR32:$src1, imm:$src2), 1678 (SUB32ri GR32:$src1, imm:$src2)>; 1679 def : Pat<(sub GR16:$src1, i16immSExt8:$src2), 1680 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>; 1681 def : Pat<(sub GR32:$src1, i32immSExt8:$src2), 1682 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; 1683 1684 // sub 0, reg 1685 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>; 1686 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>; 1687 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>; 1688 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>; 1689 1690 // mul reg, reg 1691 def : Pat<(mul GR16:$src1, GR16:$src2), 1692 (IMUL16rr GR16:$src1, GR16:$src2)>; 1693 def : Pat<(mul GR32:$src1, GR32:$src2), 1694 (IMUL32rr GR32:$src1, GR32:$src2)>; 1695 1696 // mul reg, mem 1697 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)), 1698 (IMUL16rm GR16:$src1, addr:$src2)>; 1699 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)), 1700 (IMUL32rm GR32:$src1, addr:$src2)>; 1701 1702 // mul reg, imm 1703 def : Pat<(mul GR16:$src1, imm:$src2), 1704 (IMUL16rri GR16:$src1, imm:$src2)>; 1705 def : Pat<(mul GR32:$src1, imm:$src2), 1706 (IMUL32rri GR32:$src1, imm:$src2)>; 1707 def : Pat<(mul GR16:$src1, i16immSExt8:$src2), 1708 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>; 1709 def : Pat<(mul GR32:$src1, i32immSExt8:$src2), 1710 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>; 1711 1712 // reg = mul mem, imm 1713 def : Pat<(mul (loadi16 addr:$src1), imm:$src2), 1714 (IMUL16rmi addr:$src1, imm:$src2)>; 1715 def : Pat<(mul (loadi32 addr:$src1), imm:$src2), 1716 (IMUL32rmi addr:$src1, imm:$src2)>; 1717 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2), 1718 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>; 1719 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2), 1720 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; 1721 1722 // Patterns for nodes that do not produce flags, for instructions that do. 1723 1724 // addition 1725 def : Pat<(add GR64:$src1, GR64:$src2), 1726 (ADD64rr GR64:$src1, GR64:$src2)>; 1727 def : Pat<(add GR64:$src1, i64immSExt8:$src2), 1728 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; 1729 def : Pat<(add GR64:$src1, i64immSExt32:$src2), 1730 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>; 1731 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)), 1732 (ADD64rm GR64:$src1, addr:$src2)>; 1733 1734 // subtraction 1735 def : Pat<(sub GR64:$src1, GR64:$src2), 1736 (SUB64rr GR64:$src1, GR64:$src2)>; 1737 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)), 1738 (SUB64rm GR64:$src1, addr:$src2)>; 1739 def : Pat<(sub GR64:$src1, i64immSExt8:$src2), 1740 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; 1741 def : Pat<(sub GR64:$src1, i64immSExt32:$src2), 1742 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; 1743 1744 // Multiply 1745 def : Pat<(mul GR64:$src1, GR64:$src2), 1746 (IMUL64rr GR64:$src1, GR64:$src2)>; 1747 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)), 1748 (IMUL64rm GR64:$src1, addr:$src2)>; 1749 def : Pat<(mul GR64:$src1, i64immSExt8:$src2), 1750 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>; 1751 def : Pat<(mul GR64:$src1, i64immSExt32:$src2), 1752 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>; 1753 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2), 1754 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>; 1755 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2), 1756 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>; 1757 1758 // Increment/Decrement reg. 1759 // Do not make INC/DEC if it is slow 1760 let Predicates = [NotSlowIncDec] in { 1761 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>; 1762 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>; 1763 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>; 1764 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>; 1765 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>; 1766 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>; 1767 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>; 1768 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>; 1769 } 1770 1771 // or reg/reg. 1772 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>; 1773 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>; 1774 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>; 1775 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>; 1776 1777 // or reg/mem 1778 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)), 1779 (OR8rm GR8:$src1, addr:$src2)>; 1780 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)), 1781 (OR16rm GR16:$src1, addr:$src2)>; 1782 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)), 1783 (OR32rm GR32:$src1, addr:$src2)>; 1784 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)), 1785 (OR64rm GR64:$src1, addr:$src2)>; 1786 1787 // or reg/imm 1788 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>; 1789 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>; 1790 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>; 1791 def : Pat<(or GR16:$src1, i16immSExt8:$src2), 1792 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1793 def : Pat<(or GR32:$src1, i32immSExt8:$src2), 1794 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1795 def : Pat<(or GR64:$src1, i64immSExt8:$src2), 1796 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1797 def : Pat<(or GR64:$src1, i64immSExt32:$src2), 1798 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1799 1800 // xor reg/reg 1801 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>; 1802 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>; 1803 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>; 1804 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>; 1805 1806 // xor reg/mem 1807 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)), 1808 (XOR8rm GR8:$src1, addr:$src2)>; 1809 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)), 1810 (XOR16rm GR16:$src1, addr:$src2)>; 1811 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)), 1812 (XOR32rm GR32:$src1, addr:$src2)>; 1813 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)), 1814 (XOR64rm GR64:$src1, addr:$src2)>; 1815 1816 // xor reg/imm 1817 def : Pat<(xor GR8:$src1, imm:$src2), 1818 (XOR8ri GR8:$src1, imm:$src2)>; 1819 def : Pat<(xor GR16:$src1, imm:$src2), 1820 (XOR16ri GR16:$src1, imm:$src2)>; 1821 def : Pat<(xor GR32:$src1, imm:$src2), 1822 (XOR32ri GR32:$src1, imm:$src2)>; 1823 def : Pat<(xor GR16:$src1, i16immSExt8:$src2), 1824 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>; 1825 def : Pat<(xor GR32:$src1, i32immSExt8:$src2), 1826 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>; 1827 def : Pat<(xor GR64:$src1, i64immSExt8:$src2), 1828 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>; 1829 def : Pat<(xor GR64:$src1, i64immSExt32:$src2), 1830 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>; 1831 1832 // and reg/reg 1833 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>; 1834 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>; 1835 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>; 1836 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>; 1837 1838 // and reg/mem 1839 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)), 1840 (AND8rm GR8:$src1, addr:$src2)>; 1841 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)), 1842 (AND16rm GR16:$src1, addr:$src2)>; 1843 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)), 1844 (AND32rm GR32:$src1, addr:$src2)>; 1845 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)), 1846 (AND64rm GR64:$src1, addr:$src2)>; 1847 1848 // and reg/imm 1849 def : Pat<(and GR8:$src1, imm:$src2), 1850 (AND8ri GR8:$src1, imm:$src2)>; 1851 def : Pat<(and GR16:$src1, imm:$src2), 1852 (AND16ri GR16:$src1, imm:$src2)>; 1853 def : Pat<(and GR32:$src1, imm:$src2), 1854 (AND32ri GR32:$src1, imm:$src2)>; 1855 def : Pat<(and GR16:$src1, i16immSExt8:$src2), 1856 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>; 1857 def : Pat<(and GR32:$src1, i32immSExt8:$src2), 1858 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>; 1859 def : Pat<(and GR64:$src1, i64immSExt8:$src2), 1860 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; 1861 def : Pat<(and GR64:$src1, i64immSExt32:$src2), 1862 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; 1863 1864 // Bit scan instruction patterns to match explicit zero-undef behavior. 1865 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>; 1866 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>; 1867 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>; 1868 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>; 1869 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>; 1870 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>; 1871 1872 // When HasMOVBE is enabled it is possible to get a non-legalized 1873 // register-register 16 bit bswap. This maps it to a ROL instruction. 1874 let Predicates = [HasMOVBE] in { 1875 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>; 1876 } 1877
