1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 2 3 define <2 x float> @ucvt(<2 x i32> %a) nounwind readnone ssp { 4 ; CHECK-LABEL: ucvt: 5 ; CHECK: ucvtf.2s v0, v0 6 ; CHECK: ret 7 8 %vcvt.i = uitofp <2 x i32> %a to <2 x float> 9 ret <2 x float> %vcvt.i 10 } 11 12 define <2 x float> @scvt(<2 x i32> %a) nounwind readnone ssp { 13 ; CHECK-LABEL: scvt: 14 ; CHECK: scvtf.2s v0, v0 15 ; CHECK: ret 16 %vcvt.i = sitofp <2 x i32> %a to <2 x float> 17 ret <2 x float> %vcvt.i 18 } 19 20 define <4 x float> @ucvtq(<4 x i32> %a) nounwind readnone ssp { 21 ; CHECK-LABEL: ucvtq: 22 ; CHECK: ucvtf.4s v0, v0 23 ; CHECK: ret 24 %vcvt.i = uitofp <4 x i32> %a to <4 x float> 25 ret <4 x float> %vcvt.i 26 } 27 28 define <4 x float> @scvtq(<4 x i32> %a) nounwind readnone ssp { 29 ; CHECK-LABEL: scvtq: 30 ; CHECK: scvtf.4s v0, v0 31 ; CHECK: ret 32 %vcvt.i = sitofp <4 x i32> %a to <4 x float> 33 ret <4 x float> %vcvt.i 34 } 35 36 define <4 x float> @cvtf16(<4 x i16> %a) nounwind readnone ssp { 37 ; CHECK-LABEL: cvtf16: 38 ; CHECK: fcvtl v0.4s, v0.4h 39 ; CHECK-NEXT: ret 40 %vcvt1.i = tail call <4 x float> @llvm.aarch64.neon.vcvthf2fp(<4 x i16> %a) nounwind 41 ret <4 x float> %vcvt1.i 42 } 43 44 define <4 x float> @cvtf16_high(<8 x i16> %a) nounwind readnone ssp { 45 ; CHECK-LABEL: cvtf16_high: 46 ; CHECK: fcvtl2 v0.4s, v0.8h 47 ; CHECK-NEXT: ret 48 %in = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 49 %vcvt1.i = tail call <4 x float> @llvm.aarch64.neon.vcvthf2fp(<4 x i16> %in) nounwind 50 ret <4 x float> %vcvt1.i 51 } 52 53 54 55 define <4 x i16> @cvtf16f32(<4 x float> %a) nounwind readnone ssp { 56 ; CHECK-LABEL: cvtf16f32: 57 ; CHECK: fcvtn v0.4h, v0.4s 58 ; CHECK-NEXT: ret 59 %vcvt1.i = tail call <4 x i16> @llvm.aarch64.neon.vcvtfp2hf(<4 x float> %a) nounwind 60 ret <4 x i16> %vcvt1.i 61 } 62 63 define <8 x i16> @cvtf16f32_high(<4 x i16> %low, <4 x float> %high_big) { 64 ; CHECK-LABEL: cvtf16f32_high: 65 ; CHECK: fcvtn2 v0.8h, v1.4s 66 ; CHECK-NEXT: ret 67 %high = call <4 x i16> @llvm.aarch64.neon.vcvtfp2hf(<4 x float> %high_big) 68 %res = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 69 ret <8 x i16> %res 70 } 71 72 declare <4 x float> @llvm.aarch64.neon.vcvthf2fp(<4 x i16>) nounwind readnone 73 declare <4 x i16> @llvm.aarch64.neon.vcvtfp2hf(<4 x float>) nounwind readnone 74
