1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s 2 ; 3 ; 4 ; Most SALU instructions ignore control flow, so we need to make sure 5 ; they don't overwrite values from other blocks. 6 7 ; If the branch decision is made based on a value in an SGPR then all 8 ; threads will execute the same code paths, so we don't need to worry 9 ; about instructions in different blocks overwriting each other. 10 ; SI-LABEL: {{^}}sgpr_if_else_salu_br: 11 ; SI: s_add 12 ; SI: s_add 13 14 define void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { 15 entry: 16 %0 = icmp eq i32 %a, 0 17 br i1 %0, label %if, label %else 18 19 if: 20 %1 = add i32 %b, %c 21 br label %endif 22 23 else: 24 %2 = add i32 %d, %e 25 br label %endif 26 27 endif: 28 %3 = phi i32 [%1, %if], [%2, %else] 29 %4 = add i32 %3, %a 30 store i32 %4, i32 addrspace(1)* %out 31 ret void 32 } 33 34 ; The two S_ADD instructions should write to different registers, since 35 ; different threads will take different control flow paths. 36 37 ; SI-LABEL: {{^}}sgpr_if_else_valu_br: 38 ; SI: s_add_i32 [[SGPR:s[0-9]+]] 39 ; SI-NOT: s_add_i32 [[SGPR]] 40 41 define void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) { 42 entry: 43 %tid = call i32 @llvm.r600.read.tidig.x() #0 44 %tid_f = uitofp i32 %tid to float 45 %tmp1 = fcmp ueq float %tid_f, 0.0 46 br i1 %tmp1, label %if, label %else 47 48 if: 49 %tmp2 = add i32 %b, %c 50 br label %endif 51 52 else: 53 %tmp3 = add i32 %d, %e 54 br label %endif 55 56 endif: 57 %tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else] 58 store i32 %tmp4, i32 addrspace(1)* %out 59 ret void 60 } 61 62 ; FIXME: Should write to different SGPR pairs instead of copying to 63 ; VALU for i1 phi. 64 65 ; SI-LABEL: {{^}}sgpr_if_else_valu_cmp_phi_br: 66 ; SI: buffer_load_dword [[AVAL:v[0-9]+]] 67 ; SI: v_cmp_gt_i32_e32 [[CMP_IF:vcc]], 0, [[AVAL]] 68 ; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]] 69 70 ; SI: BB2_1: 71 ; SI: buffer_load_dword [[AVAL:v[0-9]+]] 72 ; SI: v_cmp_eq_i32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]] 73 ; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]] 74 75 ; SI: v_cmp_ne_i32_e32 [[CMP_CMP:vcc]], 0, [[V_CMP]] 76 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP_CMP]] 77 ; SI: buffer_store_dword [[RESULT]] 78 define void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { 79 entry: 80 %tid = call i32 @llvm.r600.read.tidig.x() #0 81 %tmp1 = icmp eq i32 %tid, 0 82 br i1 %tmp1, label %if, label %else 83 84 if: 85 %gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid 86 %a.val = load i32, i32 addrspace(1)* %gep.if 87 %cmp.if = icmp eq i32 %a.val, 0 88 br label %endif 89 90 else: 91 %gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid 92 %b.val = load i32, i32 addrspace(1)* %gep.else 93 %cmp.else = icmp slt i32 %b.val, 0 94 br label %endif 95 96 endif: 97 %tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else] 98 %ext = sext i1 %tmp4 to i32 99 store i32 %ext, i32 addrspace(1)* %out 100 ret void 101 } 102 103 declare i32 @llvm.r600.read.tidig.x() #0 104 105 attributes #0 = { readnone } 106
