1 ; RUN: llc < %s | FileCheck %s 2 3 target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" 4 target triple = "hexagon" 5 6 ; CHECK-LABEL: test1: 7 ; CHECK: r0 = ##1073741824 8 define i32 @test1() #0 { 9 entry: 10 %0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd(i32 2147483647, i32 0) 11 ret i32 %0 12 } 13 14 ; CHECK-LABEL: test2: 15 ; CHECK: r0 = ##1073741824 16 define i32 @test2() #0 { 17 entry: 18 %0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 2147483647, i32 1) 19 ret i32 %0 20 } 21 22 ; CHECK-LABEL: test3: 23 ; CHECK: r1:0 = combine(#0, #1) 24 define i64 @test3() #0 { 25 entry: 26 %0 = tail call i64 @llvm.hexagon.S4.extractp(i64 -1, i32 63, i32 63) 27 ret i64 %0 28 } 29 30 ; CHECK-LABEL: test4: 31 ; CHECK: r0 = #1 32 define i32 @test4() #0 { 33 entry: 34 %0 = tail call i32 @llvm.hexagon.S4.extract(i32 -1, i32 31, i32 31) 35 ret i32 %0 36 } 37 38 ; CHECK-LABEL: test5: 39 ; CHECK: r0 = ##-1073741569 40 define i32 @test5() #0 { 41 entry: 42 %0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 255, i32 -2147483648, i32 1) 43 ret i32 %0 44 } 45 46 declare i32 @llvm.hexagon.S2.asr.i.r.rnd(i32, i32) #0 47 declare i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32, i32) #0 48 declare i64 @llvm.hexagon.S4.extractp(i64, i32, i32) #0 49 declare i32 @llvm.hexagon.S4.extract(i32, i32, i32) #0 50 declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) #0 51 52 attributes #0 = { nounwind readnone } 53 54
