1 ; Test the MSA intrinsics that are encoded with the ELM instruction format and 2 ; are either shifts or slides. 3 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7 @llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8 @llvm_mips_sldi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 9 @llvm_mips_sldi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 10 11 define void @llvm_mips_sldi_b_test() nounwind { 12 entry: 13 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sldi_b_ARG1 14 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sldi_b_ARG2 15 %2 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, <16 x i8> %1, i32 1) 16 store <16 x i8> %2, <16 x i8>* @llvm_mips_sldi_b_RES 17 ret void 18 } 19 20 declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind 21 22 ; CHECK: llvm_mips_sldi_b_test: 23 ; CHECK: ld.b 24 ; CHECK: sldi.b 25 ; CHECK: st.b 26 ; CHECK: .size llvm_mips_sldi_b_test 27 ; 28 @llvm_mips_sldi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 29 @llvm_mips_sldi_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 30 @llvm_mips_sldi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 31 32 define void @llvm_mips_sldi_h_test() nounwind { 33 entry: 34 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sldi_h_ARG1 35 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sldi_h_ARG2 36 %2 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, <8 x i16> %1, i32 1) 37 store <8 x i16> %2, <8 x i16>* @llvm_mips_sldi_h_RES 38 ret void 39 } 40 41 declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind 42 43 ; CHECK: llvm_mips_sldi_h_test: 44 ; CHECK: ld.h 45 ; CHECK: sldi.h 46 ; CHECK: st.h 47 ; CHECK: .size llvm_mips_sldi_h_test 48 ; 49 @llvm_mips_sldi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 50 @llvm_mips_sldi_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 51 @llvm_mips_sldi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 52 53 define void @llvm_mips_sldi_w_test() nounwind { 54 entry: 55 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sldi_w_ARG1 56 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sldi_w_ARG2 57 %2 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, <4 x i32> %1, i32 1) 58 store <4 x i32> %2, <4 x i32>* @llvm_mips_sldi_w_RES 59 ret void 60 } 61 62 declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind 63 64 ; CHECK: llvm_mips_sldi_w_test: 65 ; CHECK: ld.w 66 ; CHECK: sldi.w 67 ; CHECK: st.w 68 ; CHECK: .size llvm_mips_sldi_w_test 69 ; 70 @llvm_mips_sldi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 71 @llvm_mips_sldi_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16 72 @llvm_mips_sldi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 73 74 define void @llvm_mips_sldi_d_test() nounwind { 75 entry: 76 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sldi_d_ARG1 77 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sldi_d_ARG2 78 %2 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, <2 x i64> %1, i32 1) 79 store <2 x i64> %2, <2 x i64>* @llvm_mips_sldi_d_RES 80 ret void 81 } 82 83 declare <2 x i64> @llvm.mips.sldi.d(<2 x i64>, <2 x i64>, i32) nounwind 84 85 ; CHECK: llvm_mips_sldi_d_test: 86 ; CHECK: ld.d 87 ; CHECK: sldi.d 88 ; CHECK: st.d 89 ; CHECK: .size llvm_mips_sldi_d_test 90 ; 91 @llvm_mips_splati_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 92 @llvm_mips_splati_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 93 94 define void @llvm_mips_splati_b_test() nounwind { 95 entry: 96 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_splati_b_ARG1 97 %1 = tail call <16 x i8> @llvm.mips.splati.b(<16 x i8> %0, i32 1) 98 store <16 x i8> %1, <16 x i8>* @llvm_mips_splati_b_RES 99 ret void 100 } 101 102 declare <16 x i8> @llvm.mips.splati.b(<16 x i8>, i32) nounwind 103 104 ; CHECK: llvm_mips_splati_b_test: 105 ; CHECK: ld.b 106 ; CHECK: splati.b 107 ; CHECK: st.b 108 ; CHECK: .size llvm_mips_splati_b_test 109 ; 110 @llvm_mips_splati_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 111 @llvm_mips_splati_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 112 113 define void @llvm_mips_splati_h_test() nounwind { 114 entry: 115 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_splati_h_ARG1 116 %1 = tail call <8 x i16> @llvm.mips.splati.h(<8 x i16> %0, i32 1) 117 store <8 x i16> %1, <8 x i16>* @llvm_mips_splati_h_RES 118 ret void 119 } 120 121 declare <8 x i16> @llvm.mips.splati.h(<8 x i16>, i32) nounwind 122 123 ; CHECK: llvm_mips_splati_h_test: 124 ; CHECK: ld.h 125 ; CHECK: splati.h 126 ; CHECK: st.h 127 ; CHECK: .size llvm_mips_splati_h_test 128 ; 129 @llvm_mips_splati_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 130 @llvm_mips_splati_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 131 132 define void @llvm_mips_splati_w_test() nounwind { 133 entry: 134 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_splati_w_ARG1 135 %1 = tail call <4 x i32> @llvm.mips.splati.w(<4 x i32> %0, i32 1) 136 store <4 x i32> %1, <4 x i32>* @llvm_mips_splati_w_RES 137 ret void 138 } 139 140 declare <4 x i32> @llvm.mips.splati.w(<4 x i32>, i32) nounwind 141 142 ; CHECK: llvm_mips_splati_w_test: 143 ; CHECK: ld.w 144 ; CHECK: splati.w 145 ; CHECK: st.w 146 ; CHECK: .size llvm_mips_splati_w_test 147 ; 148 @llvm_mips_splati_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 149 @llvm_mips_splati_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 150 151 define void @llvm_mips_splati_d_test() nounwind { 152 entry: 153 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_splati_d_ARG1 154 %1 = tail call <2 x i64> @llvm.mips.splati.d(<2 x i64> %0, i32 1) 155 store <2 x i64> %1, <2 x i64>* @llvm_mips_splati_d_RES 156 ret void 157 } 158 159 declare <2 x i64> @llvm.mips.splati.d(<2 x i64>, i32) nounwind 160 161 ; CHECK: llvm_mips_splati_d_test: 162 ; CHECK: ld.d 163 ; CHECK: splati.d 164 ; CHECK: st.d 165 ; CHECK: .size llvm_mips_splati_d_test 166 ; 167
