1 ; Test v2i64 comparisons. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5 ; Test eq. 6 define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 7 ; CHECK-LABEL: f1: 8 ; CHECK: vceqg %v24, %v26, %v28 9 ; CHECK-NEXT: br %r14 10 %cmp = icmp eq <2 x i64> %val1, %val2 11 %ret = sext <2 x i1> %cmp to <2 x i64> 12 ret <2 x i64> %ret 13 } 14 15 ; Test ne. 16 define <2 x i64> @f2(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 17 ; CHECK-LABEL: f2: 18 ; CHECK: vceqg [[REG:%v[0-9]+]], %v26, %v28 19 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 20 ; CHECK-NEXT: br %r14 21 %cmp = icmp ne <2 x i64> %val1, %val2 22 %ret = sext <2 x i1> %cmp to <2 x i64> 23 ret <2 x i64> %ret 24 } 25 26 ; Test sgt. 27 define <2 x i64> @f3(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 28 ; CHECK-LABEL: f3: 29 ; CHECK: vchg %v24, %v26, %v28 30 ; CHECK-NEXT: br %r14 31 %cmp = icmp sgt <2 x i64> %val1, %val2 32 %ret = sext <2 x i1> %cmp to <2 x i64> 33 ret <2 x i64> %ret 34 } 35 36 ; Test sge. 37 define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 38 ; CHECK-LABEL: f4: 39 ; CHECK: vchg [[REG:%v[0-9]+]], %v28, %v26 40 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 41 ; CHECK-NEXT: br %r14 42 %cmp = icmp sge <2 x i64> %val1, %val2 43 %ret = sext <2 x i1> %cmp to <2 x i64> 44 ret <2 x i64> %ret 45 } 46 47 ; Test sle. 48 define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 49 ; CHECK-LABEL: f5: 50 ; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v28 51 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 52 ; CHECK-NEXT: br %r14 53 %cmp = icmp sle <2 x i64> %val1, %val2 54 %ret = sext <2 x i1> %cmp to <2 x i64> 55 ret <2 x i64> %ret 56 } 57 58 ; Test slt. 59 define <2 x i64> @f6(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 60 ; CHECK-LABEL: f6: 61 ; CHECK: vchg %v24, %v28, %v26 62 ; CHECK-NEXT: br %r14 63 %cmp = icmp slt <2 x i64> %val1, %val2 64 %ret = sext <2 x i1> %cmp to <2 x i64> 65 ret <2 x i64> %ret 66 } 67 68 ; Test ugt. 69 define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 70 ; CHECK-LABEL: f7: 71 ; CHECK: vchlg %v24, %v26, %v28 72 ; CHECK-NEXT: br %r14 73 %cmp = icmp ugt <2 x i64> %val1, %val2 74 %ret = sext <2 x i1> %cmp to <2 x i64> 75 ret <2 x i64> %ret 76 } 77 78 ; Test uge. 79 define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 80 ; CHECK-LABEL: f8: 81 ; CHECK: vchlg [[REG:%v[0-9]+]], %v28, %v26 82 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 83 ; CHECK-NEXT: br %r14 84 %cmp = icmp uge <2 x i64> %val1, %val2 85 %ret = sext <2 x i1> %cmp to <2 x i64> 86 ret <2 x i64> %ret 87 } 88 89 ; Test ule. 90 define <2 x i64> @f9(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 91 ; CHECK-LABEL: f9: 92 ; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v28 93 ; CHECK-NEXT: vno %v24, [[REG]], [[REG]] 94 ; CHECK-NEXT: br %r14 95 %cmp = icmp ule <2 x i64> %val1, %val2 96 %ret = sext <2 x i1> %cmp to <2 x i64> 97 ret <2 x i64> %ret 98 } 99 100 ; Test ult. 101 define <2 x i64> @f10(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { 102 ; CHECK-LABEL: f10: 103 ; CHECK: vchlg %v24, %v28, %v26 104 ; CHECK-NEXT: br %r14 105 %cmp = icmp ult <2 x i64> %val1, %val2 106 %ret = sext <2 x i1> %cmp to <2 x i64> 107 ret <2 x i64> %ret 108 } 109 110 ; Test eq selects. 111 define <2 x i64> @f11(<2 x i64> %val1, <2 x i64> %val2, 112 <2 x i64> %val3, <2 x i64> %val4) { 113 ; CHECK-LABEL: f11: 114 ; CHECK: vceqg [[REG:%v[0-9]+]], %v24, %v26 115 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 116 ; CHECK-NEXT: br %r14 117 %cmp = icmp eq <2 x i64> %val1, %val2 118 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 119 ret <2 x i64> %ret 120 } 121 122 ; Test ne selects. 123 define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2, 124 <2 x i64> %val3, <2 x i64> %val4) { 125 ; CHECK-LABEL: f12: 126 ; CHECK: vceqg [[REG:%v[0-9]+]], %v24, %v26 127 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 128 ; CHECK-NEXT: br %r14 129 %cmp = icmp ne <2 x i64> %val1, %val2 130 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 131 ret <2 x i64> %ret 132 } 133 134 ; Test sgt selects. 135 define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2, 136 <2 x i64> %val3, <2 x i64> %val4) { 137 ; CHECK-LABEL: f13: 138 ; CHECK: vchg [[REG:%v[0-9]+]], %v24, %v26 139 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 140 ; CHECK-NEXT: br %r14 141 %cmp = icmp sgt <2 x i64> %val1, %val2 142 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 143 ret <2 x i64> %ret 144 } 145 146 ; Test sge selects. 147 define <2 x i64> @f14(<2 x i64> %val1, <2 x i64> %val2, 148 <2 x i64> %val3, <2 x i64> %val4) { 149 ; CHECK-LABEL: f14: 150 ; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v24 151 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 152 ; CHECK-NEXT: br %r14 153 %cmp = icmp sge <2 x i64> %val1, %val2 154 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 155 ret <2 x i64> %ret 156 } 157 158 ; Test sle selects. 159 define <2 x i64> @f15(<2 x i64> %val1, <2 x i64> %val2, 160 <2 x i64> %val3, <2 x i64> %val4) { 161 ; CHECK-LABEL: f15: 162 ; CHECK: vchg [[REG:%v[0-9]+]], %v24, %v26 163 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 164 ; CHECK-NEXT: br %r14 165 %cmp = icmp sle <2 x i64> %val1, %val2 166 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 167 ret <2 x i64> %ret 168 } 169 170 ; Test slt selects. 171 define <2 x i64> @f16(<2 x i64> %val1, <2 x i64> %val2, 172 <2 x i64> %val3, <2 x i64> %val4) { 173 ; CHECK-LABEL: f16: 174 ; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v24 175 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 176 ; CHECK-NEXT: br %r14 177 %cmp = icmp slt <2 x i64> %val1, %val2 178 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 179 ret <2 x i64> %ret 180 } 181 182 ; Test ugt selects. 183 define <2 x i64> @f17(<2 x i64> %val1, <2 x i64> %val2, 184 <2 x i64> %val3, <2 x i64> %val4) { 185 ; CHECK-LABEL: f17: 186 ; CHECK: vchlg [[REG:%v[0-9]+]], %v24, %v26 187 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 188 ; CHECK-NEXT: br %r14 189 %cmp = icmp ugt <2 x i64> %val1, %val2 190 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 191 ret <2 x i64> %ret 192 } 193 194 ; Test uge selects. 195 define <2 x i64> @f18(<2 x i64> %val1, <2 x i64> %val2, 196 <2 x i64> %val3, <2 x i64> %val4) { 197 ; CHECK-LABEL: f18: 198 ; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v24 199 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 200 ; CHECK-NEXT: br %r14 201 %cmp = icmp uge <2 x i64> %val1, %val2 202 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 203 ret <2 x i64> %ret 204 } 205 206 ; Test ule selects. 207 define <2 x i64> @f19(<2 x i64> %val1, <2 x i64> %val2, 208 <2 x i64> %val3, <2 x i64> %val4) { 209 ; CHECK-LABEL: f19: 210 ; CHECK: vchlg [[REG:%v[0-9]+]], %v24, %v26 211 ; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]] 212 ; CHECK-NEXT: br %r14 213 %cmp = icmp ule <2 x i64> %val1, %val2 214 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 215 ret <2 x i64> %ret 216 } 217 218 ; Test ult selects. 219 define <2 x i64> @f20(<2 x i64> %val1, <2 x i64> %val2, 220 <2 x i64> %val3, <2 x i64> %val4) { 221 ; CHECK-LABEL: f20: 222 ; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v24 223 ; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]] 224 ; CHECK-NEXT: br %r14 225 %cmp = icmp ult <2 x i64> %val1, %val2 226 %ret = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4 227 ret <2 x i64> %ret 228 } 229
