1 ; Test insertions of register values into 0. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5 ; Test v16i8 insertion into 0. 6 define <16 x i8> @f1(i8 %val1, i8 %val2) { 7 ; CHECK-LABEL: f1: 8 ; CHECK: vgbm %v24, 0 9 ; CHECK-DAG: vlvgb %v24, %r2, 2 10 ; CHECK-DAG: vlvgb %v24, %r3, 12 11 ; CHECK: br %r14 12 %vec1 = insertelement <16 x i8> zeroinitializer, i8 %val1, i32 2 13 %vec2 = insertelement <16 x i8> %vec1, i8 %val2, i32 12 14 ret <16 x i8> %vec2 15 } 16 17 ; Test v8i16 insertion into 0. 18 define <8 x i16> @f2(i16 %val1, i16 %val2) { 19 ; CHECK-LABEL: f2: 20 ; CHECK: vgbm %v24, 0 21 ; CHECK-DAG: vlvgh %v24, %r2, 3 22 ; CHECK-DAG: vlvgh %v24, %r3, 5 23 ; CHECK: br %r14 24 %vec1 = insertelement <8 x i16> zeroinitializer, i16 %val1, i32 3 25 %vec2 = insertelement <8 x i16> %vec1, i16 %val2, i32 5 26 ret <8 x i16> %vec2 27 } 28 29 ; Test v4i32 insertion into 0. 30 define <4 x i32> @f3(i32 %val) { 31 ; CHECK-LABEL: f3: 32 ; CHECK: vgbm %v24, 0 33 ; CHECK: vlvgf %v24, %r2, 3 34 ; CHECK: br %r14 35 %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 3 36 ret <4 x i32> %ret 37 } 38 39 ; Test v2i64 insertion into 0. 40 define <2 x i64> @f4(i64 %val) { 41 ; CHECK-LABEL: f4: 42 ; CHECK: lghi [[REG:%r[0-5]]], 0 43 ; CHECK: vlvgp %v24, [[REG]], %r2 44 ; CHECK: br %r14 45 %ret = insertelement <2 x i64> zeroinitializer, i64 %val, i32 1 46 ret <2 x i64> %ret 47 } 48 49 ; Test v4f32 insertion into 0. 50 define <4 x float> @f5(float %val) { 51 ; CHECK-LABEL: f5: 52 ; CHECK-DAG: vuplhf [[REG:%v[0-9]+]], %v0 53 ; CHECK-DAG: vgbm [[ZERO:%v[0-9]+]], 0 54 ; CHECK: vmrhg %v24, [[ZERO]], [[REG]] 55 ; CHECK: br %r14 56 %ret = insertelement <4 x float> zeroinitializer, float %val, i32 3 57 ret <4 x float> %ret 58 } 59 60 ; Test v2f64 insertion into 0. 61 define <2 x double> @f6(double %val) { 62 ; CHECK-LABEL: f6: 63 ; CHECK: vgbm [[REG:%v[0-9]+]], 0 64 ; CHECK: vmrhg %v24, [[REG]], %v0 65 ; CHECK: br %r14 66 %ret = insertelement <2 x double> zeroinitializer, double %val, i32 1 67 ret <2 x double> %ret 68 } 69 70
