1 //===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Tablegen register definitions common to all hw codegen targets. 11 // 12 //===----------------------------------------------------------------------===// 13 14 let Namespace = "AMDGPU" in { 15 def sel_x : SubRegIndex; 16 def sel_y : SubRegIndex; 17 def sel_z : SubRegIndex; 18 def sel_w : SubRegIndex; 19 } 20 21 include "R600RegisterInfo.td" 22 include "SIRegisterInfo.td" 23
