1 // Copyright 2015, ARM Limited 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // --------------------------------------------------------------------- 29 // This file is auto generated using tools/generate_simulator_traces.py. 30 // 31 // PLEASE DO NOT EDIT. 32 // --------------------------------------------------------------------- 33 34 #ifndef VIXL_SIM_FCVTAU_XS_TRACE_A64_H_ 35 #define VIXL_SIM_FCVTAU_XS_TRACE_A64_H_ 36 37 const uint64_t kExpected_fcvtau_xs[] = { 38 0u, 39 0u, 40 0u, 41 1u, 42 1u, 43 1u, 44 1u, 45 1u, 46 2u, 47 10u, 48 0u, 49 18446744073709551615u, 50 0u, 51 0u, 52 0u, 53 0u, 54 0u, 55 0u, 56 0u, 57 0u, 58 0u, 59 0u, 60 0u, 61 0u, 62 0u, 63 0u, 64 0u, 65 0u, 66 0u, 67 0u, 68 0u, 69 0u, 70 0u, 71 0u, 72 0u, 73 0u, 74 0u, 75 0u, 76 8388608u, 77 8388609u, 78 8388610u, 79 8388611u, 80 16143410u, 81 16777212u, 82 16777213u, 83 16777214u, 84 16777215u, 85 4194304u, 86 4194305u, 87 4194305u, 88 4194306u, 89 8071705u, 90 8388606u, 91 8388607u, 92 8388607u, 93 8388608u, 94 2097152u, 95 2097152u, 96 2097153u, 97 2097153u, 98 4035853u, 99 4194303u, 100 4194303u, 101 4194304u, 102 4194304u, 103 0u, 104 0u, 105 0u, 106 0u, 107 0u, 108 0u, 109 0u, 110 0u, 111 0u, 112 0u, 113 0u, 114 0u, 115 0u, 116 0u, 117 0u, 118 0u, 119 0u, 120 0u, 121 0u, 122 0u, 123 0u, 124 0u, 125 0u, 126 0u, 127 0u, 128 0u, 129 0u, 130 0u, 131 0u, 132 0u, 133 9223371487098961920u, 134 9223372036854775808u, 135 18446742974197923840u, 136 18446744073709551615u, 137 0u, 138 0u, 139 0u, 140 2147483520u, 141 2147483648u, 142 }; 143 const unsigned kExpectedCount_fcvtau_xs = 104; 144 145 #endif // VIXL_SIM_FCVTAU_XS_TRACE_A64_H_ 146
