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      1 // Copyright 2015, ARM Limited
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // ---------------------------------------------------------------------
     29 // This file is auto generated using tools/generate_simulator_traces.py.
     30 //
     31 // PLEASE DO NOT EDIT.
     32 // ---------------------------------------------------------------------
     33 
     34 #ifndef VIXL_SIM_FNEG_2S_TRACE_A64_H_
     35 #define VIXL_SIM_FNEG_2S_TRACE_A64_H_
     36 
     37 const uint32_t kExpected_NEON_fneg_2S[] = {
     38   0x00123456, 0x007fffff,
     39   0x007fffff, 0x00000001,
     40   0x00000001, 0x80000000,
     41   0x80000000, 0x80800000,
     42   0x80800000, 0xbeffffff,
     43   0xbeffffff, 0xbf000000,
     44   0xbf000000, 0xbf000001,
     45   0xbf000001, 0xbf7fffff,
     46   0xbf7fffff, 0xbf800000,
     47   0xbf800000, 0xbf800001,
     48   0xbf800001, 0xbfc00000,
     49   0xbfc00000, 0xc1200000,
     50   0xc1200000, 0xff8fffff,
     51   0xff8fffff, 0xff800000,
     52   0xff800000, 0xffd23456,
     53   0xffd23456, 0xffc00000,
     54   0xffc00000, 0xff923456,
     55   0xff923456, 0xff800001,
     56   0xff800001, 0x80123456,
     57   0x80123456, 0x807fffff,
     58   0x807fffff, 0x80000001,
     59   0x80000001, 0x00000000,
     60   0x00000000, 0x00800000,
     61   0x00800000, 0x3effffff,
     62   0x3effffff, 0x3f000000,
     63   0x3f000000, 0x3f000001,
     64   0x3f000001, 0x3f7fffff,
     65   0x3f7fffff, 0x3f800000,
     66   0x3f800000, 0x3f800001,
     67   0x3f800001, 0x3fc00000,
     68   0x3fc00000, 0x41200000,
     69   0x41200000, 0x7f8fffff,
     70   0x7f8fffff, 0x7f800000,
     71   0x7f800000, 0x7fd23456,
     72   0x7fd23456, 0x7fc00000,
     73   0x7fc00000, 0x7f923456,
     74   0x7f923456, 0x7f800001,
     75   0x7f800001, 0x00123456,
     76 };
     77 const unsigned kExpectedCount_NEON_fneg_2S = 38;
     78 
     79 #endif  // VIXL_SIM_FNEG_2S_TRACE_A64_H_
     80