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      1 // Copyright 2015, ARM Limited
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // ---------------------------------------------------------------------
     29 // This file is auto generated using tools/generate_simulator_traces.py.
     30 //
     31 // PLEASE DO NOT EDIT.
     32 // ---------------------------------------------------------------------
     33 
     34 #ifndef VIXL_SIM_FSQRT_S_TRACE_A64_H_
     35 #define VIXL_SIM_FSQRT_S_TRACE_A64_H_
     36 
     37 const uint32_t kExpected_fsqrt_s[] = {
     38   0x00000000,
     39   0x20000000,
     40   0x3f3504f3,
     41   0x3f3504f3,
     42   0x3f3504f4,
     43   0x3f7fffff,
     44   0x3f800000,
     45   0x3f800000,
     46   0x3f9cc471,
     47   0x404a62c2,
     48   0x7fcfffff,
     49   0x7f800000,
     50   0x7fd23456,
     51   0x7fc00000,
     52   0x7fd23456,
     53   0x7fc00001,
     54   0x1f411656,
     55   0x1fffffff,
     56   0x1a3504f3,
     57   0x80000000,
     58   0x7fc00000,
     59   0x7fc00000,
     60   0x7fc00000,
     61   0x7fc00000,
     62   0x7fc00000,
     63   0x7fc00000,
     64   0x7fc00000,
     65   0x7fc00000,
     66   0x7fc00000,
     67   0xffcfffff,
     68   0x7fc00000,
     69   0xffd23456,
     70   0xffc00000,
     71   0xffd23456,
     72   0xffc00001,
     73   0x7fc00000,
     74   0x7fc00000,
     75   0x7fc00000,
     76 };
     77 const unsigned kExpectedCount_fsqrt_s = 38;
     78 
     79 #endif  // VIXL_SIM_FSQRT_S_TRACE_A64_H_
     80