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      1 // Copyright 2015, ARM Limited
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // ---------------------------------------------------------------------
     29 // This file is auto generated using tools/generate_simulator_traces.py.
     30 //
     31 // PLEASE DO NOT EDIT.
     32 // ---------------------------------------------------------------------
     33 
     34 #ifndef VIXL_SIM_SADDLP_2D_TRACE_A64_H_
     35 #define VIXL_SIM_SADDLP_2D_TRACE_A64_H_
     36 
     37 const uint64_t kExpected_NEON_saddlp_2D[] = {
     38   0xfffffffffffffffb, 0xffffffffffffffff,
     39   0xfffffffffffffffd, 0x0000000000000001,
     40   0xffffffffffffffff, 0x0000000000000003,
     41   0x0000000000000001, 0x0000000000000022,
     42   0x0000000000000003, 0x000000000000009d,
     43   0x0000000000000022, 0x00000000000000fb,
     44   0x000000000000009d, 0x00000000000000fd,
     45   0x00000000000000fb, 0x000000000000807c,
     46   0x00000000000000fd, 0x000000000000fffb,
     47   0x000000000000807c, 0x000000000000fffd,
     48   0x000000000000fffb, 0x000000003333b332,
     49   0x000000000000fffd, 0x0000000088888888,
     50   0x000000003333b332, 0x00000000d5555552,
     51   0x0000000088888888, 0x00000000fffffffb,
     52   0x00000000d5555552, 0x00000000fffffffd,
     53   0x00000000fffffffb, 0xffffffffffffffff,
     54   0x00000000fffffffd, 0xffffffff00000001,
     55   0xffffffffffffffff, 0xffffffff2aaaaaab,
     56   0xffffffff00000001, 0xffffffff77777776,
     57   0xffffffff2aaaaaab, 0xffffffffcccc4ccc,
     58   0xffffffff77777776, 0xffffffffffff0001,
     59   0xffffffffcccc4ccc, 0xffffffffffff0003,
     60   0xffffffffffff0001, 0xffffffffffff0005,
     61   0xffffffffffff0003, 0xffffffffffff7f83,
     62   0xffffffffffff0005, 0xffffffffffffff01,
     63   0xffffffffffff7f83, 0xffffffffffffff03,
     64   0xffffffffffffff01, 0xffffffffffffff05,
     65   0xffffffffffffff03, 0xffffffffffffff63,
     66   0xffffffffffffff05, 0xffffffffffffffdd,
     67   0xffffffffffffff63, 0xfffffffffffffffb,
     68   0xffffffffffffffdd, 0xfffffffffffffffd,
     69 };
     70 const unsigned kExpectedCount_NEON_saddlp_2D = 31;
     71 
     72 #endif  // VIXL_SIM_SADDLP_2D_TRACE_A64_H_
     73