1 ; OpenRISC Basic Instruction Set 32-bit (ORBIS) -*- Scheme -*- 2 ; Copyright 2000-2014 Free Software Foundation, Inc. 3 ; Contributed for OR32 by Johan Rydberg, jrydberg (a] opencores.org 4 ; Modified by Julius Baxter, juliusbaxter (a] gmail.com 5 ; Modified by Peter Gavin, pgavin (a] gmail.com 6 ; 7 ; This program is free software; you can redistribute it and/or modify 8 ; it under the terms of the GNU General Public License as published by 9 ; the Free Software Foundation; either version 3 of the License, or 10 ; (at your option) any later version. 11 ; 12 ; This program is distributed in the hope that it will be useful, 13 ; but WITHOUT ANY WARRANTY; without even the implied warranty of 14 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 ; GNU General Public License for more details. 16 ; 17 ; You should have received a copy of the GNU General Public License 18 ; along with this program; if not, see <http://www.gnu.org/licenses/> 19 20 ; Instruction fields. 21 22 ; Hardware for immediate operands 23 (dnh h-simm16 "16-bit signed immediate" ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ()) 24 (dnh h-uimm16 "16-bit unsigned immediate" () (immediate (UINT 16)) () () ()) 25 (dnh h-uimm6 "6-bit unsigned immediate" () (immediate (UINT 6)) () () ()) 26 27 ; Hardware for the (internal) atomic registers 28 (dsh h-atomic-reserve "atomic reserve flag" () (register BI)) 29 (dsh h-atomic-address "atomic reserve address" () (register SI)) 30 31 ; Instruction classes. 32 (dnf f-opcode "insn opcode" ((MACH ORBIS-MACHS)) 31 6) 33 34 ; Register fields. 35 (dnf f-r1 "r1" ((MACH ORBIS-MACHS)) 25 5) 36 (dnf f-r2 "r2" ((MACH ORBIS-MACHS)) 20 5) 37 (dnf f-r3 "r3" ((MACH ORBIS-MACHS)) 15 5) 38 39 ; Sub fields 40 (dnf f-op-25-2 "op-25-2" ((MACH ORBIS-MACHS)) 25 2) ;; nop 41 (dnf f-op-25-5 "op-25-5" ((MACH ORBIS-MACHS)) 25 5) ;; sys, trap, *sync, sf* 42 (dnf f-op-16-1 "op-16-1" ((MACH ORBIS-MACHS)) 16 1) ;; movhi,macrc 43 (dnf f-op-7-4 "op-7-4" ((MACH ORBIS-MACHS)) 7 4) 44 (dnf f-op-3-4 "op-3-4" ((MACH ORBIS-MACHS)) 3 4) 45 (dnf f-op-9-2 "op-9-2" ((MACH ORBIS-MACHS)) 9 2) ;; alu ops upper opcode 46 (dnf f-op-9-4 "op-9-4" ((MACH ORBIS-MACHS)) 9 4) ;; 47 (dnf f-op-7-8 "op-7-8" ((MACH ORBIS-MACHS)) 7 8) 48 (dnf f-op-7-2 "op-7-2" ((MACH ORBIS-MACHS)) 7 2) ;; alu lower upper opc,shroti 49 50 ; Reserved fields 51 (dnf f-resv-25-26 "resv-25-26" ((MACH ORBIS-MACHS) RESERVED) 25 26) 52 (dnf f-resv-25-10 "resv-25-10" ((MACH ORBIS-MACHS) RESERVED) 25 10) 53 (dnf f-resv-25-5 "resv-25-5" ((MACH ORBIS-MACHS) RESERVED) 25 5) 54 (dnf f-resv-23-8 "resv-23-8" ((MACH ORBIS-MACHS) RESERVED) 23 8) 55 (dnf f-resv-20-21 "resv-20-21" ((MACH ORBIS-MACHS) RESERVED) 20 21) 56 (dnf f-resv-20-5 "resv-20-5" ((MACH ORBIS-MACHS) RESERVED) 20 5) 57 (dnf f-resv-20-4 "resv-20-4" ((MACH ORBIS-MACHS) RESERVED) 20 4) 58 (dnf f-resv-15-8 "resv-15-8" ((MACH ORBIS-MACHS) RESERVED) 15 8) 59 (dnf f-resv-15-6 "resv-15-6" ((MACH ORBIS-MACHS) RESERVED) 15 6) 60 (dnf f-resv-10-11 "resv-10-11" ((MACH ORBIS-MACHS) RESERVED) 10 11) 61 (dnf f-resv-10-7 "resv-10-7" ((MACH ORBIS-MACHS) RESERVED) 10 7) 62 (dnf f-resv-10-3 "resv-10-3" ((MACH ORBIS-MACHS) RESERVED) 10 3) 63 (dnf f-resv-10-1 "resv-10-1" ((MACH ORBIS-MACHS) RESERVED) 10 1) 64 (dnf f-resv-7-4 "resv-7-4" ((MACH ORBIS-MACHS) RESERVED) 7 4) 65 (dnf f-resv-5-2 "resv-5-2" ((MACH ORBIS-MACHS) RESERVED) 5 2) 66 67 (dnf f-imm16-25-5 "imm16-25-5" ((MACH ORBIS-MACHS)) 25 5) 68 (dnf f-imm16-10-11 "imm16-10-11" ((MACH ORBIS-MACHS)) 10 11) 69 70 ; PC relative, 26-bit (2 shifted to right) 71 (df f-disp26 72 "disp26" 73 ((MACH ORBIS-MACHS) PCREL-ADDR) 74 25 75 26 76 INT 77 ((value pc) (sra SI (sub IAI value pc) (const 2))) 78 ((value pc) (add IAI (sll IAI value (const 2)) pc)) 79 ) 80 81 ; Immediates. 82 (dnf f-uimm16 "uimm16" ((MACH ORBIS-MACHS)) 15 16) 83 (df f-simm16 "simm16" ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f) 84 (dnf f-uimm6 "uimm6" ((MACH ORBIS-MACHS)) 5 6) ;; shroti 85 86 (define-multi-ifield 87 (name f-uimm16-split) 88 (comment "16-bit split unsigned immediate") 89 (attrs (MACH ORBIS-MACHS)) 90 (mode UINT) 91 (subfields f-imm16-25-5 f-imm16-10-11) 92 (insert (sequence () 93 (set (ifield f-imm16-25-5) 94 (and (srl (ifield f-uimm16-split) 95 (const 11)) 96 (const #x1f))) 97 (set (ifield f-imm16-10-11) 98 (and (ifield f-uimm16-split) 99 (const #x7ff))))) 100 (extract 101 (set (ifield f-uimm16-split) 102 (trunc UHI 103 (or (sll (ifield f-imm16-25-5) 104 (const 11)) 105 (ifield f-imm16-10-11))))) 106 ) 107 108 (define-multi-ifield 109 (name f-simm16-split) 110 (comment "16-bit split signed immediate") 111 (attrs (MACH ORBIS-MACHS) SIGN-OPT) 112 (mode INT) 113 (subfields f-imm16-25-5 f-imm16-10-11) 114 (insert (sequence () 115 (set (ifield f-imm16-25-5) 116 (and (sra (ifield f-simm16-split) 117 (const 11)) 118 (const #x1f))) 119 (set (ifield f-imm16-10-11) 120 (and (ifield f-simm16-split) 121 (const #x7ff))))) 122 (extract 123 (set (ifield f-simm16-split) 124 (trunc HI 125 (or (sll (ifield f-imm16-25-5) 126 (const 11)) 127 (ifield f-imm16-10-11))))) 128 ) 129 130 ; Enums. 131 132 ; insn-opcode: bits 31-26 133 (define-normal-insn-enum 134 insn-opcode "insn main opcode enums" ((MACH ORBIS-MACHS)) OPC_ f-opcode 135 (("J" #x00) 136 ("JAL" #x01) 137 ("BNF" #x03) 138 ("BF" #x04) 139 ("NOP" #x05) 140 ("MOVHIMACRC" #x06) 141 ("SYSTRAPSYNCS" #x08) 142 ("RFE" #x09) 143 ("VECTOR" #x0a) 144 ("JR" #x11) 145 ("JALR" #x12) 146 ("MACI" #x13) 147 ("LWA" #x1b) 148 ("CUST1" #x1c) 149 ("CUST2" #x1d) 150 ("CUST3" #x1e) 151 ("CUST4" #x1f) 152 ("LD" #x20) 153 ("LWZ" #x21) 154 ("LWS" #x22) 155 ("LBZ" #x23) 156 ("LBS" #x24) 157 ("LHZ" #x25) 158 ("LHS" #x26) 159 ("ADDI" #x27) 160 ("ADDIC" #x28) 161 ("ANDI" #x29) 162 ("ORI" #x2a) 163 ("XORI" #x2b) 164 ("MULI" #x2c) 165 ("MFSPR" #x2d) 166 ("SHROTI" #x2e) 167 ("SFI" #x2f) 168 ("MTSPR" #x30) 169 ("MAC" #x31) 170 ("FLOAT" #x32) 171 ("SWA" #x33) 172 ("SD" #x34) 173 ("SW" #x35) 174 ("SB" #x36) 175 ("SH" #x37) 176 ("ALU" #x38) 177 ("SF" #x39) 178 ("CUST5" #x3c) 179 ("CUST6" #x3d) 180 ("CUST7" #x3e) 181 ("CUST8" #x3f) 182 ) 183 ) 184 185 (define-normal-insn-enum insn-opcode-systrapsyncs 186 "systrapsync insn opcode enums" ((MACH ORBIS-MACHS)) 187 OPC_SYSTRAPSYNCS_ f-op-25-5 188 (("SYSCALL" #x00 ) 189 ("TRAP" #x08 ) 190 ("MSYNC" #x10 ) 191 ("PSYNC" #x14 ) 192 ("CSYNC" #x18 ) 193 ) 194 ) 195 196 (define-normal-insn-enum insn-opcode-movehimacrc 197 "movhi/macrc insn opcode enums" ((MACH ORBIS-MACHS)) 198 OPC_MOVHIMACRC_ f-op-16-1 199 (("MOVHI" #x0) 200 ("MACRC" #x1) 201 ) 202 ) 203 204 (define-normal-insn-enum insn-opcode-mac 205 "multiply/accumulate insn opcode enums" ((MACH ORBIS-MACHS)) 206 OPC_MAC_ f-op-3-4 207 (("MAC" #x1) 208 ("MSB" #x2) 209 ) 210 ) 211 212 (define-normal-insn-enum insn-opcode-shorts 213 "shift/rotate insn opcode enums" ((MACH ORBIS-MACHS)) 214 OPC_SHROTS_ f-op-7-2 215 (("SLL" #x0 ) 216 ("SRL" #x1 ) 217 ("SRA" #x2 ) 218 ("ROR" #x3 ) 219 ) 220 ) 221 222 (define-normal-insn-enum insn-opcode-extbhs 223 "extend byte/half opcode enums" ((MACH ORBIS-MACHS)) 224 OPC_EXTBHS_ f-op-9-4 225 (("EXTHS" #x0) 226 ("EXTBS" #x1) 227 ("EXTHZ" #x2) 228 ("EXTBZ" #x3) 229 ) 230 ) 231 232 (define-normal-insn-enum insn-opcode-extws 233 "extend word opcode enums" ((MACH ORBIS-MACHS)) 234 OPC_EXTWS_ f-op-9-4 235 (("EXTWS" #x0) 236 ("EXTWZ" #x1) 237 ) 238 ) 239 240 (define-normal-insn-enum insn-opcode-alu-regreg 241 "alu reg/reg insn opcode enums" ((MACH ORBIS-MACHS)) 242 OPC_ALU_REGREG_ f-op-3-4 243 (("ADD" #x0) 244 ("ADDC" #x1) 245 ("SUB" #x2) 246 ("AND" #x3) 247 ("OR" #x4) 248 ("XOR" #x5) 249 ("MUL" #x6) 250 ("SHROT" #x8) 251 ("DIV" #x9) 252 ("DIVU" #xA) 253 ("MULU" #xB) 254 ("EXTBH" #xC) 255 ("EXTW" #xD) 256 ("CMOV" #xE) 257 ("FFL1" #xF) 258 ) 259 ) 260 261 (define-normal-insn-enum insn-opcode-setflag 262 "setflag insn opcode enums" ((MACH ORBIS-MACHS)) 263 OPC_SF_ f-op-25-5 264 (("EQ" #x00) 265 ("NE" #x01) 266 ("GTU" #x02) 267 ("GEU" #x03) 268 ("LTU" #x04) 269 ("LEU" #x05) 270 ("GTS" #x0A) 271 ("GES" #x0B) 272 ("LTS" #x0C) 273 ("LES" #x0D) 274 ) 275 ) 276 277 279 ; Instruction operands. 280 281 (dnop sys-sr "supervision register" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr f-nil) 282 (dnop sys-esr0 "exception supervision register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-esr0 f-nil) 283 (dnop sys-epcr0 "exception PC register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-epcr0 f-nil) 284 285 (dnop sys-sr-lee "SR little endian enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-lee f-nil) 286 (dnop sys-sr-f "SR flag bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-f f-nil) 287 (dnop sys-sr-cy "SR carry bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-cy f-nil) 288 (dnop sys-sr-ov "SR overflow bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ov f-nil) 289 (dnop sys-sr-ove "SR overflow exception enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ove f-nil) 290 (dnop sys-cpucfgr-ob64s "CPUCFGR ORBIS64 supported bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-ob64s f-nil) 291 (dnop sys-cpucfgr-nd "CPUCFGR no delay bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-nd f-nil) 292 (dnop sys-fpcsr-rm "floating point round mode" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-fpcsr-rm f-nil) 293 294 (dnop mac-machi "MAC HI result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi f-nil) 295 (dnop mac-maclo "MAC LO result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo f-nil) 296 297 (dnop atomic-reserve "atomic reserve flag" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-reserve f-nil) 298 (dnop atomic-address "atomic address" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-address f-nil) 299 300 (dnop uimm6 "uimm6" ((MACH ORBIS-MACHS)) h-uimm6 f-uimm6) 301 302 (dnop rD "destination register" ((MACH ORBIS-MACHS)) h-gpr f-r1) 303 (dnop rA "source register A" ((MACH ORBIS-MACHS)) h-gpr f-r2) 304 (dnop rB "source register B" ((MACH ORBIS-MACHS)) h-gpr f-r3) 305 306 (define-operand 307 (name disp26) 308 (comment "pc-rel 26 bit") 309 (attrs (MACH ORBIS-MACHS)) 310 (type h-iaddr) 311 (index f-disp26) 312 (handlers (parse "disp26")) 313 ) 314 315 (define-operand 316 (name simm16) 317 (comment "16-bit signed immediate") 318 (attrs (MACH ORBIS-MACHS) SIGN-OPT) 319 (type h-simm16) 320 (index f-simm16) 321 (handlers (parse "simm16")) 322 ) 323 324 (define-operand 325 (name uimm16) 326 (comment "16-bit unsigned immediate") 327 (attrs (MACH ORBIS-MACHS)) 328 (type h-uimm16) 329 (index f-uimm16) 330 (handlers (parse "uimm16")) 331 ) 332 333 (define-operand 334 (name simm16-split) 335 (comment "split 16-bit signed immediate") 336 (attrs (MACH ORBIS-MACHS) SIGN-OPT) 337 (type h-simm16) 338 (index f-simm16-split) 339 (handlers (parse "simm16")) 340 ) 341 342 (define-operand 343 (name uimm16-split) 344 (comment "split 16-bit unsigned immediate") 345 (attrs (MACH ORBIS-MACHS)) 346 (type h-uimm16) 347 (index f-uimm16-split) 348 (handlers (parse "uimm16")) 349 ) 350 351 ; Instructions. 352 353 ; Branch releated instructions 354 355 (define-pmacro (cti-link-return) 356 (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8))) 357 ) 358 (define-pmacro (cti-transfer-control condition target) 359 ;; this mess is necessary because we're 360 ;; skipping the delay slot, but it's 361 ;; actually the start of the next basic 362 ;; block 363 (sequence () 364 (if condition 365 (delay 1 (set IAI pc target)) 366 (if sys-cpucfgr-nd 367 (delay 1 (set IAI pc (add pc 4)))) 368 ) 369 (if sys-cpucfgr-nd 370 (skip 1) 371 ) 372 ) 373 ) 374 375 (define-pmacro 376 (define-cti 377 cti-name 378 cti-comment 379 cti-attrs 380 cti-syntax 381 cti-format 382 cti-semantics) 383 (begin 384 (dni 385 cti-name 386 cti-comment 387 (.splice (MACH ORBIS-MACHS) DELAYED-CTI NOT-IN-DELAY-SLOT (.unsplice cti-attrs)) 388 cti-syntax 389 cti-format 390 (cti-semantics) 391 () 392 ) 393 ) 394 ) 395 396 (define-cti 397 l-j 398 "jump (pc-relative iaddr)" 399 (!COND-CTI UNCOND-CTI) 400 "l.j ${disp26}" 401 (+ OPC_J disp26) 402 (.pmacro () 403 (cti-transfer-control 1 disp26) 404 ) 405 ) 406 407 (define-cti 408 l-jal 409 "jump and link (pc-relative iaddr)" 410 (!COND-CTI UNCOND-CTI) 411 "l.jal ${disp26}" 412 (+ OPC_JAL disp26) 413 (.pmacro () 414 (sequence () 415 (cti-link-return) 416 (cti-transfer-control 1 disp26) 417 ) 418 ) 419 ) 420 421 (define-cti 422 l-jr 423 "jump register (absolute iaddr)" 424 (!COND-CTI UNCOND-CTI) 425 "l.jr $rB" 426 (+ OPC_JR (f-resv-25-10 0) rB (f-resv-10-11 0)) 427 (.pmacro () 428 (cti-transfer-control 1 rB) 429 ) 430 ) 431 432 (define-cti 433 l-jalr 434 "jump register and link (absolute iaddr)" 435 (!COND-CTI UNCOND-CTI) 436 "l.jalr $rB" 437 (+ OPC_JALR (f-resv-25-10 0) rB (f-resv-10-11 0) ) 438 (.pmacro () 439 (sequence () 440 (cti-link-return) 441 (cti-transfer-control 1 rB) 442 ) 443 ) 444 ) 445 446 (define-cti 447 l-bnf 448 "branch if condition bit not set (pc relative iaddr)" 449 (COND-CTI !UNCOND-CTI) 450 "l.bnf ${disp26}" 451 (+ OPC_BNF disp26) 452 (.pmacro () 453 (cti-transfer-control (not sys-sr-f) disp26) 454 ) 455 ) 456 457 (define-cti 458 l-bf 459 "branch if condition bit set (pc relative iaddr)" 460 (COND-CTI !UNCOND-CTI) 461 "l.bf ${disp26}" 462 (+ OPC_BF disp26) 463 (.pmacro () 464 (cti-transfer-control sys-sr-f disp26) 465 ) 466 ) 467 468 (dni l-trap "trap (exception)" 469 ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) 470 "l.trap ${uimm16}" 471 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_TRAP (f-resv-20-5 0) uimm16) 472 ; Do exception entry handling in C function, PC set based on SR state 473 (raise-exception EXCEPT-TRAP) 474 () 475 ) 476 477 478 (dni l-sys "syscall (exception)" 479 ; This function may not be in delay slot 480 ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) 481 482 "l.sys ${uimm16}" 483 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_SYSCALL (f-resv-20-5 0) uimm16) 484 ; Do exception entry handling in C function, PC set based on SR state 485 (raise-exception EXCEPT-SYSCALL) 486 () 487 ) 488 489 (dni l-msync "memory sync" 490 ((MACH ORBIS-MACHS)) 491 "l.msync" 492 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_MSYNC (f-resv-20-21 0)) 493 (nop) 494 () 495 ) 496 497 (dni l-psync "pipeline sync" 498 ((MACH ORBIS-MACHS)) 499 "l.psync" 500 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_PSYNC (f-resv-20-21 0)) 501 (nop) 502 () 503 ) 504 505 (dni l-csync "context sync" 506 ((MACH ORBIS-MACHS)) 507 "l.csync" 508 (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_CSYNC (f-resv-20-21 0)) 509 (nop) 510 () 511 ) 512 513 (dni l-rfe "return from exception" 514 ; This function may not be in delay slot 515 ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT FORCED-CTI) 516 517 "l.rfe" 518 (+ OPC_RFE (f-resv-25-26 0)) 519 (c-call VOID "@cpu@_rfe") 520 () 521 ) 522 523 525 ; Misc instructions 526 527 ; l.nop with immediate must be first so it handles all l.nops in sim 528 (dni l-nop-imm "nop uimm16" 529 ((MACH ORBIS-MACHS)) 530 "l.nop ${uimm16}" 531 (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) 532 (c-call VOID "@cpu@_nop" (zext UWI uimm16)) 533 () 534 ) 535 536 (if (application-is? SIMULATOR) 537 (begin) 538 (begin 539 (dni l-nop "nop" 540 ((MACH ORBIS-MACHS)) 541 "l.nop" 542 (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) 543 (nop) 544 () 545 ) 546 ) 547 ) 548 549 (dni l-movhi "movhi reg/uimm16" 550 ((MACH ORBIS-MACHS)) 551 "l.movhi $rD,$uimm16" 552 (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MOVHI uimm16) 553 (set UWI rD (sll UWI (zext UWI uimm16) (const 16))) 554 () 555 ) 556 557 (dni l-macrc "macrc reg" 558 ((MACH ORBIS-MACHS)) 559 "l.macrc $rD" 560 (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MACRC (f-uimm16 0)) 561 (sequence () 562 (set UWI rD mac-maclo) 563 (set UWI mac-maclo 0) 564 (set UWI mac-machi 0) 565 ) 566 () 567 ) 568 569 571 ; System releated instructions 572 573 (dni l-mfspr "mfspr" 574 ((MACH ORBIS-MACHS)) 575 "l.mfspr $rD,$rA,${uimm16}" 576 (+ OPC_MFSPR rD rA uimm16) 577 (set UWI rD (c-call UWI "@cpu@_mfspr" (or rA (zext UWI uimm16)))) 578 () 579 ) 580 581 (dni l-mtspr "mtspr" 582 ((MACH ORBIS-MACHS)) 583 "l.mtspr $rA,$rB,${uimm16-split}" 584 (+ OPC_MTSPR rA rB uimm16-split ) 585 (c-call VOID "@cpu@_mtspr" (or rA (zext WI uimm16-split)) rB) 586 () 587 ) 588 589 591 ; Load instructions 592 (define-pmacro (load-store-addr base offset size) 593 (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size)) 594 595 (dni l-lwz "l.lwz reg/simm16(reg)" 596 ((MACH ORBIS-MACHS)) 597 "l.lwz $rD,${simm16}($rA)" 598 (+ OPC_LWZ rD rA simm16) 599 (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) 600 () 601 ) 602 603 604 (dni l-lws "l.lws reg/simm16(reg)" 605 ((MACH ORBIS-MACHS)) 606 "l.lws $rD,${simm16}($rA)" 607 (+ OPC_LWS rD rA simm16) 608 (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4)))) 609 () 610 ) 611 612 (dni l-lwa "l.lwa reg/simm16(reg)" 613 ((MACH ORBIS-MACHS)) 614 "l.lwa $rD,${simm16}($rA)" 615 (+ OPC_LWA rD rA simm16) 616 (sequence () 617 (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) 618 (set atomic-reserve (const 1)) 619 (set atomic-address (load-store-addr rA simm16 4)) 620 ) 621 () 622 ) 623 624 (dni l-lbz "l.lbz reg/simm16(reg)" 625 ((MACH ORBIS-MACHS)) 626 "l.lbz $rD,${simm16}($rA)" 627 (+ OPC_LBZ rD rA simm16) 628 (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1)))) 629 () 630 ) 631 632 (dni l-lbs "l.lbs reg/simm16(reg)" 633 ((MACH ORBIS-MACHS)) 634 "l.lbs $rD,${simm16}($rA)" 635 (+ OPC_LBS rD rA simm16) 636 (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1)))) 637 () 638 ) 639 640 (dni l-lhz "l.lhz reg/simm16(reg)" 641 ((MACH ORBIS-MACHS)) 642 "l.lhz $rD,${simm16}($rA)" 643 (+ OPC_LHZ rD simm16 rA) 644 (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2)))) 645 () 646 ) 647 648 (dni l-lhs "l.lhs reg/simm16(reg)" 649 ((MACH ORBIS-MACHS)) 650 "l.lhs $rD,${simm16}($rA)" 651 (+ OPC_LHS rD rA simm16) 652 (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2)))) 653 () 654 ) 655 656 658 ; Store instructions 659 660 (define-pmacro (store-insn mnemonic opc-op mode size) 661 (begin 662 (dni (.sym l- mnemonic) 663 (.str "l." mnemonic " simm16(reg)/reg") 664 ((MACH ORBIS-MACHS)) 665 (.str "l." mnemonic " ${simm16-split}($rA),$rB") 666 (+ opc-op rA rB simm16-split) 667 (sequence ((SI addr)) 668 (set addr (load-store-addr rA simm16-split size)) 669 (set mode (mem mode addr) (trunc mode rB)) 670 (if (eq (and addr #xffffffc) atomic-address) 671 (set atomic-reserve (const 0)) 672 ) 673 ) 674 () 675 ) 676 ) 677 ) 678 679 (store-insn sw OPC_SW USI 4) 680 (store-insn sb OPC_SB UQI 1) 681 (store-insn sh OPC_SH UHI 2) 682 683 (dni l-swa "l.swa simm16(reg)/reg" 684 ((MACH ORBIS-MACHS)) 685 "l.swa ${simm16-split}($rA),$rB" 686 (+ OPC_SWA rA rB simm16) 687 (sequence ((SI addr) (BI flag)) 688 (set addr (load-store-addr rA simm16-split 4)) 689 (set sys-sr-f (and atomic-reserve (eq addr atomic-address))) 690 (if sys-sr-f 691 (set USI (mem USI addr) (trunc USI rB)) 692 ) 693 (set atomic-reserve (const 0)) 694 ) 695 () 696 ) 697 698 700 ; Shift and rotate instructions 701 702 (define-pmacro (shift-insn mnemonic) 703 (begin 704 (dni (.sym l- mnemonic) 705 (.str "l." mnemonic " reg/reg/reg") 706 ((MACH ORBIS-MACHS)) 707 (.str "l." mnemonic " $rD,$rA,$rB") 708 (+ OPC_ALU rD rA rB (f-resv-10-3 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) (f-resv-5-2 0) 709 OPC_ALU_REGREG_SHROT ) 710 (set UWI rD (mnemonic rA rB)) 711 () 712 ) 713 (dni (.sym l- mnemonic "i") 714 (.str "l." mnemonic " reg/reg/uimm6") 715 ((MACH ORBIS-MACHS)) 716 (.str "l." mnemonic "i $rD,$rA,${uimm6}") 717 (+ OPC_SHROTI rD rA (f-resv-15-8 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) uimm6) 718 (set rD (mnemonic rA uimm6)) 719 () 720 ) 721 ) 722 ) 723 724 (shift-insn sll) 725 (shift-insn srl) 726 (shift-insn sra) 727 (shift-insn ror) 728 729 731 ; Arithmetic insns 732 733 ; ALU op macro 734 (define-pmacro (alu-insn mnemonic) 735 (begin 736 (dni (.sym l- mnemonic) 737 (.str "l." mnemonic " reg/reg/reg") 738 ((MACH ORBIS-MACHS)) 739 (.str "l." mnemonic " $rD,$rA,$rB") 740 (+ OPC_ALU rD rA rB (f-resv-10-7 0) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) 741 (set rD (mnemonic rA rB)) 742 () 743 ) 744 ) 745 ) 746 747 (alu-insn and) 748 (alu-insn or) 749 (alu-insn xor) 750 751 (define-pmacro (alu-carry-insn mnemonic) 752 (begin 753 (dni (.sym l- mnemonic) 754 (.str "l." mnemonic " reg/reg/reg") 755 ((MACH ORBIS-MACHS)) 756 (.str "l." mnemonic " $rD,$rA,$rB") 757 (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) 758 (sequence () 759 (sequence () 760 (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA rB 0)) 761 (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA rB 0)) 762 (set rD (mnemonic WI rA rB)) 763 ) 764 (if (andif sys-sr-ov sys-sr-ove) 765 (raise-exception EXCEPT-RANGE)) 766 ) 767 () 768 ) 769 ) 770 ) 771 772 (alu-carry-insn add) 773 (alu-carry-insn sub) 774 775 (dni (l-addc) "l.addc reg/reg/reg" 776 ((MACH ORBIS-MACHS)) 777 ("l.addc $rD,$rA,$rB") 778 (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_ADDC) 779 (sequence () 780 (sequence ((BI tmp-sys-sr-cy)) 781 (set BI tmp-sys-sr-cy sys-sr-cy) 782 (set BI sys-sr-cy (addc-cflag WI rA rB tmp-sys-sr-cy)) 783 (set BI sys-sr-ov (addc-oflag WI rA rB tmp-sys-sr-cy)) 784 (set rD (addc WI rA rB tmp-sys-sr-cy)) 785 ) 786 (if (andif sys-sr-ov sys-sr-ove) 787 (raise-exception EXCEPT-RANGE)) 788 ) 789 () 790 ) 791 792 (dni (l-mul) "l.mul reg/reg/reg" 793 ((MACH ORBIS-MACHS)) 794 ("l.mul $rD,$rA,$rB") 795 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MUL) 796 (sequence () 797 (sequence () 798 ; 2's complement overflow 799 (set BI sys-sr-ov (mul-o2flag WI rA rB)) 800 ; 1's complement overflow 801 (set BI sys-sr-cy (mul-o1flag WI rA rB)) 802 (set rD (mul WI rA rB)) 803 ) 804 (if (andif sys-sr-ov sys-sr-ove) 805 (raise-exception EXCEPT-RANGE)) 806 ) 807 () 808 ) 809 810 (dni (l-mulu) "l.mulu reg/reg/reg" 811 ((MACH ORBIS-MACHS)) 812 ("l.mulu $rD,$rA,$rB") 813 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULU) 814 (sequence () 815 (sequence () 816 ; 2's complement overflow 817 (set BI sys-sr-ov 0) 818 ; 1's complement overflow 819 (set BI sys-sr-cy (mul-o1flag UWI rA rB)) 820 (set rD (mul UWI rA rB)) 821 ) 822 (if (andif sys-sr-ov sys-sr-ove) 823 (raise-exception EXCEPT-RANGE)) 824 ) 825 () 826 ) 827 828 (dni l-div "divide (signed)" 829 ((MACH ORBIS-MACHS)) 830 "l.div $rD,$rA,$rB" 831 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIV) 832 (sequence () 833 (if (ne rB 0) 834 (sequence () 835 (set BI sys-sr-cy 0) 836 (set WI rD (div WI rA rB)) 837 ) 838 (set BI sys-sr-cy 1) 839 ) 840 (set BI sys-sr-ov 0) 841 (if (andif sys-sr-cy sys-sr-ove) 842 (raise-exception EXCEPT-RANGE)) 843 ) 844 () 845 ) 846 847 (dni l-divu "divide (unsigned)" 848 ((MACH ORBIS-MACHS)) 849 "l.divu $rD,$rA,$rB" 850 (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIVU) 851 (sequence () 852 (if (ne rB 0) 853 (sequence () 854 (set BI sys-sr-cy 0) 855 (set rD (udiv UWI rA rB)) 856 ) 857 (set BI sys-sr-cy 1) 858 ) 859 (set BI sys-sr-ov 0) 860 (if (andif sys-sr-cy sys-sr-ove) 861 (raise-exception EXCEPT-RANGE)) 862 ) 863 () 864 ) 865 866 (dni l-ff1 "find first '1'" 867 ((MACH ORBIS-MACHS)) 868 "l.ff1 $rD,$rA" 869 (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_FFL1) 870 (set rD (c-call UWI "@cpu@_ff1" rA)) 871 () 872 ) 873 874 (dni l-fl1 "find last '1'" 875 ((MACH ORBIS-MACHS)) 876 "l.fl1 $rD,$rA" 877 (+ OPC_ALU rD rA rB (f-resv-10-7 #x10) OPC_ALU_REGREG_FFL1) 878 (set rD (c-call UWI "@cpu@_fl1" rA)) 879 () 880 ) 881 882 883 (define-pmacro (alu-insn-simm mnemonic) 884 (begin 885 (dni (.sym l- mnemonic "i") 886 (.str "l." mnemonic " reg/reg/simm16") 887 ((MACH ORBIS-MACHS)) 888 (.str "l." mnemonic "i $rD,$rA,$simm16") 889 (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) 890 (set rD (mnemonic rA (ext WI simm16))) 891 () 892 ) 893 ) 894 ) 895 896 (define-pmacro (alu-insn-uimm mnemonic) 897 (begin 898 (dni (.sym l- mnemonic "i") 899 (.str "l." mnemonic " reg/reg/uimm16") 900 ((MACH ORBIS-MACHS)) 901 (.str "l." mnemonic "i $rD,$rA,$uimm16") 902 (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA uimm16) 903 (set rD (mnemonic rA (zext UWI uimm16))) 904 () 905 ) 906 ) 907 ) 908 909 (alu-insn-uimm and) 910 (alu-insn-uimm or) 911 (alu-insn-simm xor) 912 913 (define-pmacro (alu-carry-insn-simm mnemonic) 914 (begin 915 (dni (.sym l- mnemonic "i") 916 (.str "l." mnemonic "i reg/reg/simm16") 917 ((MACH ORBIS-MACHS)) 918 (.str "l." mnemonic "i $rD,$rA,$simm16") 919 (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) 920 (sequence () 921 (sequence () 922 (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA (ext WI simm16) 0)) 923 (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA (ext WI simm16) 0)) 924 (set rD (mnemonic WI rA (ext WI simm16))) 925 ) 926 (if (andif sys-sr-ov sys-sr-ove) 927 (raise-exception EXCEPT-RANGE)) 928 ) 929 () 930 ) 931 ) 932 ) 933 934 (alu-carry-insn-simm add) 935 936 (dni (l-addic) 937 ("l.addic reg/reg/simm16") 938 ((MACH ORBIS-MACHS)) 939 ("l.addic $rD,$rA,$simm16") 940 (+ OPC_ADDIC rD rA simm16) 941 (sequence () 942 (sequence ((BI tmp-sys-sr-cy)) 943 (set BI tmp-sys-sr-cy sys-sr-cy) 944 (set BI sys-sr-cy (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy)) 945 (set BI sys-sr-ov (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy)) 946 (set WI rD (addc WI rA (ext WI simm16) tmp-sys-sr-cy)) 947 ) 948 (if (andif sys-sr-ov sys-sr-ove) 949 (raise-exception EXCEPT-RANGE)) 950 ) 951 () 952 ) 953 954 (dni (l-muli) 955 "l.muli reg/reg/simm16" 956 ((MACH ORBIS-MACHS)) 957 ("l.muli $rD,$rA,$simm16") 958 (+ OPC_MULI rD rA simm16) 959 (sequence () 960 (sequence () 961 ; 2's complement overflow 962 (set sys-sr-ov (mul-o2flag WI rA (ext WI simm16))) 963 ; 1's complement overflow 964 (set sys-sr-cy (mul-o1flag UWI rA (ext UWI simm16))) 965 (set rD (mul WI rA (ext WI simm16))) 966 ) 967 (if (andif sys-sr-ov sys-sr-ove) 968 (raise-exception EXCEPT-RANGE)) 969 ) 970 () 971 ) 972 973 (define-pmacro (extbh-insn mnemonic extop extmode truncmode) 974 (begin 975 (dni (.sym l- mnemonic) 976 (.str "l." mnemonic " reg/reg") 977 ((MACH ORBIS-MACHS)) 978 (.str "l." mnemonic " $rD,$rA") 979 (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTBHS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTBH) 980 (set rD (extop extmode (trunc truncmode rA))) 981 () 982 ) 983 ) 984 ) 985 986 (extbh-insn exths ext WI HI) 987 (extbh-insn extbs ext WI QI) 988 (extbh-insn exthz zext UWI UHI) 989 (extbh-insn extbz zext UWI UQI) 990 991 (define-pmacro (extw-insn mnemonic extop extmode truncmode) 992 (begin 993 (dni (.sym l- mnemonic) 994 (.str "l." mnemonic " reg/reg") 995 ((MACH ORBIS-MACHS)) 996 (.str "l." mnemonic " $rD,$rA") 997 (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTWS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTW) 998 (set rD (extop extmode (trunc truncmode rA))) 999 () 1000 ) 1001 ) 1002 ) 1003 1004 (extw-insn extws ext WI SI) 1005 (extw-insn extwz zext USI USI) 1006 1007 (dni l-cmov 1008 "l.cmov reg/reg/reg" 1009 ((MACH ORBIS-MACHS)) 1010 "l.cmov $rD,$rA,$rB" 1011 (+ OPC_ALU rD rA rB (f-resv-10-1 0) (f-op-9-2 0) (f-resv-7-4 0) OPC_ALU_REGREG_CMOV) 1012 (if sys-sr-f 1013 (set UWI rD rA) 1014 (set UWI rD rB) 1015 ) 1016 () 1017 ) 1018 1019 ; Compare instructions 1020 1021 ; Ordering compare 1022 (define-pmacro (sf-insn op) 1023 (begin 1024 (dni (.sym l- "sf" op "s") ; l-sfgts 1025 (.str "l.sf" op "s reg/reg") ; "l.sfgts reg/reg" 1026 ((MACH ORBIS-MACHS)) 1027 (.str "l.sf" op "s $rA,$rB") ; "l.sfgts $rA,$rB" 1028 (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "S") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTS rA rB (f-resv-10-11 0)) 1029 (set sys-sr-f (op WI rA rB)) ; (set sys-sr-f (gt WI rA rB)) 1030 () 1031 ) 1032 (dni (.sym l- "sf" op "si") ; l-sfgtsi 1033 (.str "l.sf" op "si reg/simm16") ; "l.sfgtsi reg/simm16" 1034 ((MACH ORBIS-MACHS)) 1035 (.str "l.sf" op "si $rA,$simm16") ; "l.sfgtsi $rA,$simm16" 1036 (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "S") rA simm16) ; (+ OPC_SFI OPC_SF_GTS rA simm16) 1037 (set sys-sr-f (op WI rA (ext WI simm16))) ; (set sys-sr-f (gt WI rA (ext WI simm16))) 1038 () 1039 ) 1040 (dni (.sym l- "sf" op "u") ; l-sfgtu 1041 (.str "l.sf" op "u reg/reg") ; "l.sfgtu reg/reg" 1042 ((MACH ORBIS-MACHS)) 1043 (.str "l.sf" op "u $rA,$rB") ; "l.sfgtu $rA,$rB" 1044 (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "U") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTU rA rB (f-resv-10-11 0)) 1045 (set sys-sr-f ((.sym op "u") WI rA rB)) ; (set sys-sr-f (gtu WI rA rB)) 1046 () 1047 ) 1048 ; immediate is sign extended even for unsigned compare 1049 (dni (.sym l- "sf" op "ui") ; l-sfgtui 1050 (.str "l.sf" op "ui reg/simm16") ; "l.sfgtui reg/uimm16" 1051 ((MACH ORBIS-MACHS)) 1052 (.str "l.sf" op "ui $rA,$simm16") ; "l.sfgtui $rA,$simm16" 1053 (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "U") rA simm16) ; (+ OPC_SFI OPC_SF_GTU rA simm16) 1054 (set sys-sr-f ((.sym op "u") WI rA (ext WI simm16))) ; (set sys-sr-f (gtu WI rA (ext WI simm16))) 1055 () 1056 ) 1057 ) 1058 ) 1059 1060 (sf-insn gt) 1061 (sf-insn ge) 1062 (sf-insn lt) 1063 (sf-insn le) 1064 1065 ; Equality compare 1066 (define-pmacro (sf-insn-eq op) 1067 (begin 1068 (dni (.sym l- "sf" op) 1069 (.str "l." op " reg/reg") 1070 ((MACH ORBIS-MACHS)) 1071 (.str "l.sf" op " $rA,$rB") 1072 (+ OPC_SF (.sym "OPC_SF_" (.upcase op)) rA rB (f-resv-10-11 0)) 1073 (set sys-sr-f (op WI rA rB)) 1074 () 1075 ) 1076 (dni (.sym l- "sf" op "i") 1077 (.str "l.sf" op "i reg/simm16") 1078 ((MACH ORBIS-MACHS)) 1079 (.str "l.sf" op "i $rA,$simm16") 1080 (+ OPC_SFI (.sym "OPC_SF_" (.upcase op)) rA simm16) 1081 (set sys-sr-f (op WI rA (ext WI simm16))) 1082 () 1083 ) 1084 ) 1085 ) 1086 1087 (sf-insn-eq eq) 1088 (sf-insn-eq ne) 1089 1090 (dni l-mac 1091 "l.mac reg/reg" 1092 ((MACH ORBIS-MACHS)) 1093 "l.mac $rA,$rB" 1094 (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MAC) 1095 (sequence ((WI prod) (DI result)) 1096 (set WI prod (mul WI rA rB)) 1097 (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod))) 1098 (set SI mac-machi (subword SI result 0)) 1099 (set SI mac-maclo (subword SI result 1)) 1100 ) 1101 () 1102 ) 1103 1104 (dni l-msb 1105 "l.msb reg/reg" 1106 ((MACH ORBIS-MACHS)) 1107 "l.msb $rA,$rB" 1108 (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSB) 1109 (sequence ((WI prod) (DI result)) 1110 (set WI prod (mul WI rA rB)) 1111 (set DI result (sub (join DI SI mac-machi mac-maclo) (ext DI prod))) 1112 (set SI mac-machi (subword SI result 0)) 1113 (set SI mac-maclo (subword SI result 1)) 1114 ) 1115 () 1116 ) 1117 1118 (dni l-maci 1119 "l.maci reg/simm16" 1120 ((MACH ORBIS-MACHS)) 1121 "l.maci $rA,${simm16}" 1122 (+ OPC_MACI (f-resv-25-5 0) rA simm16) 1123 (sequence ((WI prod) (DI result)) 1124 (set WI prod (mul WI (ext WI simm16) rA)) 1125 (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod))) 1126 (set SI mac-machi (subword SI result 0)) 1127 (set SI mac-maclo (subword SI result 1)) 1128 ) 1129 () 1130 ) 1131 1132 (define-pmacro (cust-insn cust-num) 1133 (begin 1134 (dni (.sym l- "cust" cust-num) 1135 (.str "l.cust" cust-num) 1136 ((MACH ORBIS-MACHS)) 1137 (.str "l.cust" cust-num) 1138 (+ (.sym OPC_CUST cust-num) (f-resv-25-26 0)) 1139 (nop) 1140 () 1141 ) 1142 ) 1143 ) 1144 1145 (cust-insn "1") 1146 (cust-insn "2") 1147 (cust-insn "3") 1148 (cust-insn "4") 1149 (cust-insn "5") 1150 (cust-insn "6") 1151 (cust-insn "7") 1152 (cust-insn "8") 1153
