1 @c Copyright (C) 1997-2014 Free Software Foundation, Inc. 2 @c This is part of the GAS manual. 3 @c For copying conditions, see the file as.texinfo. 4 @ifset GENERIC 5 @page 6 @node D30V-Dependent 7 @chapter D30V Dependent Features 8 @end ifset 9 @ifclear GENERIC 10 @node Machine Dependencies 11 @chapter D30V Dependent Features 12 @end ifclear 13 14 @cindex D30V support 15 @menu 16 * D30V-Opts:: D30V Options 17 * D30V-Syntax:: Syntax 18 * D30V-Float:: Floating Point 19 * D30V-Opcodes:: Opcodes 20 @end menu 21 22 @node D30V-Opts 23 @section D30V Options 24 @cindex options, D30V 25 @cindex D30V options 26 The Mitsubishi D30V version of @code{@value{AS}} has a few machine 27 dependent options. 28 29 @table @samp 30 @item -O 31 The D30V can often execute two sub-instructions in parallel. When this option 32 is used, @code{@value{AS}} will attempt to optimize its output by detecting when 33 instructions can be executed in parallel. 34 35 @item -n 36 When this option is used, @code{@value{AS}} will issue a warning every 37 time it adds a nop instruction. 38 39 @item -N 40 When this option is used, @code{@value{AS}} will issue a warning if it 41 needs to insert a nop after a 32-bit multiply before a load or 16-bit 42 multiply instruction. 43 @end table 44 45 @node D30V-Syntax 46 @section Syntax 47 @cindex D30V syntax 48 @cindex syntax, D30V 49 50 The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. 51 The differences are detailed below. 52 53 @menu 54 * D30V-Size:: Size Modifiers 55 * D30V-Subs:: Sub-Instructions 56 * D30V-Chars:: Special Characters 57 * D30V-Guarded:: Guarded Execution 58 * D30V-Regs:: Register Names 59 * D30V-Addressing:: Addressing Modes 60 @end menu 61 62 63 @node D30V-Size 64 @subsection Size Modifiers 65 @cindex D30V size modifiers 66 @cindex size modifiers, D30V 67 The D30V version of @code{@value{AS}} uses the instruction names in the D30V 68 Architecture Manual. However, the names in the manual are sometimes ambiguous. 69 There are instruction names that can assemble to a short or long form opcode. 70 How does the assembler pick the correct form? @code{@value{AS}} will always pick the 71 smallest form if it can. When dealing with a symbol that is not defined yet when a 72 line is being assembled, it will always use the long form. If you need to force the 73 assembler to use either the short or long form of the instruction, you can append 74 either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing 75 an assembly program and you want to do a branch to a symbol that is defined later 76 in your program, you can write @samp{bra.s foo}. 77 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which 78 have both short and long forms. 79 80 @node D30V-Subs 81 @subsection Sub-Instructions 82 @cindex D30V sub-instructions 83 @cindex sub-instructions, D30V 84 The D30V assembler takes as input a series of instructions, either one-per-line, 85 or in the special two-per-line format described in the next section. Some of these 86 instructions will be short-form or sub-instructions. These sub-instructions can be packed 87 into a single instruction. The assembler will do this automatically. It will also detect 88 when it should not pack instructions. For example, when a label is defined, the next 89 instruction will never be packaged with the previous one. Whenever a branch and link 90 instruction is called, it will not be packaged with the next instruction so the return 91 address will be valid. Nops are automatically inserted when necessary. 92 93 If you do not want the assembler automatically making these decisions, you can control 94 the packaging and execution type (parallel or sequential) with the special execution 95 symbols described in the next section. 96 97 @node D30V-Chars 98 @subsection Special Characters 99 @cindex line comment character, D30V 100 @cindex D30V line comment character 101 A semicolon (@samp{;}) can be used anywhere on a line to start a 102 comment that extends to the end of the line. 103 104 If a @samp{#} appears as the first character of a line, the whole line 105 is treated as a comment, but in this case the line could also be a 106 logical line number directive (@pxref{Comments}) or a preprocessor 107 control command (@pxref{Preprocessing}). 108 109 @cindex sub-instruction ordering, D30V 110 @cindex D30V sub-instruction ordering 111 Sub-instructions may be executed in order, in reverse-order, or in parallel. 112 Instructions listed in the standard one-per-line format will be executed 113 sequentially unless you use the @samp{-O} option. 114 115 To specify the executing order, use the following symbols: 116 @table @samp 117 @item -> 118 Sequential with instruction on the left first. 119 120 @item <- 121 Sequential with instruction on the right first. 122 123 @item || 124 Parallel 125 @end table 126 127 The D30V syntax allows either one instruction per line, one instruction per line with 128 the execution symbol, or two instructions per line. For example 129 @table @code 130 @item abs r2,r3 -> abs r4,r5 131 Execute these sequentially. The instruction on the right is in the right 132 container and is executed second. 133 134 @item abs r2,r3 <- abs r4,r5 135 Execute these reverse-sequentially. The instruction on the right is in the right 136 container, and is executed first. 137 138 @item abs r2,r3 || abs r4,r5 139 Execute these in parallel. 140 141 @item ldw r2,@@(r3,r4) || 142 @itemx mulx r6,r8,r9 143 Two-line format. Execute these in parallel. 144 145 @item mulx a0,r8,r9 146 @itemx stw r2,@@(r3,r4) 147 Two-line format. Execute these sequentially unless @samp{-O} option is 148 used. If the @samp{-O} option is used, the assembler will determine if 149 the instructions could be done in parallel (the above two instructions 150 can be done in parallel), and if so, emit them as parallel instructions. 151 The assembler will put them in the proper containers. In the above 152 example, the assembler will put the @samp{stw} instruction in left 153 container and the @samp{mulx} instruction in the right container. 154 155 @item stw r2,@@(r3,r4) -> 156 @itemx mulx a0,r8,r9 157 Two-line format. Execute the @samp{stw} instruction followed by the 158 @samp{mulx} instruction sequentially. The first instruction goes in the 159 left container and the second instruction goes into right container. 160 The assembler will give an error if the machine ordering constraints are 161 violated. 162 163 @item stw r2,@@(r3,r4) <- 164 @itemx mulx a0,r8,r9 165 Same as previous example, except that the @samp{mulx} instruction is 166 executed before the @samp{stw} instruction. 167 @end table 168 169 @cindex symbol names, @samp{$} in 170 @cindex @code{$} in symbol names 171 Since @samp{$} has no special meaning, you may use it in symbol names. 172 173 @node D30V-Guarded 174 @subsection Guarded Execution 175 @cindex D30V Guarded Execution 176 @code{@value{AS}} supports the full range of guarded execution 177 directives for each instruction. Just append the directive after the 178 instruction proper. The directives are: 179 180 @table @samp 181 @item /tx 182 Execute the instruction if flag f0 is true. 183 @item /fx 184 Execute the instruction if flag f0 is false. 185 @item /xt 186 Execute the instruction if flag f1 is true. 187 @item /xf 188 Execute the instruction if flag f1 is false. 189 @item /tt 190 Execute the instruction if both flags f0 and f1 are true. 191 @item /tf 192 Execute the instruction if flag f0 is true and flag f1 is false. 193 @end table 194 195 @node D30V-Regs 196 @subsection Register Names 197 @cindex D30V registers 198 @cindex registers, D30V 199 You can use the predefined symbols @samp{r0} through @samp{r63} to refer 200 to the D30V registers. You can also use @samp{sp} as an alias for 201 @samp{r63} and @samp{link} as an alias for @samp{r62}. The accumulators 202 are @samp{a0} and @samp{a1}. 203 204 The D30V also has predefined symbols for these control registers and status bits: 205 @table @code 206 @item psw 207 Processor Status Word 208 @item bpsw 209 Backup Processor Status Word 210 @item pc 211 Program Counter 212 @item bpc 213 Backup Program Counter 214 @item rpt_c 215 Repeat Count 216 @item rpt_s 217 Repeat Start address 218 @item rpt_e 219 Repeat End address 220 @item mod_s 221 Modulo Start address 222 @item mod_e 223 Modulo End address 224 @item iba 225 Instruction Break Address 226 @item f0 227 Flag 0 228 @item f1 229 Flag 1 230 @item f2 231 Flag 2 232 @item f3 233 Flag 3 234 @item f4 235 Flag 4 236 @item f5 237 Flag 5 238 @item f6 239 Flag 6 240 @item f7 241 Flag 7 242 @item s 243 Same as flag 4 (saturation flag) 244 @item v 245 Same as flag 5 (overflow flag) 246 @item va 247 Same as flag 6 (sticky overflow flag) 248 @item c 249 Same as flag 7 (carry/borrow flag) 250 @item b 251 Same as flag 7 (carry/borrow flag) 252 @end table 253 254 @node D30V-Addressing 255 @subsection Addressing Modes 256 @cindex addressing modes, D30V 257 @cindex D30V addressing modes 258 @code{@value{AS}} understands the following addressing modes for the D30V. 259 @code{R@var{n}} in the following refers to any of the numbered 260 registers, but @emph{not} the control registers. 261 @table @code 262 @item R@var{n} 263 Register direct 264 @item @@R@var{n} 265 Register indirect 266 @item @@R@var{n}+ 267 Register indirect with post-increment 268 @item @@R@var{n}- 269 Register indirect with post-decrement 270 @item @@-SP 271 Register indirect with pre-decrement 272 @item @@(@var{disp}, R@var{n}) 273 Register indirect with displacement 274 @item @var{addr} 275 PC relative address (for branch or rep). 276 @item #@var{imm} 277 Immediate data (the @samp{#} is optional and ignored) 278 @end table 279 280 @node D30V-Float 281 @section Floating Point 282 @cindex floating point, D30V 283 @cindex D30V floating point 284 The D30V has no hardware floating point, but the @code{.float} and @code{.double} 285 directives generates @sc{ieee} floating-point numbers for compatibility 286 with other development tools. 287 288 @node D30V-Opcodes 289 @section Opcodes 290 @cindex D30V opcode summary 291 @cindex opcode summary, D30V 292 @cindex mnemonics, D30V 293 @cindex instruction summary, D30V 294 For detailed information on the D30V machine instruction set, see 295 @cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications} 296 (Mitsubishi Electric Corp.). 297 @code{@value{AS}} implements all the standard D30V opcodes. The only changes are those 298 described in the section on size modifiers 299 300
