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      1 /* ia64-opc-i.c -- IA-64 `I' opcode table.
      2    Copyright (C) 1998-2014 Free Software Foundation, Inc.
      3    Contributed by David Mosberger-Tang <davidm (at) hpl.hp.com>
      4 
      5    This file is part of the GNU opcodes library.
      6 
      7    This library is free software; you can redistribute it and/or modify
      8    it under the terms of the GNU General Public License as published by
      9    the Free Software Foundation; either version 3, or (at your option)
     10    any later version.
     11 
     12    It is distributed in the hope that it will be useful, but WITHOUT
     13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     15    License for more details.
     16 
     17    You should have received a copy of the GNU General Public License
     18    along with this file; see the file COPYING.  If not, write to the
     19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
     20    MA 02110-1301, USA.  */
     21 
     22 #include "ia64-opc.h"
     23 
     24 #define I0	IA64_TYPE_I, 0
     25 #define I	IA64_TYPE_I, 1
     26 #define I2	IA64_TYPE_I, 2
     27 
     28 /* instruction bit fields: */
     29 #define bC(x)		(((ia64_insn) ((x) & 0x1)) << 12)
     30 #define bIh(x)		(((ia64_insn) ((x) & 0x1)) << 23)
     31 #define bTa(x)		(((ia64_insn) ((x) & 0x1)) << 33)
     32 #define bTag13(x)	(((ia64_insn) ((x) & 0x1)) << 33)
     33 #define bTb(x)		(((ia64_insn) ((x) & 0x1)) << 36)
     34 #define bVc(x)		(((ia64_insn) ((x) & 0x1)) << 20)
     35 #define bVe(x)		(((ia64_insn) ((x) & 0x1)) << 32)
     36 #define bWh(x)		(((ia64_insn) ((x) & 0x3)) << 20)
     37 #define bX(x)		(((ia64_insn) ((x) & 0x1)) << 33)
     38 #define bXb(x)		(((ia64_insn) ((x) & 0x1)) << 22)
     39 #define bXc(x)		(((ia64_insn) ((x) & 0x1)) << 19)
     40 #define bX2(x)		(((ia64_insn) ((x) & 0x3)) << 34)
     41 #define bX2a(x)		(((ia64_insn) ((x) & 0x3)) << 34)
     42 #define bX2b(x)		(((ia64_insn) ((x) & 0x3)) << 28)
     43 #define bX2c(x)		(((ia64_insn) ((x) & 0x3)) << 30)
     44 #define bX3(x)		(((ia64_insn) ((x) & 0x7)) << 33)
     45 #define bX6(x)		(((ia64_insn) ((x) & 0x3f)) << 27)
     46 #define bYa(x)		(((ia64_insn) ((x) & 0x1)) << 13)
     47 #define bYb(x)		(((ia64_insn) ((x) & 0x1)) << 26)
     48 #define bZa(x)		(((ia64_insn) ((x) & 0x1)) << 36)
     49 #define bZb(x)		(((ia64_insn) ((x) & 0x1)) << 33)
     50 
     51 /* instruction bit masks: */
     52 #define mC	bC (-1)
     53 #define mIh	bIh (-1)
     54 #define mTa	bTa (-1)
     55 #define mTag13	bTag13 (-1)
     56 #define mTb	bTb (-1)
     57 #define mVc	bVc (-1)
     58 #define mVe	bVe (-1)
     59 #define mWh	bWh (-1)
     60 #define mX	bX (-1)
     61 #define mXb	bXb (-1)
     62 #define mXc	bXc (-1)
     63 #define mX2	bX2 (-1)
     64 #define mX2a	bX2a (-1)
     65 #define mX2b	bX2b (-1)
     66 #define mX2c	bX2c (-1)
     67 #define mX3	bX3 (-1)
     68 #define mX6	bX6 (-1)
     69 #define mYa	bYa (-1)
     70 #define mYb	bYb (-1)
     71 #define mZa	bZa (-1)
     72 #define mZb	bZb (-1)
     73 
     74 #define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
     75 	(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
     76 	(mOp | mZa | mZb | mVe | mX2a | mX2b)
     77 #define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
     78   (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
     79 	(mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
     80 #define OpX2X(a,b,c)		(bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
     81 #define OpX2XYa(a,b,c,d)	(bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
     82 				(mOp | mX2 | mX | mYa)
     83 #define OpX2XYb(a,b,c,d)	(bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
     84 				(mOp | mX2 | mX | mYb)
     85 #define OpX2TaTbYaC(a,b,c,d,e,f) \
     86 	(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
     87 	(mOp | mX2 | mTa | mTb | mYa | mC)
     88 #define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \
     89 	(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \
     90 	(mOp | mX2 | mTa | mTb | mYa | mXc | mC)
     91 #define OpX3(a,b)		(bOp (a) | bX3 (b)), (mOp | mX3)
     92 #define OpX3X6(a,b,c)		(bOp (a) | bX3 (b) | bX6(c)), \
     93 				(mOp | mX3 | mX6)
     94 #define OpX3X6Yb(a,b,c,d)	(bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \
     95 				(mOp | mX3 | mX6 | mYb)
     96 #define OpX3XbIhWh(a,b,c,d,e) \
     97   (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
     98   (mOp | mX3 | mXb | mIh | mWh)
     99 #define OpX3XbIhWhTag13(a,b,c,d,e,f) \
    100      (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
    101      (mOp | mX3 | mXb | mIh | mWh | mTag13)
    102 
    103 #define FULL17 ((ia64_insn)0x10ff001fc0LL)
    104 
    105 /* Used to initialise unused fields in ia64_opcode struct,
    106    in order to stop gcc from complaining.  */
    107 #define EMPTY 0,0,NULL
    108 
    109 struct ia64_opcode ia64_opcodes_i[] =
    110   {
    111     /* I-type instruction encodings (sorted according to major opcode).  */
    112 
    113     {"break.i",	I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
    114     {"nop.i",	I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL},
    115     {"hint.i",	I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL},
    116     {"chk.s.i",	I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
    117 
    118     {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
    119 #define MOV(a,b,c,d) \
    120     I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
    121     {"mov.sptk",		MOV (7, 0, 0, 0)},
    122     {"mov.sptk.imp",		MOV (7, 0, 1, 0)},
    123     {"mov",			MOV (7, 0, 0, 1)},
    124     {"mov.imp",			MOV (7, 0, 1, 1)},
    125     {"mov.dptk",		MOV (7, 0, 0, 2)},
    126     {"mov.dptk.imp",		MOV (7, 0, 1, 2)},
    127     {"mov.ret.sptk",		MOV (7, 1, 0, 0)},
    128     {"mov.ret.sptk.imp",	MOV (7, 1, 1, 0)},
    129     {"mov.ret",			MOV (7, 1, 0, 1)},
    130     {"mov.ret.imp",		MOV (7, 1, 1, 1)},
    131     {"mov.ret.dptk",		MOV (7, 1, 0, 2)},
    132     {"mov.ret.dptk.imp",	MOV (7, 1, 1, 2)},
    133 #undef MOV
    134     {"mov",	I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
    135     {"mov",	I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
    136     /* Don't remove one of the seemingly redundant FULL17-s.  */
    137     {"mov",	I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
    138     {"mov",	I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY},
    139     {"mov",	I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
    140     {"mov",	I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
    141     {"mov.i",	I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
    142     {"mov.i",	I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY},
    143     {"mov.i",	I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY},
    144     {"zxt1",	I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
    145     {"zxt2",	I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
    146     {"zxt4",	I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
    147     {"sxt1",	I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
    148     {"sxt2",	I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
    149     {"sxt4",	I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
    150     {"czx1.l",	I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
    151     {"czx2.l",	I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
    152     {"czx1.r",	I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
    153     {"czx2.r",	I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
    154 
    155     {"dep",	I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
    156 
    157     {"shrp",	I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
    158 
    159     {"shr.u",	I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
    160      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
    161     {"extr.u",	I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY},
    162 
    163     {"shr",	I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
    164      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
    165     {"extr",	I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY},
    166 
    167     {"shl",	I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
    168      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
    169     {"dep.z",	I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
    170     {"dep.z",	I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
    171     {"dep",	I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
    172 #define TF(a,b,c) \
    173 	I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY
    174 #define TFCM(a,b,c) \
    175 	I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL
    176     {"tf.z",		 TF   (0, 0, 0)},
    177     {"tf.nz",		 TFCM (0, 0, 0)},
    178     {"tf.z.unc",	 TF   (0, 0, 1)},
    179     {"tf.nz.unc",	 TFCM (0, 0, 1)},
    180     {"tf.z.and",	 TF   (0, 1, 0)},
    181     {"tf.nz.andcm",	 TFCM (0, 1, 0)},
    182     {"tf.nz.and",	 TF   (0, 1, 1)},
    183     {"tf.z.andcm",	 TFCM (0, 1, 1)},
    184     {"tf.z.or",		 TF   (1, 0, 0)},
    185     {"tf.nz.orcm",	 TFCM (1, 0, 0)},
    186     {"tf.nz.or",	 TF   (1, 0, 1)},
    187     {"tf.z.orcm",	 TFCM (1, 0, 1)},
    188     {"tf.z.or.andcm",	 TF   (1, 1, 0)},
    189     {"tf.nz.and.orcm",	 TFCM (1, 1, 0)},
    190     {"tf.nz.or.andcm",	 TF   (1, 1, 1)},
    191     {"tf.z.and.orcm",	 TFCM (1, 1, 1)},
    192 #undef TF
    193 #undef TFCM
    194 #define TBIT(a,b,c,d) \
    195         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
    196 #define TBITCM(a,b,c,d)	\
    197         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL
    198     {"tbit.z",		 TBIT   (0, 0, 0, 0)},
    199     {"tbit.nz",		 TBITCM (0, 0, 0, 0)},
    200     {"tbit.z.unc",	 TBIT   (0, 0, 0, 1)},
    201     {"tbit.nz.unc",	 TBITCM (0, 0, 0, 1)},
    202     {"tbit.z.and",	 TBIT   (0, 1, 0, 0)},
    203     {"tbit.nz.andcm",	 TBITCM (0, 1, 0, 0)},
    204     {"tbit.nz.and",	 TBIT   (0, 1, 0, 1)},
    205     {"tbit.z.andcm",	 TBITCM (0, 1, 0, 1)},
    206     {"tbit.z.or",	 TBIT   (1, 0, 0, 0)},
    207     {"tbit.nz.orcm",	 TBITCM (1, 0, 0, 0)},
    208     {"tbit.nz.or",	 TBIT   (1, 0, 0, 1)},
    209     {"tbit.z.orcm",	 TBITCM (1, 0, 0, 1)},
    210     {"tbit.z.or.andcm",	 TBIT   (1, 1, 0, 0)},
    211     {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
    212     {"tbit.nz.or.andcm", TBIT   (1, 1, 0, 1)},
    213     {"tbit.z.and.orcm",  TBITCM (1, 1, 0, 1)},
    214 #undef TBIT
    215 #undef TBITCM
    216 #define TNAT(a,b,c,d) \
    217 	I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY
    218 #define TNATCM(a,b,c,d) \
    219 	I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL
    220     {"tnat.z",		 TNAT   (0, 0, 1, 0)},
    221     {"tnat.nz",		 TNATCM (0, 0, 1, 0)},
    222     {"tnat.z.unc",	 TNAT   (0, 0, 1, 1)},
    223     {"tnat.nz.unc",	 TNATCM (0, 0, 1, 1)},
    224     {"tnat.z.and",	 TNAT   (0, 1, 1, 0)},
    225     {"tnat.nz.andcm",	 TNATCM (0, 1, 1, 0)},
    226     {"tnat.nz.and",	 TNAT   (0, 1, 1, 1)},
    227     {"tnat.z.andcm",	 TNATCM (0, 1, 1, 1)},
    228     {"tnat.z.or",	 TNAT   (1, 0, 1, 0)},
    229     {"tnat.nz.orcm",	 TNATCM (1, 0, 1, 0)},
    230     {"tnat.nz.or",	 TNAT   (1, 0, 1, 1)},
    231     {"tnat.z.orcm",	 TNATCM (1, 0, 1, 1)},
    232     {"tnat.z.or.andcm",	 TNAT   (1, 1, 1, 0)},
    233     {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
    234     {"tnat.nz.or.andcm", TNAT   (1, 1, 1, 1)},
    235     {"tnat.z.and.orcm",  TNATCM (1, 1, 1, 1)},
    236 #undef TNAT
    237 #undef TNATCM
    238 
    239     {"pmpyshr2",   I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY},
    240     {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY},
    241     {"pmpy2.r",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY},
    242     {"pmpy2.l",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY},
    243     {"mix1.r",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
    244     {"mix2.r",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
    245     {"mix4.r",	   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
    246     {"mix1.l",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
    247     {"mix2.l",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
    248     {"mix4.l",	   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
    249     {"pack2.uss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY},
    250     {"pack2.sss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
    251     {"pack4.sss",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
    252     {"unpack1.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
    253     {"unpack2.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
    254     {"unpack4.h",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
    255     {"unpack1.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
    256     {"unpack2.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
    257     {"unpack4.l",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
    258     {"pmin1.u",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY},
    259     {"pmax1.u",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY},
    260     {"pmin2",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY},
    261     {"pmax2",	   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY},
    262     {"psad1",	   I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY},
    263     {"mux1",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY},
    264     {"mux2",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY},
    265     {"pshr2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
    266     {"pshr4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
    267     {"shr",	I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
    268     {"pshr2.u",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
    269     {"pshr4.u",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
    270     {"shr.u",	I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
    271     {"pshr2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
    272     {"pshr4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
    273     {"pshr2.u",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
    274     {"pshr4.u",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
    275     {"pshl2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
    276     {"pshl4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
    277     {"shl",	I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
    278     {"mpy4",    I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 1, 3), {R1, R2, R3}, EMPTY},
    279     {"mpyshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
    280     {"pshl2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
    281     {"pshl4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
    282     {"popcnt",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY},
    283     {"clz",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 3), {R1, R3}, EMPTY},
    284 
    285     {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
    286   };
    287 
    288 #undef I0
    289 #undef I
    290 #undef I2
    291 #undef L
    292 #undef bC
    293 #undef bIh
    294 #undef bTa
    295 #undef bTag13
    296 #undef bTb
    297 #undef bVc
    298 #undef bVe
    299 #undef bWh
    300 #undef bX
    301 #undef bXb
    302 #undef bX2
    303 #undef bX2a
    304 #undef bX2b
    305 #undef bX2c
    306 #undef bX3
    307 #undef bX6
    308 #undef bY
    309 #undef bZa
    310 #undef bZb
    311 #undef mC
    312 #undef mIh
    313 #undef mTa
    314 #undef mTag13
    315 #undef mTb
    316 #undef mVc
    317 #undef mVe
    318 #undef mWh
    319 #undef mX
    320 #undef mXb
    321 #undef mX2
    322 #undef mX2a
    323 #undef mX2b
    324 #undef mX2c
    325 #undef mX3
    326 #undef mX6
    327 #undef mY
    328 #undef mZa
    329 #undef mZb
    330 #undef OpZaZbVeX2aX2b
    331 #undef OpZaZbVeX2aX2bX2c
    332 #undef OpX2X
    333 #undef OpX2XYa
    334 #undef OpX2XYb
    335 #undef OpX2TaTbYaC
    336 #undef OpX3
    337 #undef OpX3X6
    338 #undef OpX3XbIhWh
    339 #undef OpX3XbIhWhTag13
    340 #undef EMPTY
    341