1 /* Instruction building/extraction support for m32r. -*- C -*- 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 4 - the resultant file is machine generated, cgen-ibld.in isn't 5 6 Copyright (C) 1996-2014 Free Software Foundation, Inc. 7 8 This file is part of libopcodes. 9 10 This library is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 23 24 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 25 Keep that in mind. */ 26 27 #include "sysdep.h" 28 #include <stdio.h> 29 #include "ansidecl.h" 30 #include "dis-asm.h" 31 #include "bfd.h" 32 #include "symcat.h" 33 #include "m32r-desc.h" 34 #include "m32r-opc.h" 35 #include "cgen/basic-modes.h" 36 #include "opintl.h" 37 #include "safe-ctype.h" 38 39 #undef min 40 #define min(a,b) ((a) < (b) ? (a) : (b)) 41 #undef max 42 #define max(a,b) ((a) > (b) ? (a) : (b)) 43 44 /* Used by the ifield rtx function. */ 45 #define FLD(f) (fields->f) 46 47 static const char * insert_normal 48 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 49 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 50 static const char * insert_insn_normal 51 (CGEN_CPU_DESC, const CGEN_INSN *, 52 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 53 static int extract_normal 54 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 55 unsigned int, unsigned int, unsigned int, unsigned int, 56 unsigned int, unsigned int, bfd_vma, long *); 57 static int extract_insn_normal 58 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 59 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 60 #if CGEN_INT_INSN_P 61 static void put_insn_int_value 62 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 63 #endif 64 #if ! CGEN_INT_INSN_P 65 static CGEN_INLINE void insert_1 66 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 67 static CGEN_INLINE int fill_cache 68 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 69 static CGEN_INLINE long extract_1 70 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 71 #endif 72 73 /* Operand insertion. */ 75 76 #if ! CGEN_INT_INSN_P 77 78 /* Subroutine of insert_normal. */ 79 80 static CGEN_INLINE void 81 insert_1 (CGEN_CPU_DESC cd, 82 unsigned long value, 83 int start, 84 int length, 85 int word_length, 86 unsigned char *bufp) 87 { 88 unsigned long x,mask; 89 int shift; 90 91 x = cgen_get_insn_value (cd, bufp, word_length); 92 93 /* Written this way to avoid undefined behaviour. */ 94 mask = (((1L << (length - 1)) - 1) << 1) | 1; 95 if (CGEN_INSN_LSB0_P) 96 shift = (start + 1) - length; 97 else 98 shift = (word_length - (start + length)); 99 x = (x & ~(mask << shift)) | ((value & mask) << shift); 100 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); 102 } 103 104 #endif /* ! CGEN_INT_INSN_P */ 105 106 /* Default insertion routine. 107 108 ATTRS is a mask of the boolean attributes. 109 WORD_OFFSET is the offset in bits from the start of the insn of the value. 110 WORD_LENGTH is the length of the word in bits in which the value resides. 111 START is the starting bit number in the word, architecture origin. 112 LENGTH is the length of VALUE in bits. 113 TOTAL_LENGTH is the total length of the insn in bits. 114 115 The result is an error message or NULL if success. */ 116 117 /* ??? This duplicates functionality with bfd's howto table and 118 bfd_install_relocation. */ 119 /* ??? This doesn't handle bfd_vma's. Create another function when 120 necessary. */ 121 122 static const char * 123 insert_normal (CGEN_CPU_DESC cd, 124 long value, 125 unsigned int attrs, 126 unsigned int word_offset, 127 unsigned int start, 128 unsigned int length, 129 unsigned int word_length, 130 unsigned int total_length, 131 CGEN_INSN_BYTES_PTR buffer) 132 { 133 static char errbuf[100]; 134 /* Written this way to avoid undefined behaviour. */ 135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 142 abort (); 143 144 /* For architectures with insns smaller than the base-insn-bitsize, 145 word_length may be too big. */ 146 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 147 { 148 if (word_offset == 0 149 && word_length > total_length) 150 word_length = total_length; 151 } 152 153 /* Ensure VALUE will fit. */ 154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 155 { 156 long minval = - (1L << (length - 1)); 157 unsigned long maxval = mask; 158 159 if ((value > 0 && (unsigned long) value > maxval) 160 || value < minval) 161 { 162 /* xgettext:c-format */ 163 sprintf (errbuf, 164 _("operand out of range (%ld not between %ld and %lu)"), 165 value, minval, maxval); 166 return errbuf; 167 } 168 } 169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 170 { 171 unsigned long maxval = mask; 172 unsigned long val = (unsigned long) value; 173 174 /* For hosts with a word size > 32 check to see if value has been sign 175 extended beyond 32 bits. If so then ignore these higher sign bits 176 as the user is attempting to store a 32-bit signed value into an 177 unsigned 32-bit field which is allowed. */ 178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 179 val &= 0xFFFFFFFF; 180 181 if (val > maxval) 182 { 183 /* xgettext:c-format */ 184 sprintf (errbuf, 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 186 val, maxval); 187 return errbuf; 188 } 189 } 190 else 191 { 192 if (! cgen_signed_overflow_ok_p (cd)) 193 { 194 long minval = - (1L << (length - 1)); 195 long maxval = (1L << (length - 1)) - 1; 196 197 if (value < minval || value > maxval) 198 { 199 sprintf 200 /* xgettext:c-format */ 201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 202 value, minval, maxval); 203 return errbuf; 204 } 205 } 206 } 207 208 #if CGEN_INT_INSN_P 209 210 { 211 int shift; 212 213 if (CGEN_INSN_LSB0_P) 214 shift = (word_offset + start + 1) - length; 215 else 216 shift = total_length - (word_offset + start + length); 217 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 218 } 219 220 #else /* ! CGEN_INT_INSN_P */ 221 222 { 223 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 224 225 insert_1 (cd, value, start, length, word_length, bufp); 226 } 227 228 #endif /* ! CGEN_INT_INSN_P */ 229 230 return NULL; 231 } 232 233 /* Default insn builder (insert handler). 234 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 235 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 236 recorded in host byte order, otherwise BUFFER is an array of bytes 237 and the value is recorded in target byte order). 238 The result is an error message or NULL if success. */ 239 240 static const char * 241 insert_insn_normal (CGEN_CPU_DESC cd, 242 const CGEN_INSN * insn, 243 CGEN_FIELDS * fields, 244 CGEN_INSN_BYTES_PTR buffer, 245 bfd_vma pc) 246 { 247 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 248 unsigned long value; 249 const CGEN_SYNTAX_CHAR_TYPE * syn; 250 251 CGEN_INIT_INSERT (cd); 252 value = CGEN_INSN_BASE_VALUE (insn); 253 254 /* If we're recording insns as numbers (rather than a string of bytes), 255 target byte order handling is deferred until later. */ 256 257 #if CGEN_INT_INSN_P 258 259 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 260 CGEN_FIELDS_BITSIZE (fields), value); 261 262 #else 263 264 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 265 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 266 value); 267 268 #endif /* ! CGEN_INT_INSN_P */ 269 270 /* ??? It would be better to scan the format's fields. 271 Still need to be able to insert a value based on the operand though; 272 e.g. storing a branch displacement that got resolved later. 273 Needs more thought first. */ 274 275 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 276 { 277 const char *errmsg; 278 279 if (CGEN_SYNTAX_CHAR_P (* syn)) 280 continue; 281 282 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 283 fields, buffer, pc); 284 if (errmsg) 285 return errmsg; 286 } 287 288 return NULL; 289 } 290 291 #if CGEN_INT_INSN_P 292 /* Cover function to store an insn value into an integral insn. Must go here 293 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 294 295 static void 296 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 297 CGEN_INSN_BYTES_PTR buf, 298 int length, 299 int insn_length, 300 CGEN_INSN_INT value) 301 { 302 /* For architectures with insns smaller than the base-insn-bitsize, 303 length may be too big. */ 304 if (length > insn_length) 305 *buf = value; 306 else 307 { 308 int shift = insn_length - length; 309 /* Written this way to avoid undefined behaviour. */ 310 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; 311 312 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 313 } 314 } 315 #endif 316 317 /* Operand extraction. */ 319 320 #if ! CGEN_INT_INSN_P 321 322 /* Subroutine of extract_normal. 323 Ensure sufficient bytes are cached in EX_INFO. 324 OFFSET is the offset in bytes from the start of the insn of the value. 325 BYTES is the length of the needed value. 326 Returns 1 for success, 0 for failure. */ 327 328 static CGEN_INLINE int 329 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 330 CGEN_EXTRACT_INFO *ex_info, 331 int offset, 332 int bytes, 333 bfd_vma pc) 334 { 335 /* It's doubtful that the middle part has already been fetched so 336 we don't optimize that case. kiss. */ 337 unsigned int mask; 338 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 339 340 /* First do a quick check. */ 341 mask = (1 << bytes) - 1; 342 if (((ex_info->valid >> offset) & mask) == mask) 343 return 1; 344 345 /* Search for the first byte we need to read. */ 346 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 347 if (! (mask & ex_info->valid)) 348 break; 349 350 if (bytes) 351 { 352 int status; 353 354 pc += offset; 355 status = (*info->read_memory_func) 356 (pc, ex_info->insn_bytes + offset, bytes, info); 357 358 if (status != 0) 359 { 360 (*info->memory_error_func) (status, pc, info); 361 return 0; 362 } 363 364 ex_info->valid |= ((1 << bytes) - 1) << offset; 365 } 366 367 return 1; 368 } 369 370 /* Subroutine of extract_normal. */ 371 372 static CGEN_INLINE long 373 extract_1 (CGEN_CPU_DESC cd, 374 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 375 int start, 376 int length, 377 int word_length, 378 unsigned char *bufp, 379 bfd_vma pc ATTRIBUTE_UNUSED) 380 { 381 unsigned long x; 382 int shift; 383 384 x = cgen_get_insn_value (cd, bufp, word_length); 385 386 if (CGEN_INSN_LSB0_P) 387 shift = (start + 1) - length; 388 else 389 shift = (word_length - (start + length)); 390 return x >> shift; 391 } 392 393 #endif /* ! CGEN_INT_INSN_P */ 394 395 /* Default extraction routine. 396 397 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 398 or sometimes less for cases like the m32r where the base insn size is 32 399 but some insns are 16 bits. 400 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 401 but for generality we take a bitmask of all of them. 402 WORD_OFFSET is the offset in bits from the start of the insn of the value. 403 WORD_LENGTH is the length of the word in bits in which the value resides. 404 START is the starting bit number in the word, architecture origin. 405 LENGTH is the length of VALUE in bits. 406 TOTAL_LENGTH is the total length of the insn in bits. 407 408 Returns 1 for success, 0 for failure. */ 409 410 /* ??? The return code isn't properly used. wip. */ 411 412 /* ??? This doesn't handle bfd_vma's. Create another function when 413 necessary. */ 414 415 static int 416 extract_normal (CGEN_CPU_DESC cd, 417 #if ! CGEN_INT_INSN_P 418 CGEN_EXTRACT_INFO *ex_info, 419 #else 420 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 421 #endif 422 CGEN_INSN_INT insn_value, 423 unsigned int attrs, 424 unsigned int word_offset, 425 unsigned int start, 426 unsigned int length, 427 unsigned int word_length, 428 unsigned int total_length, 429 #if ! CGEN_INT_INSN_P 430 bfd_vma pc, 431 #else 432 bfd_vma pc ATTRIBUTE_UNUSED, 433 #endif 434 long *valuep) 435 { 436 long value, mask; 437 438 /* If LENGTH is zero, this operand doesn't contribute to the value 439 so give it a standard value of zero. */ 440 if (length == 0) 441 { 442 *valuep = 0; 443 return 1; 444 } 445 446 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 447 abort (); 448 449 /* For architectures with insns smaller than the insn-base-bitsize, 450 word_length may be too big. */ 451 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 452 { 453 if (word_offset + word_length > total_length) 454 word_length = total_length - word_offset; 455 } 456 457 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 458 459 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 460 { 461 if (CGEN_INSN_LSB0_P) 462 value = insn_value >> ((word_offset + start + 1) - length); 463 else 464 value = insn_value >> (total_length - ( word_offset + start + length)); 465 } 466 467 #if ! CGEN_INT_INSN_P 468 469 else 470 { 471 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 472 473 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 474 abort (); 475 476 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 477 return 0; 478 479 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 480 } 481 482 #endif /* ! CGEN_INT_INSN_P */ 483 484 /* Written this way to avoid undefined behaviour. */ 485 mask = (((1L << (length - 1)) - 1) << 1) | 1; 486 487 value &= mask; 488 /* sign extend? */ 489 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 490 && (value & (1L << (length - 1)))) 491 value |= ~mask; 492 493 *valuep = value; 494 495 return 1; 496 } 497 498 /* Default insn extractor. 499 500 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 501 The extracted fields are stored in FIELDS. 502 EX_INFO is used to handle reading variable length insns. 503 Return the length of the insn in bits, or 0 if no match, 504 or -1 if an error occurs fetching data (memory_error_func will have 505 been called). */ 506 507 static int 508 extract_insn_normal (CGEN_CPU_DESC cd, 509 const CGEN_INSN *insn, 510 CGEN_EXTRACT_INFO *ex_info, 511 CGEN_INSN_INT insn_value, 512 CGEN_FIELDS *fields, 513 bfd_vma pc) 514 { 515 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 516 const CGEN_SYNTAX_CHAR_TYPE *syn; 517 518 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 519 520 CGEN_INIT_EXTRACT (cd); 521 522 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 523 { 524 int length; 525 526 if (CGEN_SYNTAX_CHAR_P (*syn)) 527 continue; 528 529 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 530 ex_info, insn_value, fields, pc); 531 if (length <= 0) 532 return length; 533 } 534 535 /* We recognized and successfully extracted this insn. */ 536 return CGEN_INSN_BITSIZE (insn); 537 } 538 539 /* Machine generated code added here. */ 541 542 const char * m32r_cgen_insert_operand 543 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 544 545 /* Main entry point for operand insertion. 546 547 This function is basically just a big switch statement. Earlier versions 548 used tables to look up the function to use, but 549 - if the table contains both assembler and disassembler functions then 550 the disassembler contains much of the assembler and vice-versa, 551 - there's a lot of inlining possibilities as things grow, 552 - using a switch statement avoids the function call overhead. 553 554 This function could be moved into `parse_insn_normal', but keeping it 555 separate makes clear the interface between `parse_insn_normal' and each of 556 the handlers. It's also needed by GAS to insert operands that couldn't be 557 resolved during parsing. */ 558 559 const char * 560 m32r_cgen_insert_operand (CGEN_CPU_DESC cd, 561 int opindex, 562 CGEN_FIELDS * fields, 563 CGEN_INSN_BYTES_PTR buffer, 564 bfd_vma pc ATTRIBUTE_UNUSED) 565 { 566 const char * errmsg = NULL; 567 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 568 569 switch (opindex) 570 { 571 case M32R_OPERAND_ACC : 572 errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer); 573 break; 574 case M32R_OPERAND_ACCD : 575 errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer); 576 break; 577 case M32R_OPERAND_ACCS : 578 errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer); 579 break; 580 case M32R_OPERAND_DCR : 581 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 582 break; 583 case M32R_OPERAND_DISP16 : 584 { 585 long value = fields->f_disp16; 586 value = ((SI) (((value) - (pc))) >> (2)); 587 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer); 588 } 589 break; 590 case M32R_OPERAND_DISP24 : 591 { 592 long value = fields->f_disp24; 593 value = ((SI) (((value) - (pc))) >> (2)); 594 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer); 595 } 596 break; 597 case M32R_OPERAND_DISP8 : 598 { 599 long value = fields->f_disp8; 600 value = ((SI) (((value) - (((pc) & (-4))))) >> (2)); 601 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer); 602 } 603 break; 604 case M32R_OPERAND_DR : 605 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 606 break; 607 case M32R_OPERAND_HASH : 608 break; 609 case M32R_OPERAND_HI16 : 610 errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer); 611 break; 612 case M32R_OPERAND_IMM1 : 613 { 614 long value = fields->f_imm1; 615 value = ((value) - (1)); 616 errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer); 617 } 618 break; 619 case M32R_OPERAND_SCR : 620 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 621 break; 622 case M32R_OPERAND_SIMM16 : 623 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); 624 break; 625 case M32R_OPERAND_SIMM8 : 626 errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer); 627 break; 628 case M32R_OPERAND_SLO16 : 629 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); 630 break; 631 case M32R_OPERAND_SR : 632 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 633 break; 634 case M32R_OPERAND_SRC1 : 635 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 636 break; 637 case M32R_OPERAND_SRC2 : 638 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 639 break; 640 case M32R_OPERAND_UIMM16 : 641 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); 642 break; 643 case M32R_OPERAND_UIMM24 : 644 errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer); 645 break; 646 case M32R_OPERAND_UIMM3 : 647 errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer); 648 break; 649 case M32R_OPERAND_UIMM4 : 650 errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer); 651 break; 652 case M32R_OPERAND_UIMM5 : 653 errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer); 654 break; 655 case M32R_OPERAND_UIMM8 : 656 errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer); 657 break; 658 case M32R_OPERAND_ULO16 : 659 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); 660 break; 661 662 default : 663 /* xgettext:c-format */ 664 fprintf (stderr, _("Unrecognized field %d while building insn.\n"), 665 opindex); 666 abort (); 667 } 668 669 return errmsg; 670 } 671 672 int m32r_cgen_extract_operand 673 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 674 675 /* Main entry point for operand extraction. 676 The result is <= 0 for error, >0 for success. 677 ??? Actual values aren't well defined right now. 678 679 This function is basically just a big switch statement. Earlier versions 680 used tables to look up the function to use, but 681 - if the table contains both assembler and disassembler functions then 682 the disassembler contains much of the assembler and vice-versa, 683 - there's a lot of inlining possibilities as things grow, 684 - using a switch statement avoids the function call overhead. 685 686 This function could be moved into `print_insn_normal', but keeping it 687 separate makes clear the interface between `print_insn_normal' and each of 688 the handlers. */ 689 690 int 691 m32r_cgen_extract_operand (CGEN_CPU_DESC cd, 692 int opindex, 693 CGEN_EXTRACT_INFO *ex_info, 694 CGEN_INSN_INT insn_value, 695 CGEN_FIELDS * fields, 696 bfd_vma pc) 697 { 698 /* Assume success (for those operands that are nops). */ 699 int length = 1; 700 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 701 702 switch (opindex) 703 { 704 case M32R_OPERAND_ACC : 705 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc); 706 break; 707 case M32R_OPERAND_ACCD : 708 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd); 709 break; 710 case M32R_OPERAND_ACCS : 711 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs); 712 break; 713 case M32R_OPERAND_DCR : 714 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 715 break; 716 case M32R_OPERAND_DISP16 : 717 { 718 long value; 719 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value); 720 value = ((((value) << (2))) + (pc)); 721 fields->f_disp16 = value; 722 } 723 break; 724 case M32R_OPERAND_DISP24 : 725 { 726 long value; 727 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value); 728 value = ((((value) << (2))) + (pc)); 729 fields->f_disp24 = value; 730 } 731 break; 732 case M32R_OPERAND_DISP8 : 733 { 734 long value; 735 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value); 736 value = ((((value) << (2))) + (((pc) & (-4)))); 737 fields->f_disp8 = value; 738 } 739 break; 740 case M32R_OPERAND_DR : 741 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 742 break; 743 case M32R_OPERAND_HASH : 744 break; 745 case M32R_OPERAND_HI16 : 746 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16); 747 break; 748 case M32R_OPERAND_IMM1 : 749 { 750 long value; 751 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value); 752 value = ((value) + (1)); 753 fields->f_imm1 = value; 754 } 755 break; 756 case M32R_OPERAND_SCR : 757 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 758 break; 759 case M32R_OPERAND_SIMM16 : 760 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16); 761 break; 762 case M32R_OPERAND_SIMM8 : 763 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8); 764 break; 765 case M32R_OPERAND_SLO16 : 766 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16); 767 break; 768 case M32R_OPERAND_SR : 769 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 770 break; 771 case M32R_OPERAND_SRC1 : 772 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 773 break; 774 case M32R_OPERAND_SRC2 : 775 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 776 break; 777 case M32R_OPERAND_UIMM16 : 778 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); 779 break; 780 case M32R_OPERAND_UIMM24 : 781 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24); 782 break; 783 case M32R_OPERAND_UIMM3 : 784 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3); 785 break; 786 case M32R_OPERAND_UIMM4 : 787 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4); 788 break; 789 case M32R_OPERAND_UIMM5 : 790 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5); 791 break; 792 case M32R_OPERAND_UIMM8 : 793 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8); 794 break; 795 case M32R_OPERAND_ULO16 : 796 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); 797 break; 798 799 default : 800 /* xgettext:c-format */ 801 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), 802 opindex); 803 abort (); 804 } 805 806 return length; 807 } 808 809 cgen_insert_fn * const m32r_cgen_insert_handlers[] = 810 { 811 insert_insn_normal, 812 }; 813 814 cgen_extract_fn * const m32r_cgen_extract_handlers[] = 815 { 816 extract_insn_normal, 817 }; 818 819 int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 820 bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 821 822 /* Getting values from cgen_fields is handled by a collection of functions. 823 They are distinguished by the type of the VALUE argument they return. 824 TODO: floating point, inlining support, remove cases where result type 825 not appropriate. */ 826 827 int 828 m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 829 int opindex, 830 const CGEN_FIELDS * fields) 831 { 832 int value; 833 834 switch (opindex) 835 { 836 case M32R_OPERAND_ACC : 837 value = fields->f_acc; 838 break; 839 case M32R_OPERAND_ACCD : 840 value = fields->f_accd; 841 break; 842 case M32R_OPERAND_ACCS : 843 value = fields->f_accs; 844 break; 845 case M32R_OPERAND_DCR : 846 value = fields->f_r1; 847 break; 848 case M32R_OPERAND_DISP16 : 849 value = fields->f_disp16; 850 break; 851 case M32R_OPERAND_DISP24 : 852 value = fields->f_disp24; 853 break; 854 case M32R_OPERAND_DISP8 : 855 value = fields->f_disp8; 856 break; 857 case M32R_OPERAND_DR : 858 value = fields->f_r1; 859 break; 860 case M32R_OPERAND_HASH : 861 value = 0; 862 break; 863 case M32R_OPERAND_HI16 : 864 value = fields->f_hi16; 865 break; 866 case M32R_OPERAND_IMM1 : 867 value = fields->f_imm1; 868 break; 869 case M32R_OPERAND_SCR : 870 value = fields->f_r2; 871 break; 872 case M32R_OPERAND_SIMM16 : 873 value = fields->f_simm16; 874 break; 875 case M32R_OPERAND_SIMM8 : 876 value = fields->f_simm8; 877 break; 878 case M32R_OPERAND_SLO16 : 879 value = fields->f_simm16; 880 break; 881 case M32R_OPERAND_SR : 882 value = fields->f_r2; 883 break; 884 case M32R_OPERAND_SRC1 : 885 value = fields->f_r1; 886 break; 887 case M32R_OPERAND_SRC2 : 888 value = fields->f_r2; 889 break; 890 case M32R_OPERAND_UIMM16 : 891 value = fields->f_uimm16; 892 break; 893 case M32R_OPERAND_UIMM24 : 894 value = fields->f_uimm24; 895 break; 896 case M32R_OPERAND_UIMM3 : 897 value = fields->f_uimm3; 898 break; 899 case M32R_OPERAND_UIMM4 : 900 value = fields->f_uimm4; 901 break; 902 case M32R_OPERAND_UIMM5 : 903 value = fields->f_uimm5; 904 break; 905 case M32R_OPERAND_UIMM8 : 906 value = fields->f_uimm8; 907 break; 908 case M32R_OPERAND_ULO16 : 909 value = fields->f_uimm16; 910 break; 911 912 default : 913 /* xgettext:c-format */ 914 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), 915 opindex); 916 abort (); 917 } 918 919 return value; 920 } 921 922 bfd_vma 923 m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 924 int opindex, 925 const CGEN_FIELDS * fields) 926 { 927 bfd_vma value; 928 929 switch (opindex) 930 { 931 case M32R_OPERAND_ACC : 932 value = fields->f_acc; 933 break; 934 case M32R_OPERAND_ACCD : 935 value = fields->f_accd; 936 break; 937 case M32R_OPERAND_ACCS : 938 value = fields->f_accs; 939 break; 940 case M32R_OPERAND_DCR : 941 value = fields->f_r1; 942 break; 943 case M32R_OPERAND_DISP16 : 944 value = fields->f_disp16; 945 break; 946 case M32R_OPERAND_DISP24 : 947 value = fields->f_disp24; 948 break; 949 case M32R_OPERAND_DISP8 : 950 value = fields->f_disp8; 951 break; 952 case M32R_OPERAND_DR : 953 value = fields->f_r1; 954 break; 955 case M32R_OPERAND_HASH : 956 value = 0; 957 break; 958 case M32R_OPERAND_HI16 : 959 value = fields->f_hi16; 960 break; 961 case M32R_OPERAND_IMM1 : 962 value = fields->f_imm1; 963 break; 964 case M32R_OPERAND_SCR : 965 value = fields->f_r2; 966 break; 967 case M32R_OPERAND_SIMM16 : 968 value = fields->f_simm16; 969 break; 970 case M32R_OPERAND_SIMM8 : 971 value = fields->f_simm8; 972 break; 973 case M32R_OPERAND_SLO16 : 974 value = fields->f_simm16; 975 break; 976 case M32R_OPERAND_SR : 977 value = fields->f_r2; 978 break; 979 case M32R_OPERAND_SRC1 : 980 value = fields->f_r1; 981 break; 982 case M32R_OPERAND_SRC2 : 983 value = fields->f_r2; 984 break; 985 case M32R_OPERAND_UIMM16 : 986 value = fields->f_uimm16; 987 break; 988 case M32R_OPERAND_UIMM24 : 989 value = fields->f_uimm24; 990 break; 991 case M32R_OPERAND_UIMM3 : 992 value = fields->f_uimm3; 993 break; 994 case M32R_OPERAND_UIMM4 : 995 value = fields->f_uimm4; 996 break; 997 case M32R_OPERAND_UIMM5 : 998 value = fields->f_uimm5; 999 break; 1000 case M32R_OPERAND_UIMM8 : 1001 value = fields->f_uimm8; 1002 break; 1003 case M32R_OPERAND_ULO16 : 1004 value = fields->f_uimm16; 1005 break; 1006 1007 default : 1008 /* xgettext:c-format */ 1009 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), 1010 opindex); 1011 abort (); 1012 } 1013 1014 return value; 1015 } 1016 1017 void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1018 void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1019 1020 /* Stuffing values in cgen_fields is handled by a collection of functions. 1021 They are distinguished by the type of the VALUE argument they accept. 1022 TODO: floating point, inlining support, remove cases where argument type 1023 not appropriate. */ 1024 1025 void 1026 m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1027 int opindex, 1028 CGEN_FIELDS * fields, 1029 int value) 1030 { 1031 switch (opindex) 1032 { 1033 case M32R_OPERAND_ACC : 1034 fields->f_acc = value; 1035 break; 1036 case M32R_OPERAND_ACCD : 1037 fields->f_accd = value; 1038 break; 1039 case M32R_OPERAND_ACCS : 1040 fields->f_accs = value; 1041 break; 1042 case M32R_OPERAND_DCR : 1043 fields->f_r1 = value; 1044 break; 1045 case M32R_OPERAND_DISP16 : 1046 fields->f_disp16 = value; 1047 break; 1048 case M32R_OPERAND_DISP24 : 1049 fields->f_disp24 = value; 1050 break; 1051 case M32R_OPERAND_DISP8 : 1052 fields->f_disp8 = value; 1053 break; 1054 case M32R_OPERAND_DR : 1055 fields->f_r1 = value; 1056 break; 1057 case M32R_OPERAND_HASH : 1058 break; 1059 case M32R_OPERAND_HI16 : 1060 fields->f_hi16 = value; 1061 break; 1062 case M32R_OPERAND_IMM1 : 1063 fields->f_imm1 = value; 1064 break; 1065 case M32R_OPERAND_SCR : 1066 fields->f_r2 = value; 1067 break; 1068 case M32R_OPERAND_SIMM16 : 1069 fields->f_simm16 = value; 1070 break; 1071 case M32R_OPERAND_SIMM8 : 1072 fields->f_simm8 = value; 1073 break; 1074 case M32R_OPERAND_SLO16 : 1075 fields->f_simm16 = value; 1076 break; 1077 case M32R_OPERAND_SR : 1078 fields->f_r2 = value; 1079 break; 1080 case M32R_OPERAND_SRC1 : 1081 fields->f_r1 = value; 1082 break; 1083 case M32R_OPERAND_SRC2 : 1084 fields->f_r2 = value; 1085 break; 1086 case M32R_OPERAND_UIMM16 : 1087 fields->f_uimm16 = value; 1088 break; 1089 case M32R_OPERAND_UIMM24 : 1090 fields->f_uimm24 = value; 1091 break; 1092 case M32R_OPERAND_UIMM3 : 1093 fields->f_uimm3 = value; 1094 break; 1095 case M32R_OPERAND_UIMM4 : 1096 fields->f_uimm4 = value; 1097 break; 1098 case M32R_OPERAND_UIMM5 : 1099 fields->f_uimm5 = value; 1100 break; 1101 case M32R_OPERAND_UIMM8 : 1102 fields->f_uimm8 = value; 1103 break; 1104 case M32R_OPERAND_ULO16 : 1105 fields->f_uimm16 = value; 1106 break; 1107 1108 default : 1109 /* xgettext:c-format */ 1110 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), 1111 opindex); 1112 abort (); 1113 } 1114 } 1115 1116 void 1117 m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1118 int opindex, 1119 CGEN_FIELDS * fields, 1120 bfd_vma value) 1121 { 1122 switch (opindex) 1123 { 1124 case M32R_OPERAND_ACC : 1125 fields->f_acc = value; 1126 break; 1127 case M32R_OPERAND_ACCD : 1128 fields->f_accd = value; 1129 break; 1130 case M32R_OPERAND_ACCS : 1131 fields->f_accs = value; 1132 break; 1133 case M32R_OPERAND_DCR : 1134 fields->f_r1 = value; 1135 break; 1136 case M32R_OPERAND_DISP16 : 1137 fields->f_disp16 = value; 1138 break; 1139 case M32R_OPERAND_DISP24 : 1140 fields->f_disp24 = value; 1141 break; 1142 case M32R_OPERAND_DISP8 : 1143 fields->f_disp8 = value; 1144 break; 1145 case M32R_OPERAND_DR : 1146 fields->f_r1 = value; 1147 break; 1148 case M32R_OPERAND_HASH : 1149 break; 1150 case M32R_OPERAND_HI16 : 1151 fields->f_hi16 = value; 1152 break; 1153 case M32R_OPERAND_IMM1 : 1154 fields->f_imm1 = value; 1155 break; 1156 case M32R_OPERAND_SCR : 1157 fields->f_r2 = value; 1158 break; 1159 case M32R_OPERAND_SIMM16 : 1160 fields->f_simm16 = value; 1161 break; 1162 case M32R_OPERAND_SIMM8 : 1163 fields->f_simm8 = value; 1164 break; 1165 case M32R_OPERAND_SLO16 : 1166 fields->f_simm16 = value; 1167 break; 1168 case M32R_OPERAND_SR : 1169 fields->f_r2 = value; 1170 break; 1171 case M32R_OPERAND_SRC1 : 1172 fields->f_r1 = value; 1173 break; 1174 case M32R_OPERAND_SRC2 : 1175 fields->f_r2 = value; 1176 break; 1177 case M32R_OPERAND_UIMM16 : 1178 fields->f_uimm16 = value; 1179 break; 1180 case M32R_OPERAND_UIMM24 : 1181 fields->f_uimm24 = value; 1182 break; 1183 case M32R_OPERAND_UIMM3 : 1184 fields->f_uimm3 = value; 1185 break; 1186 case M32R_OPERAND_UIMM4 : 1187 fields->f_uimm4 = value; 1188 break; 1189 case M32R_OPERAND_UIMM5 : 1190 fields->f_uimm5 = value; 1191 break; 1192 case M32R_OPERAND_UIMM8 : 1193 fields->f_uimm8 = value; 1194 break; 1195 case M32R_OPERAND_ULO16 : 1196 fields->f_uimm16 = value; 1197 break; 1198 1199 default : 1200 /* xgettext:c-format */ 1201 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), 1202 opindex); 1203 abort (); 1204 } 1205 } 1206 1207 /* Function to call before using the instruction builder tables. */ 1208 1209 void 1210 m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1211 { 1212 cd->insert_handlers = & m32r_cgen_insert_handlers[0]; 1213 cd->extract_handlers = & m32r_cgen_extract_handlers[0]; 1214 1215 cd->insert_operand = m32r_cgen_insert_operand; 1216 cd->extract_operand = m32r_cgen_extract_operand; 1217 1218 cd->get_int_operand = m32r_cgen_get_int_operand; 1219 cd->set_int_operand = m32r_cgen_set_int_operand; 1220 cd->get_vma_operand = m32r_cgen_get_vma_operand; 1221 cd->set_vma_operand = m32r_cgen_set_vma_operand; 1222 } 1223
