Lines Matching defs:Add
420 // add/sub are legal for all supported vector VT's.
421 setOperationAction(ISD::ADD, VT, Legal);
633 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1765 if (N.getOpcode() == ISD::ADD) {
1778 // If this is an or of disjoint bitfields, we can codegen this as an add
1789 // If all of the bits are known zero on the LHS or RHS, the add won't
1856 if (N.getOpcode() == ISD::ADD) {
1869 // Match LOAD (ADD (X, Lo(G))).
1884 // If this is an or of disjoint bitfields, we can codegen this as an add
1891 // If all of the bits are known zero on the LHS or RHS, the add won't
1955 // better (for code size, and execution, as the memop does the add for free)
1956 add.
1957 if (N.getOpcode() == ISD::ADD) {
2097 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2102 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2425 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2433 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2442 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2445 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2470 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2475 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2479 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2493 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2627 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2636 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2644 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3069 // Get an existing live-in vreg, or add a new one.
3080 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3088 // Get an existing live-in vreg, or add a new one.
3100 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3130 // TODO: add description of PPC stack frame format, or at least some docs.
3188 // Add DAG nodes to load the arguments or copy them out of registers. On
3275 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3321 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3534 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3548 // TODO: add description of PPC stack frame format, or at least some docs.
3636 // Add DAG nodes to load the arguments or copy them out of registers. On
3896 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4289 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4458 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4464 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4500 // Add use of X11 (holding environment pointer)
4503 // Add CTR register as callee so a bctr can be emitted later.
4513 // If this is a tail call add stack pointer delta.
4517 // Add argument registers to the end of the list so that they are known live
4599 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4610 // Add a register mask operand representing the call-preserved registers.
4633 // Add a NOP immediately after the branch instruction when using the 64-bit
4660 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4882 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4920 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5051 // Add up all the space actually used.
5187 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5244 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5283 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5305 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5424 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5483 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5541 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5590 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5652 // Add up all the space actually used.
5764 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5793 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5813 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5866 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5909 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5925 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
6081 // Add the flag if we have it.
6425 // add in a bias on big endian.
6427 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6519 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6620 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6688 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6704 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6901 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6944 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6973 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
7001 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
7148 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7901 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7935 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7997 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8023 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
8088 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8108 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
8143 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
8156 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
8195 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
8365 // Add the two halves of the long double in round-to-zero mode.
8480 // add r0, dest, incr
8562 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8571 // add tmp, tmpDest, incr2
8898 // will confuse it with a regular operand. Instead, add the dependence
8983 // Next, add the true and fallthrough blocks as its successors.
9279 // add ptr1, ptrA, ptrB [copy if ptrA==0]
10479 // Add a bitcast if the resulting load type doesn't match v2f64.
10727 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
10736 DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
10865 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10915 N->getOperand(1)->getOpcode() == ISD::ADD) {
10916 SDValue Add = N->getOperand(1);
10922 Add->getOperand(1),
10925 Add.getValueType().getScalarType().getSizeInBits()))) {
10926 SDNode *BasePtr = Add->getOperand(0).getNode();
10941 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10942 SDNode *BasePtr = Add->getOperand(0).getNode();
10945 if (UI->getOpcode() == ISD::ADD &&
10947 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
11478 /// vector. If it is invalid, don't add anything to Ops.
11617 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11957 // FIXME: Add other cases...
