Lines Matching refs:Op
1124 static bool isFloatingPointZero(SDValue Op) {
1125 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1127 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1129 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1136 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1137 /// true if Op is undef or if it matches the specified value.
1138 static bool isConstantOrUndef(int Op, int Val) {
1139 return Op < 0 || Op == Val;
1754 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1755 return isIntS16Immediate(Op.getNode(), Imm);
2127 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2129 EVT PtrVT = Op.getValueType();
2130 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2158 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2159 EVT PtrVT = Op.getValueType();
2160 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2185 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2187 EVT PtrVT = Op.getValueType();
2188 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2207 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2214 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2297 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2299 EVT PtrVT = Op.getValueType();
2300 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2338 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2339 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2340 SDLoc dl(Op);
2342 if (Op.getValueType() == MVT::v2i64) {
2345 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2351 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2352 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2360 return Op;
2366 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2368 EVT VT = Op.getOperand(0).getValueType();
2369 SDValue Zext = Op.getOperand(0);
2372 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2392 EVT LHSVT = Op.getOperand(0).getValueType();
2394 EVT VT = Op.getValueType();
2395 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2396 Op.getOperand(1));
2402 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2403 SDNode *Node = Op.getNode();
2509 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
2514 return DAG.getMemcpy(Op.getOperand(0), Op,
2515 Op.getOperand(1), Op.getOperand(2),
2516 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2520 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2522 return Op.getOperand(0);
2525 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2527 SDValue Chain = Op.getOperand(0);
2528 SDValue Trmp = Op.getOperand(1); // trampoline
2529 SDValue FPtr = Op.getOperand(2); // nested function
2530 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2531 SDLoc dl(Op);
2562 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2567 SDLoc dl(Op);
2573 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2574 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2619 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2622 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2623 Op.getOperand(1),
2627 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
4134 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4135 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4145 (int)C->getZExtValue() >> 2, SDLoc(Op),
6089 PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op,
6091 SDLoc dl(Op);
6094 EVT IntVT = Op.getValueType();
6097 SDValue Chain = Op.getOperand(0);
6105 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op,
6108 SDLoc dl(Op);
6119 SDValue Chain = Op.getOperand(0);
6120 SDValue SaveSP = Op.getOperand(1);
6180 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6183 SDValue Chain = Op.getOperand(0);
6184 SDValue Size = Op.getOperand(1);
6185 SDLoc dl(Op);
6200 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
6202 SDLoc DL(Op);
6205 Op.getOperand(0), Op.getOperand(1));
6208 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
6210 SDLoc DL(Op);
6212 Op.getOperand(0), Op.getOperand(1));
6215 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
6216 if (Op.getValueType().isVector())
6217 return LowerVectorLoad(Op, DAG);
6219 assert(Op.getValueType() == MVT::i1 &&
6224 SDLoc dl(Op);
6225 LoadSDNode *LD = cast<LoadSDNode>(Op);
6240 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
6241 if (Op.getOperand(1).getValueType().isVector())
6242 return LowerVectorStore(Op, DAG);
6244 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
6249 SDLoc dl(Op);
6250 StoreSDNode *ST = cast<StoreSDNode>(Op);
6263 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
6264 assert(Op.getValueType() == MVT::i1 &&
6267 SDLoc DL(Op);
6269 Op.getOperand(0));
6274 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
6276 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
6277 !Op.getOperand(2).getValueType().isFloatingPoint())
6278 return Op;
6285 return Op;
6291 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6293 EVT ResVT = Op.getValueType();
6294 EVT CmpVT = Op.getOperand(0).getValueType();
6295 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6296 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6297 SDLoc dl(Op);
6373 return Op;
6376 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6379 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6380 SDValue Src = Op.getOperand(0);
6385 switch (Op.getSimpleValueType().SimpleTy) {
6389 Op.getOpcode() == ISD::FP_TO_SINT
6395 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6397 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6404 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6405 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6426 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6440 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6443 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6444 SDValue Src = Op.getOperand(0);
6450 switch (Op.getSimpleValueType().SimpleTy) {
6454 Op.getOpcode() == ISD::FP_TO_SINT
6461 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6463 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6472 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6475 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6478 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6480 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6493 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6497 SDLoc dl(Op);
6499 (Op.getOpcode() == ISD::FP_TO_UINT ||
6500 Op.getOpcode() == ISD::FP_TO_SINT) &&
6501 isOperationLegalOrCustom(Op.getOpcode(),
6502 Op.getOperand(0).getValueType())) {
6504 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6508 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6557 static bool directMoveIsProfitable(const SDValue &Op) {
6558 SDNode *Origin = Op.getOperand(0).getNode();
6581 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6584 assert((Op.getValueType() == MVT::f32 ||
6585 Op.getValueType() == MVT::f64) &&
6590 SDValue Src = Op.getOperand(0);
6591 bool SinglePrec = Op.getValueType() == MVT::f32;
6593 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6610 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6612 SDLoc dl(Op);
6614 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6615 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6618 SDValue Value = Op.getOperand(0);
6628 if (Op.getValueType() != MVT::v4f64)
6630 Op.getValueType(), Value,
6636 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6639 if (Op.getOperand(0).getValueType() == MVT::i1)
6640 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6641 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6642 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6646 if (Subtarget.hasDirectMove() && directMoveIsProfitable(Op) &&
6648 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6650 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6655 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6656 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6658 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6660 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6664 if (Op.getOperand(0).getValueType() == MVT::i64) {
6665 SDValue SINT = Op.getOperand(0);
6676 if (Op.getValueType() == MVT::f32 &&
6779 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6785 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6799 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6805 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6823 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6837 Op.getOperand(0));
6854 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6860 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6862 SDLoc dl(Op);
6883 EVT VT = Op.getValueType();
6924 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6925 EVT VT = Op.getValueType();
6927 SDLoc dl(Op);
6928 assert(Op.getNumOperands() == 3 &&
6929 VT == Op.getOperand(1).getValueType() &&
6934 SDValue Lo = Op.getOperand(0);
6935 SDValue Hi = Op.getOperand(1);
6936 SDValue Amt = Op.getOperand(2);
6953 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6954 EVT VT = Op.getValueType();
6955 SDLoc dl(Op);
6957 assert(Op.getNumOperands() == 3 &&
6958 VT == Op.getOperand(1).getValueType() &&
6963 SDValue Lo = Op.getOperand(0);
6964 SDValue Hi = Op.getOperand(1);
6965 SDValue Amt = Op.getOperand(2);
6982 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6983 SDLoc dl(Op);
6984 EVT VT = Op.getValueType();
6986 assert(Op.getNumOperands() == 3 &&
6987 VT == Op.getOperand(1).getValueType() &&
6991 SDValue Lo = Op.getOperand(0);
6992 SDValue Hi = Op.getOperand(1);
6993 SDValue Amt = Op.getOperand(2);
7039 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG,
7041 if (DestVT == MVT::Other) DestVT = Op.getValueType();
7043 DAG.getConstant(IID, dl, MVT::i32), Op);
7083 // selects to a single instruction, return Op. Otherwise, if we can codegen
7086 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
7088 SDLoc dl(Op);
7089 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7092 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
7217 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
7219 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
7221 return Op;
7228 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
7248 if (VT == Op.getValueType())
7251 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
7267 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7293 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7304 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7315 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7327 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7334 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7340 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7346 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7434 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7436 SDLoc dl(Op);
7437 SDValue V1 = Op.getOperand(0);
7438 SDValue V2 = Op.getOperand(1);
7439 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7440 EVT VT = Op.getValueType();
7538 return Op;
7559 return Op;
7769 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7772 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7783 SDLoc dl(Op);
7786 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
7791 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7792 Op.getOperand(1), Op.getOperand(2),
7794 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7799 Op.getOperand(2), // LHS
7800 Op.getOperand(3), // RHS
7803 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7815 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7845 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7847 SDLoc dl(Op);
7851 if (Op.getValueType() == MVT::v2i64) {
7852 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7854 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7855 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7858 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7859 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7863 return Op;
7869 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7871 SDLoc dl(Op);
7880 Op.getOperand(0), FIdx, MachinePointerInfo(),
7883 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7887 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7889 SDLoc dl(Op);
7890 SDNode *N = Op.getNode();
7948 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7950 SDLoc dl(Op);
7951 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7955 if (Op.getValueType() == MVT::v4f64 ||
7956 Op.getValueType() == MVT::v4f32) {
7962 return Op;
7964 EVT ScalarVT = Op.getValueType().getScalarType(),
8003 SDValue Value = DAG.getBuildVector(Op.getValueType(), dl, Vals);
8014 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
8041 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
8043 SDLoc dl(Op);
8044 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
8056 return Op;
8169 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
8170 SDLoc dl(Op);
8171 if (Op.getValueType() == MVT::v4i32) {
8172 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
8196 } else if (Op.getValueType() == MVT::v8i16) {
8197 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
8203 } else if (Op.getValueType() == MVT::v16i8) {
8204 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
8242 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8243 switch (Op.getOpcode()) {
8245 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8246 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8247 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8248 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8249 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8250 case ISD::SETCC: return LowerSETCC(Op, DAG);
8251 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
8252 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
8254 return LowerVASTART(Op, DAG);
8257 return LowerVAARG(Op, DAG);
8260 return LowerVACOPY(Op, DAG);
8263 return LowerSTACKRESTORE(Op, DAG);
8266 return LowerDYNAMIC_STACKALLOC(Op, DAG);
8269 return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
8271 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
8272 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
8274 case ISD::LOAD: return LowerLOAD(Op, DAG);
8275 case ISD::STORE: return LowerSTORE(Op, DAG);
8276 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
8277 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
8279 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
8280 SDLoc(Op));
8282 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
8283 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8286 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
8287 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
8288 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
8291 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8292 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8293 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8294 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8295 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
8296 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8297 case ISD::MUL: return LowerMUL(Op, DAG);
8303 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8304 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10369 SDValue Op(N, 0);
10372 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
10374 if (Op.getOperand(0).getValueType() == MVT::i1)
10381 if (Op.getOperand(0).getValueType() == MVT::i32)
10384 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
10389 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10390 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10392 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10394 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10400 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10402 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10403 SDValue Src = Op.getOperand(0).getOperand(0);
10413 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10419 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
11220 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
11222 Created->push_back(Op.getNode());
11225 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
11227 Created->push_back(Op.getNode());
11230 return Op;
11237 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
11243 switch (Op.getOpcode()) {
11247 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
11252 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
11479 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11499 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
11501 SDLoc dl(Op);
11550 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11592 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11598 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11601 SDLoc dl(Op);
11602 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11612 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11627 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11629 SDLoc dl(Op);
11630 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11650 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
