Lines Matching refs:v4f32
519 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
520 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
521 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
522 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
524 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
529 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
530 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
533 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
534 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
545 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
551 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
554 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
555 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
556 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
557 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
563 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
564 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
584 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
595 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
615 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
656 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
658 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
670 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);
686 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
687 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
704 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
705 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
728 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
729 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
730 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
731 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
734 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
736 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
737 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
740 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
741 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
743 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
744 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
745 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
746 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
747 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
749 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
751 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
752 v4f32, Expand);
754 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
755 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
756 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
757 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
758 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
759 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
760 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
761 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
762 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
763 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
764 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
766 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
767 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
769 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
770 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
772 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
803 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
804 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
805 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
806 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
809 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
813 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
819 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
820 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
825 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
826 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
1710 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1998 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2757 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2830 (HasQPX && (ArgVT == MVT::v4f32 ||
2837 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2967 case MVT::v4f32:
3426 case MVT::v4f32:
3454 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3462 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3467 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3622 case MVT::v4f32:
3658 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3803 case MVT::v4f32:
5081 case MVT::v4f32:
5444 case MVT::v4f32:
5467 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5517 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5523 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5531 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5663 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5892 case MVT::v4f32:
5915 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5963 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
6615 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
7138 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
7956 Op.getValueType() == MVT::v4f32) {
8050 Value.getValueType() == MVT::v4f32) {
9459 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9461 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9481 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9483 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9591 VT = MVT::v4f32;
9635 VT = MVT::v4f32;
10638 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10652 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10770 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10771 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
11427 if (VT == MVT::v4f32 && Subtarget.hasQPX())
11433 if (VT == MVT::v4f32 && Subtarget.hasQPX())
11722 VT = MVT::v4f32;
11758 VT = MVT::v4f32;
11812 VT = MVT::v4f32;
11847 VT = MVT::v4f32;
11997 VT != MVT::v4f32 && VT != MVT::v4i32)
