1 //===-- X86ShuffleDecode.cpp - X86 shuffle decode logic -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Define several functions to decode x86 specific shuffle semantics into a 11 // generic vector mask. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86ShuffleDecode.h" 16 17 //===----------------------------------------------------------------------===// 18 // Vector Mask Decoding 19 //===----------------------------------------------------------------------===// 20 21 namespace llvm { 22 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) { 24 // Defaults the copying the dest value. 25 ShuffleMask.push_back(0); 26 ShuffleMask.push_back(1); 27 ShuffleMask.push_back(2); 28 ShuffleMask.push_back(3); 29 30 // Decode the immediate. 31 unsigned ZMask = Imm & 15; 32 unsigned CountD = (Imm >> 4) & 3; 33 unsigned CountS = (Imm >> 6) & 3; 34 35 // CountS selects which input element to use. 36 unsigned InVal = 4+CountS; 37 // CountD specifies which element of destination to update. 38 ShuffleMask[CountD] = InVal; 39 // ZMask zaps values, potentially overriding the CountD elt. 40 if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero; 41 if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero; 42 if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero; 43 if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero; 44 } 45 46 // <3,1> or <6,7,2,3> 47 void DecodeMOVHLPSMask(unsigned NElts, 48 SmallVectorImpl<unsigned> &ShuffleMask) { 49 for (unsigned i = NElts/2; i != NElts; ++i) 50 ShuffleMask.push_back(NElts+i); 51 52 for (unsigned i = NElts/2; i != NElts; ++i) 53 ShuffleMask.push_back(i); 54 } 55 56 // <0,2> or <0,1,4,5> 57 void DecodeMOVLHPSMask(unsigned NElts, 58 SmallVectorImpl<unsigned> &ShuffleMask) { 59 for (unsigned i = 0; i != NElts/2; ++i) 60 ShuffleMask.push_back(i); 61 62 for (unsigned i = 0; i != NElts/2; ++i) 63 ShuffleMask.push_back(NElts+i); 64 } 65 66 void DecodePSHUFMask(unsigned NElts, unsigned Imm, 67 SmallVectorImpl<unsigned> &ShuffleMask) { 68 for (unsigned i = 0; i != NElts; ++i) { 69 ShuffleMask.push_back(Imm % NElts); 70 Imm /= NElts; 71 } 72 } 73 74 void DecodePSHUFHWMask(unsigned Imm, 75 SmallVectorImpl<unsigned> &ShuffleMask) { 76 ShuffleMask.push_back(0); 77 ShuffleMask.push_back(1); 78 ShuffleMask.push_back(2); 79 ShuffleMask.push_back(3); 80 for (unsigned i = 0; i != 4; ++i) { 81 ShuffleMask.push_back(4+(Imm & 3)); 82 Imm >>= 2; 83 } 84 } 85 86 void DecodePSHUFLWMask(unsigned Imm, 87 SmallVectorImpl<unsigned> &ShuffleMask) { 88 for (unsigned i = 0; i != 4; ++i) { 89 ShuffleMask.push_back((Imm & 3)); 90 Imm >>= 2; 91 } 92 ShuffleMask.push_back(4); 93 ShuffleMask.push_back(5); 94 ShuffleMask.push_back(6); 95 ShuffleMask.push_back(7); 96 } 97 98 void DecodePUNPCKLBWMask(unsigned NElts, 99 SmallVectorImpl<unsigned> &ShuffleMask) { 100 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i8, NElts), ShuffleMask); 101 } 102 103 void DecodePUNPCKLWDMask(unsigned NElts, 104 SmallVectorImpl<unsigned> &ShuffleMask) { 105 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i16, NElts), ShuffleMask); 106 } 107 108 void DecodePUNPCKLDQMask(unsigned NElts, 109 SmallVectorImpl<unsigned> &ShuffleMask) { 110 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i32, NElts), ShuffleMask); 111 } 112 113 void DecodePUNPCKLQDQMask(unsigned NElts, 114 SmallVectorImpl<unsigned> &ShuffleMask) { 115 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask); 116 } 117 118 void DecodePUNPCKLMask(EVT VT, 119 SmallVectorImpl<unsigned> &ShuffleMask) { 120 DecodeUNPCKLPMask(VT, ShuffleMask); 121 } 122 123 void DecodePUNPCKHMask(unsigned NElts, 124 SmallVectorImpl<unsigned> &ShuffleMask) { 125 for (unsigned i = 0; i != NElts/2; ++i) { 126 ShuffleMask.push_back(i+NElts/2); 127 ShuffleMask.push_back(i+NElts+NElts/2); 128 } 129 } 130 131 void DecodeSHUFPSMask(unsigned NElts, unsigned Imm, 132 SmallVectorImpl<unsigned> &ShuffleMask) { 133 // Part that reads from dest. 134 for (unsigned i = 0; i != NElts/2; ++i) { 135 ShuffleMask.push_back(Imm % NElts); 136 Imm /= NElts; 137 } 138 // Part that reads from src. 139 for (unsigned i = 0; i != NElts/2; ++i) { 140 ShuffleMask.push_back(Imm % NElts + NElts); 141 Imm /= NElts; 142 } 143 } 144 145 void DecodeUNPCKHPMask(unsigned NElts, 146 SmallVectorImpl<unsigned> &ShuffleMask) { 147 for (unsigned i = 0; i != NElts/2; ++i) { 148 ShuffleMask.push_back(i+NElts/2); // Reads from dest 149 ShuffleMask.push_back(i+NElts+NElts/2); // Reads from src 150 } 151 } 152 153 void DecodeUNPCKLPSMask(unsigned NElts, 154 SmallVectorImpl<unsigned> &ShuffleMask) { 155 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i32, NElts), ShuffleMask); 156 } 157 158 void DecodeUNPCKLPDMask(unsigned NElts, 159 SmallVectorImpl<unsigned> &ShuffleMask) { 160 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask); 161 } 162 163 /// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd 164 /// etc. VT indicates the type of the vector allowing it to handle different 165 /// datatypes and vector widths. 166 void DecodeUNPCKLPMask(EVT VT, 167 SmallVectorImpl<unsigned> &ShuffleMask) { 168 unsigned NumElts = VT.getVectorNumElements(); 169 170 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 171 // independently on 128-bit lanes. 172 unsigned NumLanes = VT.getSizeInBits() / 128; 173 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX 174 unsigned NumLaneElts = NumElts / NumLanes; 175 176 unsigned Start = 0; 177 unsigned End = NumLaneElts / 2; 178 for (unsigned s = 0; s < NumLanes; ++s) { 179 for (unsigned i = Start; i != End; ++i) { 180 ShuffleMask.push_back(i); // Reads from dest/src1 181 ShuffleMask.push_back(i+NumLaneElts); // Reads from src/src2 182 } 183 // Process the next 128 bits. 184 Start += NumLaneElts; 185 End += NumLaneElts; 186 } 187 } 188 189 // DecodeVPERMILPSMask - Decodes VPERMILPS permutes for any 128-bit 32-bit 190 // elements. For 256-bit vectors, it's considered as two 128 lanes, the 191 // referenced elements can't cross lanes and the mask of the first lane must 192 // be the same of the second. 193 void DecodeVPERMILPSMask(unsigned NumElts, unsigned Imm, 194 SmallVectorImpl<unsigned> &ShuffleMask) { 195 unsigned NumLanes = (NumElts*32)/128; 196 unsigned LaneSize = NumElts/NumLanes; 197 198 for (unsigned l = 0; l != NumLanes; ++l) { 199 for (unsigned i = 0; i != LaneSize; ++i) { 200 unsigned Idx = (Imm >> (i*2)) & 0x3 ; 201 ShuffleMask.push_back(Idx+(l*LaneSize)); 202 } 203 } 204 } 205 206 // DecodeVPERMILPDMask - Decodes VPERMILPD permutes for any 128-bit 64-bit 207 // elements. For 256-bit vectors, it's considered as two 128 lanes, the 208 // referenced elements can't cross lanes but the mask of the first lane can 209 // be the different of the second (not like VPERMILPS). 210 void DecodeVPERMILPDMask(unsigned NumElts, unsigned Imm, 211 SmallVectorImpl<unsigned> &ShuffleMask) { 212 unsigned NumLanes = (NumElts*64)/128; 213 unsigned LaneSize = NumElts/NumLanes; 214 215 for (unsigned l = 0; l < NumLanes; ++l) { 216 for (unsigned i = l*LaneSize; i < LaneSize*(l+1); ++i) { 217 unsigned Idx = (Imm >> i) & 0x1; 218 ShuffleMask.push_back(Idx+(l*LaneSize)); 219 } 220 } 221 } 222 223 void DecodeVPERM2F128Mask(EVT VT, unsigned Imm, 224 SmallVectorImpl<unsigned> &ShuffleMask) { 225 unsigned HalfSize = VT.getVectorNumElements()/2; 226 unsigned FstHalfBegin = (Imm & 0x3) * HalfSize; 227 unsigned SndHalfBegin = ((Imm >> 4) & 0x3) * HalfSize; 228 229 for (int i = FstHalfBegin, e = FstHalfBegin+HalfSize; i != e; ++i) 230 ShuffleMask.push_back(i); 231 for (int i = SndHalfBegin, e = SndHalfBegin+HalfSize; i != e; ++i) 232 ShuffleMask.push_back(i); 233 } 234 235 void DecodeVPERM2F128Mask(unsigned Imm, 236 SmallVectorImpl<unsigned> &ShuffleMask) { 237 // VPERM2F128 is used by any 256-bit EVT, but X86InstComments only 238 // has information about the instruction and not the types. So for 239 // instruction comments purpose, assume the 256-bit vector is v4i64. 240 return DecodeVPERM2F128Mask(MVT::v4i64, Imm, ShuffleMask); 241 } 242 243 } // llvm namespace 244
