| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
45 MachineInstr *DefMI = LastMI;
58 DefMI = &*I;
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
|
| MLxExpansionPass.cpp | 95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
97 if (DefMI->getParent() != MBB)
99 if (DefMI->isCopyLike()) {
100 Reg = DefMI->getOperand(1).getReg();
102 DefMI = MRI->getVRegDef(Reg);
105 } else if (DefMI->isInsertSubreg()) {
106 Reg = DefMI->getOperand(2).getReg();
108 DefMI = MRI->getVRegDef(Reg);
114 return DefMI;
149 MachineInstr *DefMI = MRI->getVRegDef(Reg)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
48 MachineInstr *DefMI = LastMI;
58 DefMI = &*I;
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 hasRAWHazard(DefMI, MI, TRI))) {
|
| MLxExpansionPass.cpp | 92 MachineInstr *DefMI = MRI->getVRegDef(Reg);
94 if (DefMI->getParent() != MBB)
96 if (DefMI->isCopyLike()) {
97 Reg = DefMI->getOperand(1).getReg();
99 DefMI = MRI->getVRegDef(Reg);
102 } else if (DefMI->isInsertSubreg()) {
103 Reg = DefMI->getOperand(2).getReg();
105 DefMI = MRI->getVRegDef(Reg);
111 return DefMI;
160 MachineInstr *DefMI = getAccDefMI(MI)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCMIPeephole.cpp | 126 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
130 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
131 unsigned FeedImmed = DefMI->getOperand(3).getImm();
133 = lookThruCopyLike(DefMI->getOperand(1).getReg());
135 = lookThruCopyLike(DefMI->getOperand(2).getReg());
156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
169 .addOperand(DefMI->getOperand(1));
|
| PPCVSXSwapRemoval.cpp | 614 MachineInstr* DefMI = MRI->getVRegDef(Reg);
615 assert(SwapMap.find(DefMI) != SwapMap.end() &&
617 int DefIdx = SwapMap[DefMI];
624 DEBUG(DefMI->dump());
694 MachineInstr *DefMI = MRI->getVRegDef(UseReg);
695 unsigned DefReg = DefMI->getOperand(0).getReg();
696 int DefIdx = SwapMap[DefMI];
706 DEBUG(DefMI->dump());
712 // Ensure all uses of the register defined by DefMI feed store
724 DEBUG(DefMI->dump())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| LiveRangeEdit.cpp | 45 const MachineInstr *DefMI,
48 assert(DefMI && "Missing instruction");
50 if (!tii.isTriviallyReMaterializable(DefMI, aa))
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
65 if (!DefMI)
67 checkRematerializable(VNI, DefMI, tii, aa);
167 MachineInstr *DefMI = 0, *UseMI = 0;
175 if (DefMI && DefMI != MI)
179 DefMI = MI
[all...] |
| PHIElimination.cpp | 134 MachineInstr *DefMI = *I;
135 unsigned DefReg = DefMI->getOperand(0).getReg();
137 DefMI->eraseFromParent();
176 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
177 if (!DefMI || !DefMI->isImplicitDef())
297 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
298 if (DefMI->isImplicitDef()) {
299 ImpDefs.insert(DefMI);
|
| PeepholeOptimizer.cpp | 294 MachineInstr *DefMI = MRI->getVRegDef(Src);
295 if (!DefMI || !DefMI->getDesc().isBitcast())
299 NumDefs = DefMI->getDesc().getNumDefs();
300 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs;
304 const MachineOperand &MO = DefMI->getOperand(i);
|
| MachineCSE.cpp | 125 MachineInstr *DefMI = MRI->getVRegDef(Reg);
126 if (DefMI->getParent() != MBB)
128 if (!DefMI->isCopy())
130 unsigned SrcReg = DefMI->getOperand(1).getReg();
133 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
137 DEBUG(dbgs() << "Coalescing: " << *DefMI);
141 DefMI->eraseFromParent();
|
| ScheduleDAGInstrs.cpp | 599 MachineInstr *DefMI = Def->getInstr();
600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
602 const MachineOperand &MO = DefMI->getOperand(DefIdx);
604 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
633 unsigned DefClass = DefMI->getDesc().getSchedClass();
|
| StrongPHIElimination.cpp | 254 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
255 if (DefMI)
256 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
[all...] |
| TailDuplication.cpp | 226 MachineInstr *DefMI = MRI->getVRegDef(VReg);
228 if (DefMI) {
229 DefBB = DefMI->getParent();
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 155 const MachineInstr *DefMI, unsigned DefOperIdx,
159 return TII->defaultDefLatency(SchedModel, *DefMI);
164 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
168 unsigned DefClass = DefMI->getDesc().getSchedClass();
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
183 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef(
[all...] |
| LiveRangeEdit.cpp | 52 const MachineInstr *DefMI,
54 assert(DefMI && "Missing instruction");
56 if (!TII.isTriviallyReMaterializable(*DefMI, aa))
69 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
70 if (!DefMI)
72 checkRematerializable(OrigVNI, DefMI, aa);
166 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
172 if (DefMI && DefMI != MI)
176 DefMI = MI
[all...] |
| DetectDeadLanes.cpp | 362 const MachineInstr &DefMI = *Def.getParent();
363 if (lowersToCopies(DefMI)) {
380 for (const MachineOperand &MO : DefMI.uses()) {
390 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
407 unsigned OpNum = DefMI.getOperandNo(&MO);
412 if (DefMI.isImplicitDef() || Def.isDead())
516 // Transfer UsedLanes to operands of DefMI (backwards dataflow).
|
| MachineCSE.cpp | 132 MachineInstr *DefMI = MRI->getVRegDef(Reg);
133 if (!DefMI->isCopy())
135 unsigned SrcReg = DefMI->getOperand(1).getReg();
138 if (DefMI->getOperand(0).getSubReg())
152 if (DefMI->getOperand(1).getSubReg())
157 DEBUG(dbgs() << "Coalescing: " << *DefMI);
164 DefMI->eraseFromParent();
|
| MachineSink.cpp | 175 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
176 if (DefMI->isCopyLike())
178 DEBUG(dbgs() << "Coalescing: " << *DefMI);
396 MachineInstr *DefMI = MRI->getVRegDef(Reg);
397 if (DefMI->getParent() == MI.getParent())
|
| EarlyIfConversion.cpp | 245 MachineInstr *DefMI = MRI->getVRegDef(Reg);
246 if (!DefMI || DefMI->getParent() != Head)
248 if (InsertAfter.insert(DefMI).second)
249 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
250 if (DefMI->isTerminator()) {
|
| TailDuplicator.cpp | 160 MachineInstr *DefMI = MRI->getVRegDef(VReg);
162 if (DefMI) {
163 DefBB = DefMI->getParent();
[all...] |
| InlineSpiller.cpp | 385 MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def);
386 assert(DefMI && "Defining instruction disappeared");
387 MII = DefMI;
[all...] |
| PeepholeOptimizer.cpp | [all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.cpp | 501 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI, this);
502 bool Invert = !DefMI;
503 if (!DefMI)
504 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI, this);
505 if (!DefMI)
515 // Create a new predicated version of DefMI.
517 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
519 // Copy all the DefMI operands, excluding its (null) predicate.
520 const MCInstrDesc &DefDesc = DefMI->getDesc();
523 NewMI.addOperand(DefMI->getOperand(i))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 261 MachineInstr *DefMI = MRI.getVRegDef(Reg);
263 assert(DefMI);
265 // See if DefMI is an instruction that loads from a GOT entry that holds the
267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3)
270 unsigned Flags = DefMI->getOperand(2).getTargetFlags();
276 assert(DefMI->hasOneMemOperand());
277 Val = (*DefMI->memoperands_begin())->getValue();
279 Val = (*DefMI->memoperands_begin())->getPseudoValue();
|
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 317 for (auto DefMI : List) {
319 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1);
331 MRI->getRegClass(DefMI->getOperand(0).getReg()))
338 int DistTemp = calcInstrDist(*DefMI, MI);
348 BestLEA = DefMI;
487 MachineInstr *DefMI;
490 if (!chooseBestLEA(LEAs[getMemOpKey(MI, MemOpNo)], MI, DefMI, AddrDispShift,
501 DefMI->removeFromParent();
502 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI);
503 InstrPos[DefMI] = InstrPos[&MI] - 1
[all...] |
