Home | History | Annotate | Download | only in ARM 
      1 //===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "ARMHazardRecognizer.h"
     11 #include "ARMBaseInstrInfo.h"
     12 #include "ARMBaseRegisterInfo.h"
     13 #include "ARMSubtarget.h"
     14 #include "llvm/CodeGen/MachineInstr.h"
     15 #include "llvm/CodeGen/ScheduleDAG.h"
     16 #include "llvm/Target/TargetRegisterInfo.h"
     17 using namespace llvm;
     18 
     19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
     20                          const TargetRegisterInfo &TRI) {
     21   // FIXME: Detect integer instructions properly.
     22   const MCInstrDesc &MCID = MI->getDesc();
     23   unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
     24   if (MCID.mayStore())
     25     return false;
     26   unsigned Opcode = MCID.getOpcode();
     27   if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
     28     return false;
     29   if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON))
     30     return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
     31   return false;
     32 }
     33 
     34 ScheduleHazardRecognizer::HazardType
     35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
     36   assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
     37 
     38   MachineInstr *MI = SU->getInstr();
     39 
     40   if (!MI->isDebugValue()) {
     41     if (ITBlockSize && MI != ITBlockMIs[ITBlockSize-1])
     42       return Hazard;
     43 
     44     // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
     45     // a VMLA / VMLS will cause 4 cycle stall.
     46     const MCInstrDesc &MCID = MI->getDesc();
     47     if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
     48       MachineInstr *DefMI = LastMI;
     49       const MCInstrDesc &LastMCID = LastMI->getDesc();
     50       // Skip over one non-VFP / NEON instruction.
     51       if (!LastMCID.isBarrier() &&
     52           // On A9, AGU and NEON/FPU are muxed.
     53           !(STI.isCortexA9() && (LastMCID.mayLoad() || LastMCID.mayStore())) &&
     54           (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
     55         MachineBasicBlock::iterator I = LastMI;
     56         if (I != LastMI->getParent()->begin()) {
     57           I = llvm::prior(I);
     58           DefMI = &*I;
     59         }
     60       }
     61 
     62       if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
     63           (TII.canCauseFpMLxStall(MI->getOpcode()) ||
     64            hasRAWHazard(DefMI, MI, TRI))) {
     65         // Try to schedule another instruction for the next 4 cycles.
     66         if (FpMLxStalls == 0)
     67           FpMLxStalls = 4;
     68         return Hazard;
     69       }
     70     }
     71   }
     72 
     73   return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
     74 }
     75 
     76 void ARMHazardRecognizer::Reset() {
     77   LastMI = 0;
     78   FpMLxStalls = 0;
     79   ITBlockSize = 0;
     80   ScoreboardHazardRecognizer::Reset();
     81 }
     82 
     83 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
     84   MachineInstr *MI = SU->getInstr();
     85   unsigned Opcode = MI->getOpcode();
     86   if (ITBlockSize) {
     87     --ITBlockSize;
     88   } else if (Opcode == ARM::t2IT) {
     89     unsigned Mask = MI->getOperand(1).getImm();
     90     unsigned NumTZ = CountTrailingZeros_32(Mask);
     91     assert(NumTZ <= 3 && "Invalid IT mask!");
     92     ITBlockSize = 4 - NumTZ;
     93     MachineBasicBlock::iterator I = MI;
     94     for (unsigned i = 0; i < ITBlockSize; ++i) {
     95       // Advance to the next instruction, skipping any dbg_value instructions.
     96       do {
     97         ++I;
     98       } while (I->isDebugValue());
     99       ITBlockMIs[ITBlockSize-1-i] = &*I;
    100     }
    101   }
    102 
    103   if (!MI->isDebugValue()) {
    104     LastMI = MI;
    105     FpMLxStalls = 0;
    106   }
    107 
    108   ScoreboardHazardRecognizer::EmitInstruction(SU);
    109 }
    110 
    111 void ARMHazardRecognizer::AdvanceCycle() {
    112   if (FpMLxStalls && --FpMLxStalls == 0)
    113     // Stalled for 4 cycles but still can't schedule any other instructions.
    114     LastMI = 0;
    115   ScoreboardHazardRecognizer::AdvanceCycle();
    116 }
    117 
    118 void ARMHazardRecognizer::RecedeCycle() {
    119   llvm_unreachable("reverse ARM hazard checking unsupported");
    120 }
    121