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      1 /* CPU data header for epiphany.
      2 
      3 THIS FILE IS MACHINE GENERATED WITH CGEN.
      4 
      5 Copyright (C) 1996-2014 Free Software Foundation, Inc.
      6 
      7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
      8 
      9    This file is free software; you can redistribute it and/or modify
     10    it under the terms of the GNU General Public License as published by
     11    the Free Software Foundation; either version 3, or (at your option)
     12    any later version.
     13 
     14    It is distributed in the hope that it will be useful, but WITHOUT
     15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     17    License for more details.
     18 
     19    You should have received a copy of the GNU General Public License along
     20    with this program; if not, write to the Free Software Foundation, Inc.,
     21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
     22 
     23 */
     24 
     25 #ifndef EPIPHANY_CPU_H
     26 #define EPIPHANY_CPU_H
     27 
     28 #define CGEN_ARCH epiphany
     29 
     30 /* Given symbol S, return epiphany_cgen_<S>.  */
     31 #define CGEN_SYM(s) epiphany##_cgen_##s
     32 
     33 
     34 /* Selected cpu families.  */
     35 #define HAVE_CPU_EPIPHANYBF
     36 #define HAVE_CPU_EPIPHANYMF
     37 
     38 #define CGEN_INSN_LSB0_P 1
     39 
     40 /* Minimum size of any insn (in bytes).  */
     41 #define CGEN_MIN_INSN_SIZE 2
     42 
     43 /* Maximum size of any insn (in bytes).  */
     44 #define CGEN_MAX_INSN_SIZE 4
     45 
     46 #define CGEN_INT_INSN_P 1
     47 
     48 /* Maximum number of syntax elements in an instruction.  */
     49 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
     50 
     51 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
     52    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
     53    we can't hash on everything up to the space.  */
     54 #define CGEN_MNEMONIC_OPERANDS
     55 
     56 /* Maximum number of fields in an instruction.  */
     57 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
     58 
     59 /* Enums.  */
     60 
     61 /* Enum declaration for opc enums.  */
     62 typedef enum insn_opc {
     63   OP4_BRANCH16, OP4_LDSTR16X, OP4_FLOW16, OP4_IMM16
     64  , OP4_LDSTR16D, OP4_LDSTR16P, OP4_LSHIFT16, OP4_DSP16
     65  , OP4_BRANCH, OP4_LDSTRX, OP4_ALU16, OP4_IMM32
     66  , OP4_LDSTRD, OP4_LDSTRP, OP4_ASHIFT16, OP4_MISC
     67 } INSN_OPC;
     68 
     69 /* Enum declaration for memory access width.  */
     70 typedef enum insn_wordsize {
     71   OPW_BYTE, OPW_SHORT, OPW_WORD, OPW_DOUBLE
     72 } INSN_WORDSIZE;
     73 
     74 /* Enum declaration for memory access direction.  */
     75 typedef enum insn_memory_access {
     76   OP_LOAD, OP_STORE
     77 } INSN_MEMORY_ACCESS;
     78 
     79 /* Enum declaration for trap instruction dispatch code.  */
     80 typedef enum trap_codes {
     81   TRAP_WRITE, TRAP_READ, TRAP_OPEN, TRAP_EXIT
     82  , TRAP_PASS, TRAP_FAIL, TRAP_CLOSE, TRAP_OTHER
     83 } TRAP_CODES;
     84 
     85 /* Enum declaration for branch conditions.  */
     86 typedef enum insn_cond {
     87   OPC_EQ, OPC_NE, OPC_GTU, OPC_GTEU
     88  , OPC_LTEU, OPC_LTU, OPC_GT, OPC_GTE
     89  , OPC_LT, OPC_LTE, OPC_BEQ, OPC_BNE
     90  , OPC_BLT, OPC_BLTE, OPC_B, OPC_BL
     91 } INSN_COND;
     92 
     93 /* Enum declaration for binary operator subcodes.  */
     94 typedef enum insn_bop {
     95   OPB_EOR, OPB_ADD, OPB_LSL, OPB_SUB
     96  , OPB_LSR, OPB_AND, OPB_ASR, OPB_ORR
     97 } INSN_BOP;
     98 
     99 /* Enum declaration for binary operator subcodes.  */
    100 typedef enum insn_bopext {
    101   OPBE_FEXT, OPBE_FDEP, OPBE_LFSR
    102 } INSN_BOPEXT;
    103 
    104 /* Enum declaration for floating operators.  */
    105 typedef enum insn_fop {
    106   OPF_ADD, OPF_SUB, OPF_MUL, OPF_MADD
    107  , OPF_MSUB, OPF_FLOAT, OPF_FIX, OPF_FABS
    108 } INSN_FOP;
    109 
    110 /* Enum declaration for extended floating operators.  */
    111 typedef enum insn_fopexn {
    112   OPF_FRECIP, OPF_FSQRT
    113 } INSN_FOPEXN;
    114 
    115 /* Enum declaration for immediate operators.  */
    116 typedef enum insn_immop {
    117   OPI_ADD = 1, OPI_SUB = 3, OPI_TRAP = 7
    118 } INSN_IMMOP;
    119 
    120 /* Enum declaration for don't cares.  */
    121 typedef enum insn_dc_25_2 {
    122   OPI_25_2_MBZ
    123 } INSN_DC_25_2;
    124 
    125 /* Enum declaration for .  */
    126 typedef enum gr_names {
    127   H_REGISTERS_FP = 11, H_REGISTERS_SP = 13, H_REGISTERS_LR = 14, H_REGISTERS_R0 = 0
    128  , H_REGISTERS_R1 = 1, H_REGISTERS_R2 = 2, H_REGISTERS_R3 = 3, H_REGISTERS_R4 = 4
    129  , H_REGISTERS_R5 = 5, H_REGISTERS_R6 = 6, H_REGISTERS_R7 = 7, H_REGISTERS_R8 = 8
    130  , H_REGISTERS_R9 = 9, H_REGISTERS_R10 = 10, H_REGISTERS_R11 = 11, H_REGISTERS_R12 = 12
    131  , H_REGISTERS_R13 = 13, H_REGISTERS_R14 = 14, H_REGISTERS_R15 = 15, H_REGISTERS_R16 = 16
    132  , H_REGISTERS_R17 = 17, H_REGISTERS_R18 = 18, H_REGISTERS_R19 = 19, H_REGISTERS_R20 = 20
    133  , H_REGISTERS_R21 = 21, H_REGISTERS_R22 = 22, H_REGISTERS_R23 = 23, H_REGISTERS_R24 = 24
    134  , H_REGISTERS_R25 = 25, H_REGISTERS_R26 = 26, H_REGISTERS_R27 = 27, H_REGISTERS_R28 = 28
    135  , H_REGISTERS_R29 = 29, H_REGISTERS_R30 = 30, H_REGISTERS_R31 = 31, H_REGISTERS_R32 = 32
    136  , H_REGISTERS_R33 = 33, H_REGISTERS_R34 = 34, H_REGISTERS_R35 = 35, H_REGISTERS_R36 = 36
    137  , H_REGISTERS_R37 = 37, H_REGISTERS_R38 = 38, H_REGISTERS_R39 = 39, H_REGISTERS_R40 = 40
    138  , H_REGISTERS_R41 = 41, H_REGISTERS_R42 = 42, H_REGISTERS_R43 = 43, H_REGISTERS_R44 = 44
    139  , H_REGISTERS_R45 = 45, H_REGISTERS_R46 = 46, H_REGISTERS_R47 = 47, H_REGISTERS_R48 = 48
    140  , H_REGISTERS_R49 = 49, H_REGISTERS_R50 = 50, H_REGISTERS_R51 = 51, H_REGISTERS_R52 = 52
    141  , H_REGISTERS_R53 = 53, H_REGISTERS_R54 = 54, H_REGISTERS_R55 = 55, H_REGISTERS_R56 = 56
    142  , H_REGISTERS_R57 = 57, H_REGISTERS_R58 = 58, H_REGISTERS_R59 = 59, H_REGISTERS_R60 = 60
    143  , H_REGISTERS_R61 = 61, H_REGISTERS_R62 = 62, H_REGISTERS_R63 = 63, H_REGISTERS_A1 = 0
    144  , H_REGISTERS_A2 = 1, H_REGISTERS_A3 = 2, H_REGISTERS_A4 = 3, H_REGISTERS_V1 = 4
    145  , H_REGISTERS_V2 = 5, H_REGISTERS_V3 = 6, H_REGISTERS_V4 = 7, H_REGISTERS_V5 = 8
    146  , H_REGISTERS_V6 = 9, H_REGISTERS_V7 = 10, H_REGISTERS_V8 = 11, H_REGISTERS_SB = 9
    147  , H_REGISTERS_SL = 10, H_REGISTERS_IP = 12
    148 } GR_NAMES;
    149 
    150 /* Enum declaration for +/- index register.  */
    151 typedef enum post_index {
    152   DIR_POSTINC, DIR_POSTDEC
    153 } POST_INDEX;
    154 
    155 /* Enum declaration for postmodify displacement.  */
    156 typedef enum disp_post_modify {
    157   PMOD_DISP, PMOD_POST
    158 } DISP_POST_MODIFY;
    159 
    160 /* Enum declaration for .  */
    161 typedef enum cr_names {
    162   H_CORE_REGISTERS_CONFIG, H_CORE_REGISTERS_STATUS, H_CORE_REGISTERS_PC, H_CORE_REGISTERS_DEBUG
    163  , H_CORE_REGISTERS_IAB, H_CORE_REGISTERS_LC, H_CORE_REGISTERS_LS, H_CORE_REGISTERS_LE
    164  , H_CORE_REGISTERS_IRET, H_CORE_REGISTERS_IMASK, H_CORE_REGISTERS_ILAT, H_CORE_REGISTERS_ILATST
    165  , H_CORE_REGISTERS_ILATCL, H_CORE_REGISTERS_IPEND, H_CORE_REGISTERS_CTIMER0, H_CORE_REGISTERS_CTIMER1
    166  , H_CORE_REGISTERS_HSTATUS
    167 } CR_NAMES;
    168 
    169 /* Enum declaration for .  */
    170 typedef enum crdma_names {
    171   H_COREDMA_REGISTERS_DMA0CONFIG, H_COREDMA_REGISTERS_DMA0STRIDE, H_COREDMA_REGISTERS_DMA0COUNT, H_COREDMA_REGISTERS_DMA0SRCADDR
    172  , H_COREDMA_REGISTERS_DMA0DSTADDR, H_COREDMA_REGISTERS_DMA0AUTO0, H_COREDMA_REGISTERS_DMA0AUTO1, H_COREDMA_REGISTERS_DMA0STATUS
    173  , H_COREDMA_REGISTERS_DMA1CONFIG, H_COREDMA_REGISTERS_DMA1STRIDE, H_COREDMA_REGISTERS_DMA1COUNT, H_COREDMA_REGISTERS_DMA1SRCADDR
    174  , H_COREDMA_REGISTERS_DMA1DSTADDR, H_COREDMA_REGISTERS_DMA1AUTO0, H_COREDMA_REGISTERS_DMA1AUTO1, H_COREDMA_REGISTERS_DMA1STATUS
    175 } CRDMA_NAMES;
    176 
    177 /* Enum declaration for .  */
    178 typedef enum crmem_names {
    179   H_COREMEM_REGISTERS_MEMCONFIG, H_COREMEM_REGISTERS_MEMSTATUS, H_COREMEM_REGISTERS_MEMPROTECT, H_COREMEM_REGISTERS_MEMRESERVE
    180 } CRMEM_NAMES;
    181 
    182 /* Enum declaration for .  */
    183 typedef enum crmesh_names {
    184   H_COREMESH_REGISTERS_MESHCONFIG, H_COREMESH_REGISTERS_COREID, H_COREMESH_REGISTERS_MESHMULTICAST, H_COREMESH_REGISTERS_SWRESET
    185 } CRMESH_NAMES;
    186 
    187 /* Attributes.  */
    188 
    189 /* Enum declaration for machine type selection.  */
    190 typedef enum mach_attr {
    191   MACH_BASE, MACH_EPIPHANY32, MACH_MAX
    192 } MACH_ATTR;
    193 
    194 /* Enum declaration for instruction set selection.  */
    195 typedef enum isa_attr {
    196   ISA_EPIPHANY, ISA_MAX
    197 } ISA_ATTR;
    198 
    199 /* Number of architecture variants.  */
    200 #define MAX_ISAS  1
    201 #define MAX_MACHS ((int) MACH_MAX)
    202 
    203 /* Ifield support.  */
    204 
    205 /* Ifield attribute indices.  */
    206 
    207 /* Enum declaration for cgen_ifld attrs.  */
    208 typedef enum cgen_ifld_attr {
    209   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
    210  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
    211  , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
    212 } CGEN_IFLD_ATTR;
    213 
    214 /* Number of non-boolean elements in cgen_ifld_attr.  */
    215 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
    216 
    217 /* cgen_ifld attribute accessor macros.  */
    218 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
    219 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
    220 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
    221 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
    222 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
    223 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
    224 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
    225 #define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0)
    226 
    227 /* Enum declaration for epiphany ifield types.  */
    228 typedef enum ifield_type {
    229   EPIPHANY_F_NIL, EPIPHANY_F_ANYOF, EPIPHANY_F_OPC, EPIPHANY_F_OPC_4_1
    230  , EPIPHANY_F_OPC_6_3, EPIPHANY_F_OPC_8_5, EPIPHANY_F_OPC_19_4, EPIPHANY_F_CONDCODE
    231  , EPIPHANY_F_SECONDARY_CCS, EPIPHANY_F_SHIFT, EPIPHANY_F_WORDSIZE, EPIPHANY_F_STORE
    232  , EPIPHANY_F_OPC_8_1, EPIPHANY_F_OPC_31_32, EPIPHANY_F_SIMM8, EPIPHANY_F_SIMM24
    233  , EPIPHANY_F_SDISP3, EPIPHANY_F_DISP3, EPIPHANY_F_DISP8, EPIPHANY_F_IMM8
    234  , EPIPHANY_F_IMM_27_8, EPIPHANY_F_ADDSUBX, EPIPHANY_F_SUBD, EPIPHANY_F_PM
    235  , EPIPHANY_F_RM, EPIPHANY_F_RN, EPIPHANY_F_RD, EPIPHANY_F_RM_X
    236  , EPIPHANY_F_RN_X, EPIPHANY_F_RD_X, EPIPHANY_F_DC_9_1, EPIPHANY_F_SN
    237  , EPIPHANY_F_SD, EPIPHANY_F_SN_X, EPIPHANY_F_SD_X, EPIPHANY_F_DC_7_4
    238  , EPIPHANY_F_TRAP_SWI_9_1, EPIPHANY_F_GIEN_GIDIS_9_1, EPIPHANY_F_DC_15_3, EPIPHANY_F_DC_15_7
    239  , EPIPHANY_F_DC_15_6, EPIPHANY_F_TRAP_NUM, EPIPHANY_F_DC_20_1, EPIPHANY_F_DC_21_1
    240  , EPIPHANY_F_DC_21_2, EPIPHANY_F_DC_22_3, EPIPHANY_F_DC_22_2, EPIPHANY_F_DC_22_1
    241  , EPIPHANY_F_DC_25_6, EPIPHANY_F_DC_25_4, EPIPHANY_F_DC_25_2, EPIPHANY_F_DC_25_1
    242  , EPIPHANY_F_DC_28_1, EPIPHANY_F_DC_31_3, EPIPHANY_F_DISP11, EPIPHANY_F_SDISP11
    243  , EPIPHANY_F_IMM16, EPIPHANY_F_RD6, EPIPHANY_F_RN6, EPIPHANY_F_RM6
    244  , EPIPHANY_F_SD6, EPIPHANY_F_SN6, EPIPHANY_F_MAX
    245 } IFIELD_TYPE;
    246 
    247 #define MAX_IFLD ((int) EPIPHANY_F_MAX)
    248 
    249 /* Hardware attribute indices.  */
    250 
    251 /* Enum declaration for cgen_hw attrs.  */
    252 typedef enum cgen_hw_attr {
    253   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
    254  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
    255 } CGEN_HW_ATTR;
    256 
    257 /* Number of non-boolean elements in cgen_hw_attr.  */
    258 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
    259 
    260 /* cgen_hw attribute accessor macros.  */
    261 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
    262 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
    263 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
    264 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
    265 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
    266 
    267 /* Enum declaration for epiphany hardware types.  */
    268 typedef enum cgen_hw_type {
    269   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
    270  , HW_H_IADDR, HW_H_REGISTERS, HW_H_FPREGISTERS, HW_H_ZBIT
    271  , HW_H_NBIT, HW_H_CBIT, HW_H_VBIT, HW_H_VSBIT
    272  , HW_H_BZBIT, HW_H_BNBIT, HW_H_BVBIT, HW_H_BUBIT
    273  , HW_H_BIBIT, HW_H_BCBIT, HW_H_BVSBIT, HW_H_BISBIT
    274  , HW_H_BUSBIT, HW_H_EXPCAUSE0BIT, HW_H_EXPCAUSE1BIT, HW_H_EXPCAUSE2BIT
    275  , HW_H_EXTFSTALLBIT, HW_H_TRMBIT, HW_H_INVEXCENBIT, HW_H_OVFEXCENBIT
    276  , HW_H_UNEXCENBIT, HW_H_TIMER0BIT0, HW_H_TIMER0BIT1, HW_H_TIMER0BIT2
    277  , HW_H_TIMER0BIT3, HW_H_TIMER1BIT0, HW_H_TIMER1BIT1, HW_H_TIMER1BIT2
    278  , HW_H_TIMER1BIT3, HW_H_MBKPTENBIT, HW_H_CLOCKGATEENBIT, HW_H_CORECFGRESBIT12
    279  , HW_H_CORECFGRESBIT13, HW_H_CORECFGRESBIT14, HW_H_CORECFGRESBIT15, HW_H_CORECFGRESBIT16
    280  , HW_H_CORECFGRESBIT20, HW_H_CORECFGRESBIT21, HW_H_CORECFGRESBIT24, HW_H_CORECFGRESBIT25
    281  , HW_H_CORECFGRESBIT26, HW_H_CORECFGRESBIT27, HW_H_CORECFGRESBIT28, HW_H_CORECFGRESBIT29
    282  , HW_H_CORECFGRESBIT30, HW_H_CORECFGRESBIT31, HW_H_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT1
    283  , HW_H_ARITHMETIC_MODEBIT2, HW_H_GIDISABLEBIT, HW_H_KMBIT, HW_H_CAIBIT
    284  , HW_H_SFLAGBIT, HW_H_PC, HW_H_MEMADDR, HW_H_CORE_REGISTERS
    285  , HW_H_COREDMA_REGISTERS, HW_H_COREMEM_REGISTERS, HW_H_COREMESH_REGISTERS, HW_MAX
    286 } CGEN_HW_TYPE;
    287 
    288 #define MAX_HW ((int) HW_MAX)
    289 
    290 /* Operand attribute indices.  */
    291 
    292 /* Enum declaration for cgen_operand attrs.  */
    293 typedef enum cgen_operand_attr {
    294   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
    295  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
    296  , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
    297  , CGEN_OPERAND_END_NBOOLS
    298 } CGEN_OPERAND_ATTR;
    299 
    300 /* Number of non-boolean elements in cgen_operand_attr.  */
    301 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
    302 
    303 /* cgen_operand attribute accessor macros.  */
    304 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
    305 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
    306 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
    307 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
    308 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
    309 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
    310 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
    311 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
    312 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
    313 #define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0)
    314 
    315 /* Enum declaration for epiphany operand types.  */
    316 typedef enum cgen_operand_type {
    317   EPIPHANY_OPERAND_PC, EPIPHANY_OPERAND_ZBIT, EPIPHANY_OPERAND_NBIT, EPIPHANY_OPERAND_CBIT
    318  , EPIPHANY_OPERAND_VBIT, EPIPHANY_OPERAND_BZBIT, EPIPHANY_OPERAND_BNBIT, EPIPHANY_OPERAND_BVBIT
    319  , EPIPHANY_OPERAND_BCBIT, EPIPHANY_OPERAND_BUBIT, EPIPHANY_OPERAND_BIBIT, EPIPHANY_OPERAND_VSBIT
    320  , EPIPHANY_OPERAND_BVSBIT, EPIPHANY_OPERAND_BISBIT, EPIPHANY_OPERAND_BUSBIT, EPIPHANY_OPERAND_EXPCAUSE0BIT
    321  , EPIPHANY_OPERAND_EXPCAUSE1BIT, EPIPHANY_OPERAND_EXPCAUSE2BIT, EPIPHANY_OPERAND_EXTFSTALLBIT, EPIPHANY_OPERAND_TRMBIT
    322  , EPIPHANY_OPERAND_INVEXCENBIT, EPIPHANY_OPERAND_OVFEXCENBIT, EPIPHANY_OPERAND_UNEXCENBIT, EPIPHANY_OPERAND_TIMER0BIT0
    323  , EPIPHANY_OPERAND_TIMER0BIT1, EPIPHANY_OPERAND_TIMER0BIT2, EPIPHANY_OPERAND_TIMER0BIT3, EPIPHANY_OPERAND_TIMER1BIT0
    324  , EPIPHANY_OPERAND_TIMER1BIT1, EPIPHANY_OPERAND_TIMER1BIT2, EPIPHANY_OPERAND_TIMER1BIT3, EPIPHANY_OPERAND_MBKPTENBIT
    325  , EPIPHANY_OPERAND_CLOCKGATEENBIT, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2
    326  , EPIPHANY_OPERAND_CORECFGRESBIT12, EPIPHANY_OPERAND_CORECFGRESBIT13, EPIPHANY_OPERAND_CORECFGRESBIT14, EPIPHANY_OPERAND_CORECFGRESBIT15
    327  , EPIPHANY_OPERAND_CORECFGRESBIT16, EPIPHANY_OPERAND_CORECFGRESBIT20, EPIPHANY_OPERAND_CORECFGRESBIT21, EPIPHANY_OPERAND_CORECFGRESBIT24
    328  , EPIPHANY_OPERAND_CORECFGRESBIT25, EPIPHANY_OPERAND_CORECFGRESBIT26, EPIPHANY_OPERAND_CORECFGRESBIT27, EPIPHANY_OPERAND_CORECFGRESBIT28
    329  , EPIPHANY_OPERAND_CORECFGRESBIT29, EPIPHANY_OPERAND_CORECFGRESBIT30, EPIPHANY_OPERAND_CORECFGRESBIT31, EPIPHANY_OPERAND_GIDISABLEBIT
    330  , EPIPHANY_OPERAND_KMBIT, EPIPHANY_OPERAND_CAIBIT, EPIPHANY_OPERAND_SFLAGBIT, EPIPHANY_OPERAND_MEMADDR
    331  , EPIPHANY_OPERAND_SIMM24, EPIPHANY_OPERAND_SIMM8, EPIPHANY_OPERAND_RD, EPIPHANY_OPERAND_RN
    332  , EPIPHANY_OPERAND_RM, EPIPHANY_OPERAND_FRD, EPIPHANY_OPERAND_FRN, EPIPHANY_OPERAND_FRM
    333  , EPIPHANY_OPERAND_RD6, EPIPHANY_OPERAND_RN6, EPIPHANY_OPERAND_RM6, EPIPHANY_OPERAND_FRD6
    334  , EPIPHANY_OPERAND_FRN6, EPIPHANY_OPERAND_FRM6, EPIPHANY_OPERAND_SD, EPIPHANY_OPERAND_SN
    335  , EPIPHANY_OPERAND_SD6, EPIPHANY_OPERAND_SN6, EPIPHANY_OPERAND_SDDMA, EPIPHANY_OPERAND_SNDMA
    336  , EPIPHANY_OPERAND_SDMEM, EPIPHANY_OPERAND_SNMEM, EPIPHANY_OPERAND_SDMESH, EPIPHANY_OPERAND_SNMESH
    337  , EPIPHANY_OPERAND_SIMM3, EPIPHANY_OPERAND_SIMM11, EPIPHANY_OPERAND_DISP3, EPIPHANY_OPERAND_TRAPNUM6
    338  , EPIPHANY_OPERAND_SWI_NUM, EPIPHANY_OPERAND_DISP11, EPIPHANY_OPERAND_SHIFT, EPIPHANY_OPERAND_IMM16
    339  , EPIPHANY_OPERAND_IMM8, EPIPHANY_OPERAND_DIRECTION, EPIPHANY_OPERAND_DPMI, EPIPHANY_OPERAND_MAX
    340 } CGEN_OPERAND_TYPE;
    341 
    342 /* Number of operands types.  */
    343 #define MAX_OPERANDS 91
    344 
    345 /* Maximum number of operands referenced by any insn.  */
    346 #define MAX_OPERAND_INSTANCES 8
    347 
    348 /* Insn attribute indices.  */
    349 
    350 /* Enum declaration for cgen_insn attrs.  */
    351 typedef enum cgen_insn_attr {
    352   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
    353  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
    354  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_SHORT_INSN, CGEN_INSN_IMM3
    355  , CGEN_INSN_IMM8, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
    356  , CGEN_INSN_END_NBOOLS
    357 } CGEN_INSN_ATTR;
    358 
    359 /* Number of non-boolean elements in cgen_insn_attr.  */
    360 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
    361 
    362 /* cgen_insn attribute accessor macros.  */
    363 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
    364 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
    365 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
    366 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
    367 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
    368 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
    369 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
    370 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
    371 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
    372 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
    373 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
    374 #define CGEN_ATTR_CGEN_INSN_SHORT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SHORT_INSN)) != 0)
    375 #define CGEN_ATTR_CGEN_INSN_IMM3_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM3)) != 0)
    376 #define CGEN_ATTR_CGEN_INSN_IMM8_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM8)) != 0)
    377 
    378 /* cgen.h uses things we just defined.  */
    379 #include "opcode/cgen.h"
    380 
    381 extern const struct cgen_ifld epiphany_cgen_ifld_table[];
    382 
    383 /* Attributes.  */
    384 extern const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[];
    385 extern const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[];
    386 extern const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[];
    387 extern const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[];
    388 
    389 /* Hardware decls.  */
    390 
    391 extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
    392 extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
    393 extern CGEN_KEYWORD epiphany_cgen_opval_cr_names;
    394 extern CGEN_KEYWORD epiphany_cgen_opval_crdma_names;
    395 extern CGEN_KEYWORD epiphany_cgen_opval_crmem_names;
    396 extern CGEN_KEYWORD epiphany_cgen_opval_crmesh_names;
    397 
    398 extern const CGEN_HW_ENTRY epiphany_cgen_hw_table[];
    399 
    400 
    401 
    402 #endif /* EPIPHANY_CPU_H */
    403