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      1 /* CPU data for epiphany.
      2 
      3 THIS FILE IS MACHINE GENERATED WITH CGEN.
      4 
      5 Copyright (C) 1996-2014 Free Software Foundation, Inc.
      6 
      7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
      8 
      9    This file is free software; you can redistribute it and/or modify
     10    it under the terms of the GNU General Public License as published by
     11    the Free Software Foundation; either version 3, or (at your option)
     12    any later version.
     13 
     14    It is distributed in the hope that it will be useful, but WITHOUT
     15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     17    License for more details.
     18 
     19    You should have received a copy of the GNU General Public License along
     20    with this program; if not, write to the Free Software Foundation, Inc.,
     21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
     22 
     23 */
     24 
     25 #include "sysdep.h"
     26 #include <stdio.h>
     27 #include <stdarg.h>
     28 #include "ansidecl.h"
     29 #include "bfd.h"
     30 #include "symcat.h"
     31 #include "epiphany-desc.h"
     32 #include "epiphany-opc.h"
     33 #include "opintl.h"
     34 #include "libiberty.h"
     35 #include "xregex.h"
     36 
     37 /* Attributes.  */
     38 
     39 static const CGEN_ATTR_ENTRY bool_attr[] =
     40 {
     41   { "#f", 0 },
     42   { "#t", 1 },
     43   { 0, 0 }
     44 };
     45 
     46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
     47 {
     48   { "base", MACH_BASE },
     49   { "epiphany32", MACH_EPIPHANY32 },
     50   { "max", MACH_MAX },
     51   { 0, 0 }
     52 };
     53 
     54 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
     55 {
     56   { "epiphany", ISA_EPIPHANY },
     57   { "max", ISA_MAX },
     58   { 0, 0 }
     59 };
     60 
     61 const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[] =
     62 {
     63   { "MACH", & MACH_attr[0], & MACH_attr[0] },
     64   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
     65   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
     66   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
     67   { "RESERVED", &bool_attr[0], &bool_attr[0] },
     68   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
     69   { "SIGNED", &bool_attr[0], &bool_attr[0] },
     70   { "RELOC", &bool_attr[0], &bool_attr[0] },
     71   { 0, 0, 0 }
     72 };
     73 
     74 const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[] =
     75 {
     76   { "MACH", & MACH_attr[0], & MACH_attr[0] },
     77   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
     78   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
     79   { "PC", &bool_attr[0], &bool_attr[0] },
     80   { "PROFILE", &bool_attr[0], &bool_attr[0] },
     81   { 0, 0, 0 }
     82 };
     83 
     84 const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[] =
     85 {
     86   { "MACH", & MACH_attr[0], & MACH_attr[0] },
     87   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
     88   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
     89   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
     90   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
     91   { "SIGNED", &bool_attr[0], &bool_attr[0] },
     92   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
     93   { "RELAX", &bool_attr[0], &bool_attr[0] },
     94   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
     95   { "RELOC", &bool_attr[0], &bool_attr[0] },
     96   { 0, 0, 0 }
     97 };
     98 
     99 const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[] =
    100 {
    101   { "MACH", & MACH_attr[0], & MACH_attr[0] },
    102   { "ALIAS", &bool_attr[0], &bool_attr[0] },
    103   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
    104   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
    105   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
    106   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
    107   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
    108   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
    109   { "RELAXED", &bool_attr[0], &bool_attr[0] },
    110   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
    111   { "PBB", &bool_attr[0], &bool_attr[0] },
    112   { "SHORT-INSN", &bool_attr[0], &bool_attr[0] },
    113   { "IMM3", &bool_attr[0], &bool_attr[0] },
    114   { "IMM8", &bool_attr[0], &bool_attr[0] },
    115   { 0, 0, 0 }
    116 };
    117 
    118 /* Instruction set variants.  */
    119 
    120 static const CGEN_ISA epiphany_cgen_isa_table[] = {
    121   { "epiphany", 32, 32, 16, 32 },
    122   { 0, 0, 0, 0, 0 }
    123 };
    124 
    125 /* Machine variants.  */
    126 
    127 static const CGEN_MACH epiphany_cgen_mach_table[] = {
    128   { "epiphany32", "epiphany32", MACH_EPIPHANY32, 0 },
    129   { 0, 0, 0, 0 }
    130 };
    131 
    132 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] =
    133 {
    134   { "fp", 11, {0, {{{0, 0}}}}, 0, 0 },
    135   { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
    136   { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
    137   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
    138   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
    139   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
    140   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
    141   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
    142   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
    143   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
    144   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
    145   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
    146   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
    147   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
    148   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
    149   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
    150   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
    151   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
    152   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
    153   { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
    154   { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
    155   { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
    156   { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
    157   { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
    158   { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
    159   { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
    160   { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
    161   { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
    162   { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
    163   { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
    164   { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
    165   { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
    166   { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
    167   { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
    168   { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
    169   { "r32", 32, {0, {{{0, 0}}}}, 0, 0 },
    170   { "r33", 33, {0, {{{0, 0}}}}, 0, 0 },
    171   { "r34", 34, {0, {{{0, 0}}}}, 0, 0 },
    172   { "r35", 35, {0, {{{0, 0}}}}, 0, 0 },
    173   { "r36", 36, {0, {{{0, 0}}}}, 0, 0 },
    174   { "r37", 37, {0, {{{0, 0}}}}, 0, 0 },
    175   { "r38", 38, {0, {{{0, 0}}}}, 0, 0 },
    176   { "r39", 39, {0, {{{0, 0}}}}, 0, 0 },
    177   { "r40", 40, {0, {{{0, 0}}}}, 0, 0 },
    178   { "r41", 41, {0, {{{0, 0}}}}, 0, 0 },
    179   { "r42", 42, {0, {{{0, 0}}}}, 0, 0 },
    180   { "r43", 43, {0, {{{0, 0}}}}, 0, 0 },
    181   { "r44", 44, {0, {{{0, 0}}}}, 0, 0 },
    182   { "r45", 45, {0, {{{0, 0}}}}, 0, 0 },
    183   { "r46", 46, {0, {{{0, 0}}}}, 0, 0 },
    184   { "r47", 47, {0, {{{0, 0}}}}, 0, 0 },
    185   { "r48", 48, {0, {{{0, 0}}}}, 0, 0 },
    186   { "r49", 49, {0, {{{0, 0}}}}, 0, 0 },
    187   { "r50", 50, {0, {{{0, 0}}}}, 0, 0 },
    188   { "r51", 51, {0, {{{0, 0}}}}, 0, 0 },
    189   { "r52", 52, {0, {{{0, 0}}}}, 0, 0 },
    190   { "r53", 53, {0, {{{0, 0}}}}, 0, 0 },
    191   { "r54", 54, {0, {{{0, 0}}}}, 0, 0 },
    192   { "r55", 55, {0, {{{0, 0}}}}, 0, 0 },
    193   { "r56", 56, {0, {{{0, 0}}}}, 0, 0 },
    194   { "r57", 57, {0, {{{0, 0}}}}, 0, 0 },
    195   { "r58", 58, {0, {{{0, 0}}}}, 0, 0 },
    196   { "r59", 59, {0, {{{0, 0}}}}, 0, 0 },
    197   { "r60", 60, {0, {{{0, 0}}}}, 0, 0 },
    198   { "r61", 61, {0, {{{0, 0}}}}, 0, 0 },
    199   { "r62", 62, {0, {{{0, 0}}}}, 0, 0 },
    200   { "r63", 63, {0, {{{0, 0}}}}, 0, 0 },
    201   { "a1", 0, {0, {{{0, 0}}}}, 0, 0 },
    202   { "a2", 1, {0, {{{0, 0}}}}, 0, 0 },
    203   { "a3", 2, {0, {{{0, 0}}}}, 0, 0 },
    204   { "a4", 3, {0, {{{0, 0}}}}, 0, 0 },
    205   { "v1", 4, {0, {{{0, 0}}}}, 0, 0 },
    206   { "v2", 5, {0, {{{0, 0}}}}, 0, 0 },
    207   { "v3", 6, {0, {{{0, 0}}}}, 0, 0 },
    208   { "v4", 7, {0, {{{0, 0}}}}, 0, 0 },
    209   { "v5", 8, {0, {{{0, 0}}}}, 0, 0 },
    210   { "v6", 9, {0, {{{0, 0}}}}, 0, 0 },
    211   { "v7", 10, {0, {{{0, 0}}}}, 0, 0 },
    212   { "v8", 11, {0, {{{0, 0}}}}, 0, 0 },
    213   { "sb", 9, {0, {{{0, 0}}}}, 0, 0 },
    214   { "sl", 10, {0, {{{0, 0}}}}, 0, 0 },
    215   { "ip", 12, {0, {{{0, 0}}}}, 0, 0 }
    216 };
    217 
    218 CGEN_KEYWORD epiphany_cgen_opval_gr_names =
    219 {
    220   & epiphany_cgen_opval_gr_names_entries[0],
    221   82,
    222   0, 0, 0, 0, ""
    223 };
    224 
    225 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_cr_names_entries[] =
    226 {
    227   { "config", 0, {0, {{{0, 0}}}}, 0, 0 },
    228   { "status", 1, {0, {{{0, 0}}}}, 0, 0 },
    229   { "pc", 2, {0, {{{0, 0}}}}, 0, 0 },
    230   { "debug", 3, {0, {{{0, 0}}}}, 0, 0 },
    231   { "iab", 4, {0, {{{0, 0}}}}, 0, 0 },
    232   { "lc", 5, {0, {{{0, 0}}}}, 0, 0 },
    233   { "ls", 6, {0, {{{0, 0}}}}, 0, 0 },
    234   { "le", 7, {0, {{{0, 0}}}}, 0, 0 },
    235   { "iret", 8, {0, {{{0, 0}}}}, 0, 0 },
    236   { "imask", 9, {0, {{{0, 0}}}}, 0, 0 },
    237   { "ilat", 10, {0, {{{0, 0}}}}, 0, 0 },
    238   { "ilatst", 11, {0, {{{0, 0}}}}, 0, 0 },
    239   { "ilatcl", 12, {0, {{{0, 0}}}}, 0, 0 },
    240   { "ipend", 13, {0, {{{0, 0}}}}, 0, 0 },
    241   { "ctimer0", 14, {0, {{{0, 0}}}}, 0, 0 },
    242   { "ctimer1", 15, {0, {{{0, 0}}}}, 0, 0 },
    243   { "hstatus", 16, {0, {{{0, 0}}}}, 0, 0 }
    244 };
    245 
    246 CGEN_KEYWORD epiphany_cgen_opval_cr_names =
    247 {
    248   & epiphany_cgen_opval_cr_names_entries[0],
    249   17,
    250   0, 0, 0, 0, ""
    251 };
    252 
    253 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crdma_names_entries[] =
    254 {
    255   { "dma0config", 0, {0, {{{0, 0}}}}, 0, 0 },
    256   { "dma0stride", 1, {0, {{{0, 0}}}}, 0, 0 },
    257   { "dma0count", 2, {0, {{{0, 0}}}}, 0, 0 },
    258   { "dma0srcaddr", 3, {0, {{{0, 0}}}}, 0, 0 },
    259   { "dma0dstaddr", 4, {0, {{{0, 0}}}}, 0, 0 },
    260   { "dma0auto0", 5, {0, {{{0, 0}}}}, 0, 0 },
    261   { "dma0auto1", 6, {0, {{{0, 0}}}}, 0, 0 },
    262   { "dma0status", 7, {0, {{{0, 0}}}}, 0, 0 },
    263   { "dma1config", 8, {0, {{{0, 0}}}}, 0, 0 },
    264   { "dma1stride", 9, {0, {{{0, 0}}}}, 0, 0 },
    265   { "dma1count", 10, {0, {{{0, 0}}}}, 0, 0 },
    266   { "dma1srcaddr", 11, {0, {{{0, 0}}}}, 0, 0 },
    267   { "dma1dstaddr", 12, {0, {{{0, 0}}}}, 0, 0 },
    268   { "dma1auto0", 13, {0, {{{0, 0}}}}, 0, 0 },
    269   { "dma1auto1", 14, {0, {{{0, 0}}}}, 0, 0 },
    270   { "dma1status", 15, {0, {{{0, 0}}}}, 0, 0 }
    271 };
    272 
    273 CGEN_KEYWORD epiphany_cgen_opval_crdma_names =
    274 {
    275   & epiphany_cgen_opval_crdma_names_entries[0],
    276   16,
    277   0, 0, 0, 0, ""
    278 };
    279 
    280 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmem_names_entries[] =
    281 {
    282   { "memconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
    283   { "memstatus", 1, {0, {{{0, 0}}}}, 0, 0 },
    284   { "memprotect", 2, {0, {{{0, 0}}}}, 0, 0 },
    285   { "memreserve", 3, {0, {{{0, 0}}}}, 0, 0 }
    286 };
    287 
    288 CGEN_KEYWORD epiphany_cgen_opval_crmem_names =
    289 {
    290   & epiphany_cgen_opval_crmem_names_entries[0],
    291   4,
    292   0, 0, 0, 0, ""
    293 };
    294 
    295 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmesh_names_entries[] =
    296 {
    297   { "meshconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
    298   { "coreid", 1, {0, {{{0, 0}}}}, 0, 0 },
    299   { "meshmulticast", 2, {0, {{{0, 0}}}}, 0, 0 },
    300   { "swreset", 3, {0, {{{0, 0}}}}, 0, 0 }
    301 };
    302 
    303 CGEN_KEYWORD epiphany_cgen_opval_crmesh_names =
    304 {
    305   & epiphany_cgen_opval_crmesh_names_entries[0],
    306   4,
    307   0, 0, 0, 0, ""
    308 };
    309 
    310 
    311 /* The hardware table.  */
    312 
    313 #define A(a) (1 << CGEN_HW_##a)
    314 
    315 const CGEN_HW_ENTRY epiphany_cgen_hw_table[] =
    316 {
    317   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    318   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    319   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    320   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    321   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    322   { "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
    323   { "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
    324   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    325   { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    326   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    327   { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    328   { "h-vsbit", HW_H_VSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    329   { "h-bzbit", HW_H_BZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    330   { "h-bnbit", HW_H_BNBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    331   { "h-bvbit", HW_H_BVBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    332   { "h-bubit", HW_H_BUBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    333   { "h-bibit", HW_H_BIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    334   { "h-bcbit", HW_H_BCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    335   { "h-bvsbit", HW_H_BVSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    336   { "h-bisbit", HW_H_BISBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    337   { "h-busbit", HW_H_BUSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    338   { "h-expcause0bit", HW_H_EXPCAUSE0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    339   { "h-expcause1bit", HW_H_EXPCAUSE1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    340   { "h-expcause2bit", HW_H_EXPCAUSE2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    341   { "h-extFstallbit", HW_H_EXTFSTALLBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    342   { "h-trmbit", HW_H_TRMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    343   { "h-invExcEnbit", HW_H_INVEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    344   { "h-ovfExcEnbit", HW_H_OVFEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    345   { "h-unExcEnbit", HW_H_UNEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    346   { "h-timer0bit0", HW_H_TIMER0BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    347   { "h-timer0bit1", HW_H_TIMER0BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    348   { "h-timer0bit2", HW_H_TIMER0BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    349   { "h-timer0bit3", HW_H_TIMER0BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    350   { "h-timer1bit0", HW_H_TIMER1BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    351   { "h-timer1bit1", HW_H_TIMER1BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    352   { "h-timer1bit2", HW_H_TIMER1BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    353   { "h-timer1bit3", HW_H_TIMER1BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    354   { "h-mbkptEnbit", HW_H_MBKPTENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    355   { "h-clockGateEnbit", HW_H_CLOCKGATEENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    356   { "h-coreCfgResBit12", HW_H_CORECFGRESBIT12, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    357   { "h-coreCfgResBit13", HW_H_CORECFGRESBIT13, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    358   { "h-coreCfgResBit14", HW_H_CORECFGRESBIT14, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    359   { "h-coreCfgResBit15", HW_H_CORECFGRESBIT15, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    360   { "h-coreCfgResBit16", HW_H_CORECFGRESBIT16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    361   { "h-coreCfgResBit20", HW_H_CORECFGRESBIT20, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    362   { "h-coreCfgResBit21", HW_H_CORECFGRESBIT21, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    363   { "h-coreCfgResBit24", HW_H_CORECFGRESBIT24, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    364   { "h-coreCfgResBit25", HW_H_CORECFGRESBIT25, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    365   { "h-coreCfgResBit26", HW_H_CORECFGRESBIT26, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    366   { "h-coreCfgResBit27", HW_H_CORECFGRESBIT27, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    367   { "h-coreCfgResBit28", HW_H_CORECFGRESBIT28, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    368   { "h-coreCfgResBit29", HW_H_CORECFGRESBIT29, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    369   { "h-coreCfgResBit30", HW_H_CORECFGRESBIT30, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    370   { "h-coreCfgResBit31", HW_H_CORECFGRESBIT31, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    371   { "h-arithmetic-modebit0", HW_H_ARITHMETIC_MODEBIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    372   { "h-arithmetic-modebit1", HW_H_ARITHMETIC_MODEBIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    373   { "h-arithmetic-modebit2", HW_H_ARITHMETIC_MODEBIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    374   { "h-gidisablebit", HW_H_GIDISABLEBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    375   { "h-kmbit", HW_H_KMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    376   { "h-caibit", HW_H_CAIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    377   { "h-sflagbit", HW_H_SFLAGBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    378   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
    379   { "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
    380   { "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    381   { "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    382   { "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    383   { "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    384   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
    385 };
    386 
    387 #undef A
    388 
    389 
    390 /* The instruction field table.  */
    391 
    392 #define A(a) (1 << CGEN_IFLD_##a)
    393 
    394 const CGEN_IFLD epiphany_cgen_ifld_table[] =
    395 {
    396   { EPIPHANY_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    397   { EPIPHANY_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    398   { EPIPHANY_F_OPC, "f-opc", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    399   { EPIPHANY_F_OPC_4_1, "f-opc-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    400   { EPIPHANY_F_OPC_6_3, "f-opc-6-3", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    401   { EPIPHANY_F_OPC_8_5, "f-opc-8-5", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    402   { EPIPHANY_F_OPC_19_4, "f-opc-19-4", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    403   { EPIPHANY_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    404   { EPIPHANY_F_SECONDARY_CCS, "f-secondary-ccs", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    405   { EPIPHANY_F_SHIFT, "f-shift", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    406   { EPIPHANY_F_WORDSIZE, "f-wordsize", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    407   { EPIPHANY_F_STORE, "f-store", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    408   { EPIPHANY_F_OPC_8_1, "f-opc-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    409   { EPIPHANY_F_OPC_31_32, "f-opc-31-32", 0, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    410   { EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
    411   { EPIPHANY_F_SIMM24, "f-simm24", 0, 32, 31, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
    412   { EPIPHANY_F_SDISP3, "f-sdisp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    413   { EPIPHANY_F_DISP3, "f-disp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    414   { EPIPHANY_F_DISP8, "f-disp8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    415   { EPIPHANY_F_IMM8, "f-imm8", 0, 32, 12, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    416   { EPIPHANY_F_IMM_27_8, "f-imm-27-8", 0, 32, 27, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    417   { EPIPHANY_F_ADDSUBX, "f-addsubx", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    418   { EPIPHANY_F_SUBD, "f-subd", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    419   { EPIPHANY_F_PM, "f-pm", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    420   { EPIPHANY_F_RM, "f-rm", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    421   { EPIPHANY_F_RN, "f-rn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    422   { EPIPHANY_F_RD, "f-rd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    423   { EPIPHANY_F_RM_X, "f-rm-x", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    424   { EPIPHANY_F_RN_X, "f-rn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    425   { EPIPHANY_F_RD_X, "f-rd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    426   { EPIPHANY_F_DC_9_1, "f-dc-9-1", 0, 32, 9, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    427   { EPIPHANY_F_SN, "f-sn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    428   { EPIPHANY_F_SD, "f-sd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    429   { EPIPHANY_F_SN_X, "f-sn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    430   { EPIPHANY_F_SD_X, "f-sd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    431   { EPIPHANY_F_DC_7_4, "f-dc-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    432   { EPIPHANY_F_TRAP_SWI_9_1, "f-trap-swi-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    433   { EPIPHANY_F_GIEN_GIDIS_9_1, "f-gien-gidis-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    434   { EPIPHANY_F_DC_15_3, "f-dc-15-3", 0, 32, 15, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    435   { EPIPHANY_F_DC_15_7, "f-dc-15-7", 0, 32, 15, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    436   { EPIPHANY_F_DC_15_6, "f-dc-15-6", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    437   { EPIPHANY_F_TRAP_NUM, "f-trap-num", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    438   { EPIPHANY_F_DC_20_1, "f-dc-20-1", 0, 32, 20, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    439   { EPIPHANY_F_DC_21_1, "f-dc-21-1", 0, 32, 21, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    440   { EPIPHANY_F_DC_21_2, "f-dc-21-2", 0, 32, 21, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    441   { EPIPHANY_F_DC_22_3, "f-dc-22-3", 0, 32, 22, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    442   { EPIPHANY_F_DC_22_2, "f-dc-22-2", 0, 32, 22, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    443   { EPIPHANY_F_DC_22_1, "f-dc-22-1", 0, 32, 22, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    444   { EPIPHANY_F_DC_25_6, "f-dc-25-6", 0, 32, 25, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    445   { EPIPHANY_F_DC_25_4, "f-dc-25-4", 0, 32, 25, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    446   { EPIPHANY_F_DC_25_2, "f-dc-25-2", 0, 32, 25, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    447   { EPIPHANY_F_DC_25_1, "f-dc-25-1", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    448   { EPIPHANY_F_DC_28_1, "f-dc-28-1", 0, 32, 28, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    449   { EPIPHANY_F_DC_31_3, "f-dc-31-3", 0, 32, 31, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
    450   { EPIPHANY_F_DISP11, "f-disp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    451   { EPIPHANY_F_SDISP11, "f-sdisp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    452   { EPIPHANY_F_IMM16, "f-imm16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    453   { EPIPHANY_F_RD6, "f-rd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    454   { EPIPHANY_F_RN6, "f-rn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    455   { EPIPHANY_F_RM6, "f-rm6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    456   { EPIPHANY_F_SD6, "f-sd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    457   { EPIPHANY_F_SN6, "f-sn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    458   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
    459 };
    460 
    461 #undef A
    462 
    463 
    464 
    465 /* multi ifield declarations */
    466 
    467 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [];
    468 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [];
    469 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [];
    470 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [];
    471 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [];
    472 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [];
    473 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [];
    474 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [];
    475 
    476 
    477 /* multi ifield definitions */
    478 
    479 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [] =
    480 {
    481     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
    482     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
    483     { 0, { (const PTR) 0 } }
    484 };
    485 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [] =
    486 {
    487     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
    488     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
    489     { 0, { (const PTR) 0 } }
    490 };
    491 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [] =
    492 {
    493     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
    494     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } },
    495     { 0, { (const PTR) 0 } }
    496 };
    497 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [] =
    498 {
    499     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } },
    500     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
    501     { 0, { (const PTR) 0 } }
    502 };
    503 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [] =
    504 {
    505     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } },
    506     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
    507     { 0, { (const PTR) 0 } }
    508 };
    509 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [] =
    510 {
    511     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } },
    512     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
    513     { 0, { (const PTR) 0 } }
    514 };
    515 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [] =
    516 {
    517     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } },
    518     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
    519     { 0, { (const PTR) 0 } }
    520 };
    521 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [] =
    522 {
    523     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } },
    524     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
    525     { 0, { (const PTR) 0 } }
    526 };
    527 
    528 /* The operand table.  */
    529 
    530 #define A(a) (1 << CGEN_OPERAND_##a)
    531 #define OPERAND(op) EPIPHANY_OPERAND_##op
    532 
    533 const CGEN_OPERAND epiphany_cgen_operand_table[] =
    534 {
    535 /* pc: program counter */
    536   { "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
    537     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
    538     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    539 /* zbit: integer zero bit */
    540   { "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
    541     { 0, { (const PTR) 0 } },
    542     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    543 /* nbit: integer neg bit */
    544   { "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
    545     { 0, { (const PTR) 0 } },
    546     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    547 /* cbit: integer carry bit */
    548   { "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
    549     { 0, { (const PTR) 0 } },
    550     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    551 /* vbit: integer overflow bit */
    552   { "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
    553     { 0, { (const PTR) 0 } },
    554     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    555 /* bzbit: floating point zero bit */
    556   { "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
    557     { 0, { (const PTR) 0 } },
    558     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    559 /* bnbit: floating point neg bit */
    560   { "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
    561     { 0, { (const PTR) 0 } },
    562     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    563 /* bvbit: floating point ovfl bit */
    564   { "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
    565     { 0, { (const PTR) 0 } },
    566     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    567 /* bcbit: floating point carry bit */
    568   { "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
    569     { 0, { (const PTR) 0 } },
    570     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    571 /* bubit: floating point underfl bit */
    572   { "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
    573     { 0, { (const PTR) 0 } },
    574     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    575 /* bibit: floating point invalid bit */
    576   { "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
    577     { 0, { (const PTR) 0 } },
    578     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    579 /* vsbit: integer overflow sticky */
    580   { "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
    581     { 0, { (const PTR) 0 } },
    582     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    583 /* bvsbit: floating point overflow sticky */
    584   { "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
    585     { 0, { (const PTR) 0 } },
    586     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    587 /* bisbit: floating point invalid sticky */
    588   { "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
    589     { 0, { (const PTR) 0 } },
    590     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    591 /* busbit: floating point underflow sticky */
    592   { "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
    593     { 0, { (const PTR) 0 } },
    594     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    595 /* expcause0bit: exceprion cause bit0 */
    596   { "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
    597     { 0, { (const PTR) 0 } },
    598     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    599 /* expcause1bit: exceprion cause bit1 */
    600   { "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
    601     { 0, { (const PTR) 0 } },
    602     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    603 /* expcause2bit: external load stalled bit */
    604   { "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
    605     { 0, { (const PTR) 0 } },
    606     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    607 /* extFstallbit: external fetch stalled bit */
    608   { "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
    609     { 0, { (const PTR) 0 } },
    610     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    611 /* trmbit: 0=round to nearest, 1=trunacte selct bit */
    612   { "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
    613     { 0, { (const PTR) 0 } },
    614     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    615 /* invExcEnbit: invalid exception enable bit */
    616   { "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
    617     { 0, { (const PTR) 0 } },
    618     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    619 /* ovfExcEnbit: overflow exception enable bit */
    620   { "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
    621     { 0, { (const PTR) 0 } },
    622     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    623 /* unExcEnbit: underflow exception enable bit */
    624   { "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
    625     { 0, { (const PTR) 0 } },
    626     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    627 /* timer0bit0: timer 0 mode selection 0 */
    628   { "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
    629     { 0, { (const PTR) 0 } },
    630     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    631 /* timer0bit1: timer 0 mode selection 1 */
    632   { "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
    633     { 0, { (const PTR) 0 } },
    634     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    635 /* timer0bit2: timer 0 mode selection 2 */
    636   { "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
    637     { 0, { (const PTR) 0 } },
    638     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    639 /* timer0bit3: timer 0 mode selection 3 */
    640   { "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
    641     { 0, { (const PTR) 0 } },
    642     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    643 /* timer1bit0: timer 1 mode selection 0 */
    644   { "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
    645     { 0, { (const PTR) 0 } },
    646     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    647 /* timer1bit1: timer 1 mode selection 1 */
    648   { "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
    649     { 0, { (const PTR) 0 } },
    650     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    651 /* timer1bit2: timer 1 mode selection 2 */
    652   { "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
    653     { 0, { (const PTR) 0 } },
    654     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    655 /* timer1bit3: timer 1 mode selection 3 */
    656   { "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
    657     { 0, { (const PTR) 0 } },
    658     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    659 /* mbkptEnbit: multicore bkpt enable */
    660   { "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
    661     { 0, { (const PTR) 0 } },
    662     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    663 /* clockGateEnbit: clock gate enable enable */
    664   { "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
    665     { 0, { (const PTR) 0 } },
    666     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    667 /* arithmetic-modebit0: arithmetic mode bit0 */
    668   { "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
    669     { 0, { (const PTR) 0 } },
    670     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    671 /* arithmetic-modebit1: arithmetic mode bit1 */
    672   { "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
    673     { 0, { (const PTR) 0 } },
    674     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    675 /* arithmetic-modebit2: arithmetic mode bit2 */
    676   { "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
    677     { 0, { (const PTR) 0 } },
    678     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    679 /* coreCfgResBit12: core config bit 12 */
    680   { "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
    681     { 0, { (const PTR) 0 } },
    682     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    683 /* coreCfgResBit13: core config bit 13 */
    684   { "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
    685     { 0, { (const PTR) 0 } },
    686     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    687 /* coreCfgResBit14: core config bit 14 */
    688   { "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
    689     { 0, { (const PTR) 0 } },
    690     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    691 /* coreCfgResBit15: core config bit 15 */
    692   { "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
    693     { 0, { (const PTR) 0 } },
    694     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    695 /* coreCfgResBit16: core config bit 16 */
    696   { "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
    697     { 0, { (const PTR) 0 } },
    698     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    699 /* coreCfgResBit20: core config bit 20 */
    700   { "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
    701     { 0, { (const PTR) 0 } },
    702     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    703 /* coreCfgResBit21: core config bit 21 */
    704   { "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
    705     { 0, { (const PTR) 0 } },
    706     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    707 /* coreCfgResBit24: core config bit 24 */
    708   { "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
    709     { 0, { (const PTR) 0 } },
    710     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    711 /* coreCfgResBit25: core config bit 25 */
    712   { "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
    713     { 0, { (const PTR) 0 } },
    714     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    715 /* coreCfgResBit26: core config bit 26 */
    716   { "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
    717     { 0, { (const PTR) 0 } },
    718     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    719 /* coreCfgResBit27: core config bit 27 */
    720   { "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
    721     { 0, { (const PTR) 0 } },
    722     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    723 /* coreCfgResBit28: core config bit 28 */
    724   { "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
    725     { 0, { (const PTR) 0 } },
    726     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    727 /* coreCfgResBit29: core config bit 29 */
    728   { "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
    729     { 0, { (const PTR) 0 } },
    730     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    731 /* coreCfgResBit30: core config bit 30 */
    732   { "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
    733     { 0, { (const PTR) 0 } },
    734     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    735 /* coreCfgResBit31: core config bit 31 */
    736   { "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
    737     { 0, { (const PTR) 0 } },
    738     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    739 /* gidisablebit: global interrupt disable bit */
    740   { "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
    741     { 0, { (const PTR) 0 } },
    742     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    743 /* kmbit: kernel mode bit */
    744   { "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
    745     { 0, { (const PTR) 0 } },
    746     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    747 /* caibit: core actibe indicator bit */
    748   { "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
    749     { 0, { (const PTR) 0 } },
    750     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    751 /* sflagbit: sflag bit */
    752   { "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
    753     { 0, { (const PTR) 0 } },
    754     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    755 /* memaddr: memory effective address */
    756   { "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
    757     { 0, { (const PTR) 0 } },
    758     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
    759 /* simm24: branch address pc-relative */
    760   { "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
    761     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
    762     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
    763 /* simm8: branch address pc-relative */
    764   { "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
    765     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
    766     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
    767 /* rd: destination register */
    768   { "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
    769     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
    770     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    771 /* rn: source register */
    772   { "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
    773     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
    774     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    775 /* rm: source register */
    776   { "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
    777     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
    778     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    779 /* frd: fp destination register */
    780   { "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
    781     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
    782     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    783 /* frn: fp source register */
    784   { "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
    785     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
    786     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    787 /* frm: fp source register */
    788   { "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
    789     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
    790     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    791 /* rd6: destination register */
    792   { "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
    793     { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
    794     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    795 /* rn6: source register */
    796   { "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
    797     { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
    798     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    799 /* rm6: source register */
    800   { "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
    801     { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
    802     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    803 /* frd6: fp destination register */
    804   { "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
    805     { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
    806     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    807 /* frn6: fp source register */
    808   { "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
    809     { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
    810     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    811 /* frm6: fp source register */
    812   { "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
    813     { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
    814     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    815 /* sd: special destination */
    816   { "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
    817     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
    818     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    819 /* sn: special source */
    820   { "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
    821     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
    822     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    823 /* sd6: special destination register */
    824   { "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
    825     { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
    826     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    827 /* sn6: special source register */
    828   { "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
    829     { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
    830     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    831 /* sddma: dma register */
    832   { "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
    833     { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
    834     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    835 /* sndma: dma register */
    836   { "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
    837     { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
    838     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    839 /* sdmem: mem register */
    840   { "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
    841     { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
    842     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    843 /* snmem: mem register */
    844   { "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
    845     { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
    846     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    847 /* sdmesh: mesh register */
    848   { "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
    849     { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
    850     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    851 /* snmesh: mesh register */
    852   { "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
    853     { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
    854     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    855 /* simm3: signed 3-bit literal */
    856   { "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
    857     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
    858     { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } }  },
    859 /* simm11: signed 11-bit literal */
    860   { "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
    861     { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
    862     { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    863 /* disp3: short data displacement */
    864   { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
    865     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
    866     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    867 /* trapnum6: parameter for swi or trap */
    868   { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
    869     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
    870     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    871 /* swi_num: unsigned 6-bit swi# */
    872   { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
    873     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
    874     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    875 /* disp11: sign-magnitude data displacement */
    876   { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
    877     { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
    878     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    879 /* shift: immediate shift amount */
    880   { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
    881     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
    882     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    883 /* imm16: 16-bit unsigned literal */
    884   { "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
    885     { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
    886     { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
    887 /* imm8: 8-bit unsigned literal */
    888   { "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
    889     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
    890     { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } }  },
    891 /* direction: +/- indexing */
    892   { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
    893     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
    894     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    895 /* dpmi: +/- magnitude immediate displacement */
    896   { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
    897     { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
    898     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
    899 /* sentinel */
    900   { 0, 0, 0, 0, 0,
    901     { 0, { (const PTR) 0 } },
    902     { 0, { { { (1<<MACH_BASE), 0 } } } } }
    903 };
    904 
    905 #undef A
    906 
    907 
    908 /* The instruction table.  */
    909 
    910 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
    911 #define A(a) (1 << CGEN_INSN_##a)
    912 
    913 static const CGEN_IBASE epiphany_cgen_insn_table[MAX_INSNS] =
    914 {
    915   /* Special null first entry.
    916      A `num' value of zero is thus invalid.
    917      Also, the special `invalid' insn resides here.  */
    918   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
    919 /* beq.s $simm8 */
    920   {
    921     EPIPHANY_INSN_BEQ16, "beq16", "beq.s", 16,
    922     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    923   },
    924 /* beq.l $simm24 */
    925   {
    926     EPIPHANY_INSN_BEQ, "beq", "beq.l", 32,
    927     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    928   },
    929 /* bne.s $simm8 */
    930   {
    931     EPIPHANY_INSN_BNE16, "bne16", "bne.s", 16,
    932     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    933   },
    934 /* bne.l $simm24 */
    935   {
    936     EPIPHANY_INSN_BNE, "bne", "bne.l", 32,
    937     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    938   },
    939 /* bgtu.s $simm8 */
    940   {
    941     EPIPHANY_INSN_BGTU16, "bgtu16", "bgtu.s", 16,
    942     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    943   },
    944 /* bgtu.l $simm24 */
    945   {
    946     EPIPHANY_INSN_BGTU, "bgtu", "bgtu.l", 32,
    947     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    948   },
    949 /* bgteu.s $simm8 */
    950   {
    951     EPIPHANY_INSN_BGTEU16, "bgteu16", "bgteu.s", 16,
    952     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    953   },
    954 /* bgteu.l $simm24 */
    955   {
    956     EPIPHANY_INSN_BGTEU, "bgteu", "bgteu.l", 32,
    957     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    958   },
    959 /* blteu.s $simm8 */
    960   {
    961     EPIPHANY_INSN_BLTEU16, "blteu16", "blteu.s", 16,
    962     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    963   },
    964 /* blteu.l $simm24 */
    965   {
    966     EPIPHANY_INSN_BLTEU, "blteu", "blteu.l", 32,
    967     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    968   },
    969 /* bltu.s $simm8 */
    970   {
    971     EPIPHANY_INSN_BLTU16, "bltu16", "bltu.s", 16,
    972     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    973   },
    974 /* bltu.l $simm24 */
    975   {
    976     EPIPHANY_INSN_BLTU, "bltu", "bltu.l", 32,
    977     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    978   },
    979 /* bgt.s $simm8 */
    980   {
    981     EPIPHANY_INSN_BGT16, "bgt16", "bgt.s", 16,
    982     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    983   },
    984 /* bgt.l $simm24 */
    985   {
    986     EPIPHANY_INSN_BGT, "bgt", "bgt.l", 32,
    987     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    988   },
    989 /* bgte.s $simm8 */
    990   {
    991     EPIPHANY_INSN_BGTE16, "bgte16", "bgte.s", 16,
    992     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    993   },
    994 /* bgte.l $simm24 */
    995   {
    996     EPIPHANY_INSN_BGTE, "bgte", "bgte.l", 32,
    997     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
    998   },
    999 /* blt.s $simm8 */
   1000   {
   1001     EPIPHANY_INSN_BLT16, "blt16", "blt.s", 16,
   1002     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1003   },
   1004 /* blt.l $simm24 */
   1005   {
   1006     EPIPHANY_INSN_BLT, "blt", "blt.l", 32,
   1007     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1008   },
   1009 /* blte.s $simm8 */
   1010   {
   1011     EPIPHANY_INSN_BLTE16, "blte16", "blte.s", 16,
   1012     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1013   },
   1014 /* blte.l $simm24 */
   1015   {
   1016     EPIPHANY_INSN_BLTE, "blte", "blte.l", 32,
   1017     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1018   },
   1019 /* bbeq.s $simm8 */
   1020   {
   1021     EPIPHANY_INSN_BBEQ16, "bbeq16", "bbeq.s", 16,
   1022     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1023   },
   1024 /* bbeq.l $simm24 */
   1025   {
   1026     EPIPHANY_INSN_BBEQ, "bbeq", "bbeq.l", 32,
   1027     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1028   },
   1029 /* bbne.s $simm8 */
   1030   {
   1031     EPIPHANY_INSN_BBNE16, "bbne16", "bbne.s", 16,
   1032     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1033   },
   1034 /* bbne.l $simm24 */
   1035   {
   1036     EPIPHANY_INSN_BBNE, "bbne", "bbne.l", 32,
   1037     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1038   },
   1039 /* bblt.s $simm8 */
   1040   {
   1041     EPIPHANY_INSN_BBLT16, "bblt16", "bblt.s", 16,
   1042     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1043   },
   1044 /* bblt.l $simm24 */
   1045   {
   1046     EPIPHANY_INSN_BBLT, "bblt", "bblt.l", 32,
   1047     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1048   },
   1049 /* bblte.s $simm8 */
   1050   {
   1051     EPIPHANY_INSN_BBLTE16, "bblte16", "bblte.s", 16,
   1052     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1053   },
   1054 /* bblte.l $simm24 */
   1055   {
   1056     EPIPHANY_INSN_BBLTE, "bblte", "bblte.l", 32,
   1057     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1058   },
   1059 /* b.s $simm8 */
   1060   {
   1061     EPIPHANY_INSN_B16, "b16", "b.s", 16,
   1062     { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1063   },
   1064 /* b.l $simm24 */
   1065   {
   1066     EPIPHANY_INSN_B, "b", "b.l", 32,
   1067     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1068   },
   1069 /* bl.s $simm8 */
   1070   {
   1071     EPIPHANY_INSN_BL16, "bl16", "bl.s", 16,
   1072     { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1073   },
   1074 /* bl.l $simm24 */
   1075   {
   1076     EPIPHANY_INSN_BL, "bl", "bl.l", 32,
   1077     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1078   },
   1079 /* jr $rn */
   1080   {
   1081     EPIPHANY_INSN_JR16, "jr16", "jr", 16,
   1082     { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1083   },
   1084 /* rts */
   1085   {
   1086     -1, "rts", "rts", 32,
   1087     { 0|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
   1088   },
   1089 /* jr $rn6 */
   1090   {
   1091     EPIPHANY_INSN_JR, "jr", "jr", 32,
   1092     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1093   },
   1094 /* jalr $rn */
   1095   {
   1096     EPIPHANY_INSN_JALR16, "jalr16", "jalr", 16,
   1097     { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1098   },
   1099 /* jalr $rn6 */
   1100   {
   1101     EPIPHANY_INSN_JALR, "jalr", "jalr", 32,
   1102     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1103   },
   1104 /* ldrb $rd,[$rn,$rm] */
   1105   {
   1106     EPIPHANY_INSN_LDRBX16_S, "ldrbx16.s", "ldrb", 16,
   1107     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1108   },
   1109 /* ldrb $rd,[$rn],$rm */
   1110   {
   1111     EPIPHANY_INSN_LDRBP16_S, "ldrbp16.s", "ldrb", 16,
   1112     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1113   },
   1114 /* ldrb $rd6,[$rn6,$direction$rm6] */
   1115   {
   1116     EPIPHANY_INSN_LDRBX_L, "ldrbx.l", "ldrb", 32,
   1117     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1118   },
   1119 /* ldrb $rd6,[$rn6],$direction$rm6 */
   1120   {
   1121     EPIPHANY_INSN_LDRBP_L, "ldrbp.l", "ldrb", 32,
   1122     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1123   },
   1124 /* ldrb $rd,[$rn,$disp3] */
   1125   {
   1126     EPIPHANY_INSN_LDRBD16_S, "ldrbd16.s", "ldrb", 16,
   1127     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1128   },
   1129 /* ldrb $rd6,[$rn6,$dpmi$disp11] */
   1130   {
   1131     EPIPHANY_INSN_LDRBD_L, "ldrbd.l", "ldrb", 32,
   1132     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1133   },
   1134 /* ldrb $rd6,[$rn6],$dpmi$disp11 */
   1135   {
   1136     EPIPHANY_INSN_LDRBDPM_L, "ldrbdpm.l", "ldrb", 32,
   1137     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1138   },
   1139 /* ldrh $rd,[$rn,$rm] */
   1140   {
   1141     EPIPHANY_INSN_LDRHX16_S, "ldrhx16.s", "ldrh", 16,
   1142     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1143   },
   1144 /* ldrh $rd,[$rn],$rm */
   1145   {
   1146     EPIPHANY_INSN_LDRHP16_S, "ldrhp16.s", "ldrh", 16,
   1147     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1148   },
   1149 /* ldrh $rd6,[$rn6,$direction$rm6] */
   1150   {
   1151     EPIPHANY_INSN_LDRHX_L, "ldrhx.l", "ldrh", 32,
   1152     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1153   },
   1154 /* ldrh $rd6,[$rn6],$direction$rm6 */
   1155   {
   1156     EPIPHANY_INSN_LDRHP_L, "ldrhp.l", "ldrh", 32,
   1157     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1158   },
   1159 /* ldrh $rd,[$rn,$disp3] */
   1160   {
   1161     EPIPHANY_INSN_LDRHD16_S, "ldrhd16.s", "ldrh", 16,
   1162     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1163   },
   1164 /* ldrh $rd6,[$rn6,$dpmi$disp11] */
   1165   {
   1166     EPIPHANY_INSN_LDRHD_L, "ldrhd.l", "ldrh", 32,
   1167     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1168   },
   1169 /* ldrh $rd6,[$rn6],$dpmi$disp11 */
   1170   {
   1171     EPIPHANY_INSN_LDRHDPM_L, "ldrhdpm.l", "ldrh", 32,
   1172     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1173   },
   1174 /* ldr $rd,[$rn,$rm] */
   1175   {
   1176     EPIPHANY_INSN_LDRX16_S, "ldrx16.s", "ldr", 16,
   1177     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1178   },
   1179 /* ldr $rd,[$rn],$rm */
   1180   {
   1181     EPIPHANY_INSN_LDRP16_S, "ldrp16.s", "ldr", 16,
   1182     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1183   },
   1184 /* ldr $rd6,[$rn6,$direction$rm6] */
   1185   {
   1186     EPIPHANY_INSN_LDRX_L, "ldrx.l", "ldr", 32,
   1187     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1188   },
   1189 /* ldr $rd6,[$rn6],$direction$rm6 */
   1190   {
   1191     EPIPHANY_INSN_LDRP_L, "ldrp.l", "ldr", 32,
   1192     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1193   },
   1194 /* ldr $rd,[$rn,$disp3] */
   1195   {
   1196     EPIPHANY_INSN_LDRD16_S, "ldrd16.s", "ldr", 16,
   1197     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1198   },
   1199 /* ldr $rd6,[$rn6,$dpmi$disp11] */
   1200   {
   1201     EPIPHANY_INSN_LDRD_L, "ldrd.l", "ldr", 32,
   1202     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1203   },
   1204 /* ldr $rd6,[$rn6],$dpmi$disp11 */
   1205   {
   1206     EPIPHANY_INSN_LDRDPM_L, "ldrdpm.l", "ldr", 32,
   1207     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1208   },
   1209 /* ldrd $rd,[$rn,$rm] */
   1210   {
   1211     EPIPHANY_INSN_LDRDX16_S, "ldrdx16.s", "ldrd", 16,
   1212     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1213   },
   1214 /* ldrd $rd,[$rn],$rm */
   1215   {
   1216     EPIPHANY_INSN_LDRDP16_S, "ldrdp16.s", "ldrd", 16,
   1217     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1218   },
   1219 /* ldrd $rd6,[$rn6,$direction$rm6] */
   1220   {
   1221     EPIPHANY_INSN_LDRDX_L, "ldrdx.l", "ldrd", 32,
   1222     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1223   },
   1224 /* ldrd $rd6,[$rn6],$direction$rm6 */
   1225   {
   1226     EPIPHANY_INSN_LDRDP_L, "ldrdp.l", "ldrd", 32,
   1227     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1228   },
   1229 /* ldrd $rd,[$rn,$disp3] */
   1230   {
   1231     EPIPHANY_INSN_LDRDD16_S, "ldrdd16.s", "ldrd", 16,
   1232     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1233   },
   1234 /* ldrd $rd6,[$rn6,$dpmi$disp11] */
   1235   {
   1236     EPIPHANY_INSN_LDRDD_L, "ldrdd.l", "ldrd", 32,
   1237     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1238   },
   1239 /* ldrd $rd6,[$rn6],$dpmi$disp11 */
   1240   {
   1241     EPIPHANY_INSN_LDRDDPM_L, "ldrddpm.l", "ldrd", 32,
   1242     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1243   },
   1244 /* testsetb $rd6,[$rn6,$direction$rm6] */
   1245   {
   1246     EPIPHANY_INSN_TESTSETBT, "testsetbt", "testsetb", 32,
   1247     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1248   },
   1249 /* testseth $rd6,[$rn6,$direction$rm6] */
   1250   {
   1251     EPIPHANY_INSN_TESTSETHT, "testsetht", "testseth", 32,
   1252     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1253   },
   1254 /* testset $rd6,[$rn6,$direction$rm6] */
   1255   {
   1256     EPIPHANY_INSN_TESTSETT, "testsett", "testset", 32,
   1257     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1258   },
   1259 /* strb $rd,[$rn,$rm] */
   1260   {
   1261     EPIPHANY_INSN_STRBX16, "strbx16", "strb", 16,
   1262     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1263   },
   1264 /* strb $rd6,[$rn6,$direction$rm6] */
   1265   {
   1266     EPIPHANY_INSN_STRBX, "strbx", "strb", 32,
   1267     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1268   },
   1269 /* strb $rd,[$rn],$rm */
   1270   {
   1271     EPIPHANY_INSN_STRBP16, "strbp16", "strb", 16,
   1272     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1273   },
   1274 /* strb $rd6,[$rn6],$direction$rm6 */
   1275   {
   1276     EPIPHANY_INSN_STRBP, "strbp", "strb", 32,
   1277     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1278   },
   1279 /* strb $rd,[$rn,$disp3] */
   1280   {
   1281     EPIPHANY_INSN_STRBD16, "strbd16", "strb", 16,
   1282     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1283   },
   1284 /* strb $rd6,[$rn6,$dpmi$disp11] */
   1285   {
   1286     EPIPHANY_INSN_STRBD, "strbd", "strb", 32,
   1287     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1288   },
   1289 /* strb $rd6,[$rn6],$dpmi$disp11 */
   1290   {
   1291     EPIPHANY_INSN_STRBDPM, "strbdpm", "strb", 32,
   1292     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1293   },
   1294 /* strh $rd,[$rn,$rm] */
   1295   {
   1296     EPIPHANY_INSN_STRHX16, "strhx16", "strh", 16,
   1297     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1298   },
   1299 /* strh $rd6,[$rn6,$direction$rm6] */
   1300   {
   1301     EPIPHANY_INSN_STRHX, "strhx", "strh", 32,
   1302     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1303   },
   1304 /* strh $rd,[$rn],$rm */
   1305   {
   1306     EPIPHANY_INSN_STRHP16, "strhp16", "strh", 16,
   1307     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1308   },
   1309 /* strh $rd6,[$rn6],$direction$rm6 */
   1310   {
   1311     EPIPHANY_INSN_STRHP, "strhp", "strh", 32,
   1312     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1313   },
   1314 /* strh $rd,[$rn,$disp3] */
   1315   {
   1316     EPIPHANY_INSN_STRHD16, "strhd16", "strh", 16,
   1317     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1318   },
   1319 /* strh $rd6,[$rn6,$dpmi$disp11] */
   1320   {
   1321     EPIPHANY_INSN_STRHD, "strhd", "strh", 32,
   1322     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1323   },
   1324 /* strh $rd6,[$rn6],$dpmi$disp11 */
   1325   {
   1326     EPIPHANY_INSN_STRHDPM, "strhdpm", "strh", 32,
   1327     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1328   },
   1329 /* str $rd,[$rn,$rm] */
   1330   {
   1331     EPIPHANY_INSN_STRX16, "strx16", "str", 16,
   1332     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1333   },
   1334 /* str $rd6,[$rn6,$direction$rm6] */
   1335   {
   1336     EPIPHANY_INSN_STRX, "strx", "str", 32,
   1337     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1338   },
   1339 /* str $rd,[$rn],$rm */
   1340   {
   1341     EPIPHANY_INSN_STRP16, "strp16", "str", 16,
   1342     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1343   },
   1344 /* str $rd6,[$rn6],$direction$rm6 */
   1345   {
   1346     EPIPHANY_INSN_STRP, "strp", "str", 32,
   1347     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1348   },
   1349 /* str $rd,[$rn,$disp3] */
   1350   {
   1351     EPIPHANY_INSN_STRD16, "strd16", "str", 16,
   1352     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1353   },
   1354 /* str $rd6,[$rn6,$dpmi$disp11] */
   1355   {
   1356     EPIPHANY_INSN_STRD, "strd", "str", 32,
   1357     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1358   },
   1359 /* str $rd6,[$rn6],$dpmi$disp11 */
   1360   {
   1361     EPIPHANY_INSN_STRDPM, "strdpm", "str", 32,
   1362     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1363   },
   1364 /* strd $rd,[$rn,$rm] */
   1365   {
   1366     EPIPHANY_INSN_STRDX16, "strdx16", "strd", 16,
   1367     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1368   },
   1369 /* strd $rd6,[$rn6,$direction$rm6] */
   1370   {
   1371     EPIPHANY_INSN_STRDX, "strdx", "strd", 32,
   1372     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1373   },
   1374 /* strd $rd,[$rn],$rm */
   1375   {
   1376     EPIPHANY_INSN_STRDP16, "strdp16", "strd", 16,
   1377     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1378   },
   1379 /* strd $rd6,[$rn6],$direction$rm6 */
   1380   {
   1381     EPIPHANY_INSN_STRDP, "strdp", "strd", 32,
   1382     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1383   },
   1384 /* strd $rd,[$rn,$disp3] */
   1385   {
   1386     EPIPHANY_INSN_STRDD16, "strdd16", "strd", 16,
   1387     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1388   },
   1389 /* strd $rd6,[$rn6,$dpmi$disp11] */
   1390   {
   1391     EPIPHANY_INSN_STRDD, "strdd", "strd", 32,
   1392     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1393   },
   1394 /* strd $rd6,[$rn6],$dpmi$disp11 */
   1395   {
   1396     EPIPHANY_INSN_STRDDPM, "strddpm", "strd", 32,
   1397     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1398   },
   1399 /* moveq $rd,$rn */
   1400   {
   1401     EPIPHANY_INSN_CMOV16EQ, "cmov16EQ", "moveq", 16,
   1402     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1403   },
   1404 /* moveq $rd6,$rn6 */
   1405   {
   1406     EPIPHANY_INSN_CMOVEQ, "cmovEQ", "moveq", 32,
   1407     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1408   },
   1409 /* movne $rd,$rn */
   1410   {
   1411     EPIPHANY_INSN_CMOV16NE, "cmov16NE", "movne", 16,
   1412     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1413   },
   1414 /* movne $rd6,$rn6 */
   1415   {
   1416     EPIPHANY_INSN_CMOVNE, "cmovNE", "movne", 32,
   1417     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1418   },
   1419 /* movgtu $rd,$rn */
   1420   {
   1421     EPIPHANY_INSN_CMOV16GTU, "cmov16GTU", "movgtu", 16,
   1422     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1423   },
   1424 /* movgtu $rd6,$rn6 */
   1425   {
   1426     EPIPHANY_INSN_CMOVGTU, "cmovGTU", "movgtu", 32,
   1427     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1428   },
   1429 /* movgteu $rd,$rn */
   1430   {
   1431     EPIPHANY_INSN_CMOV16GTEU, "cmov16GTEU", "movgteu", 16,
   1432     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1433   },
   1434 /* movgteu $rd6,$rn6 */
   1435   {
   1436     EPIPHANY_INSN_CMOVGTEU, "cmovGTEU", "movgteu", 32,
   1437     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1438   },
   1439 /* movlteu $rd,$rn */
   1440   {
   1441     EPIPHANY_INSN_CMOV16LTEU, "cmov16LTEU", "movlteu", 16,
   1442     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1443   },
   1444 /* movlteu $rd6,$rn6 */
   1445   {
   1446     EPIPHANY_INSN_CMOVLTEU, "cmovLTEU", "movlteu", 32,
   1447     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1448   },
   1449 /* movltu $rd,$rn */
   1450   {
   1451     EPIPHANY_INSN_CMOV16LTU, "cmov16LTU", "movltu", 16,
   1452     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1453   },
   1454 /* movltu $rd6,$rn6 */
   1455   {
   1456     EPIPHANY_INSN_CMOVLTU, "cmovLTU", "movltu", 32,
   1457     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1458   },
   1459 /* movgt $rd,$rn */
   1460   {
   1461     EPIPHANY_INSN_CMOV16GT, "cmov16GT", "movgt", 16,
   1462     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1463   },
   1464 /* movgt $rd6,$rn6 */
   1465   {
   1466     EPIPHANY_INSN_CMOVGT, "cmovGT", "movgt", 32,
   1467     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1468   },
   1469 /* movgte $rd,$rn */
   1470   {
   1471     EPIPHANY_INSN_CMOV16GTE, "cmov16GTE", "movgte", 16,
   1472     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1473   },
   1474 /* movgte $rd6,$rn6 */
   1475   {
   1476     EPIPHANY_INSN_CMOVGTE, "cmovGTE", "movgte", 32,
   1477     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1478   },
   1479 /* movlt $rd,$rn */
   1480   {
   1481     EPIPHANY_INSN_CMOV16LT, "cmov16LT", "movlt", 16,
   1482     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1483   },
   1484 /* movlt $rd6,$rn6 */
   1485   {
   1486     EPIPHANY_INSN_CMOVLT, "cmovLT", "movlt", 32,
   1487     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1488   },
   1489 /* movlte $rd,$rn */
   1490   {
   1491     EPIPHANY_INSN_CMOV16LTE, "cmov16LTE", "movlte", 16,
   1492     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1493   },
   1494 /* movlte $rd6,$rn6 */
   1495   {
   1496     EPIPHANY_INSN_CMOVLTE, "cmovLTE", "movlte", 32,
   1497     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1498   },
   1499 /* mov $rd,$rn */
   1500   {
   1501     EPIPHANY_INSN_CMOV16B, "cmov16B", "mov", 16,
   1502     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1503   },
   1504 /* mov $rd6,$rn6 */
   1505   {
   1506     EPIPHANY_INSN_CMOVB, "cmovB", "mov", 32,
   1507     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1508   },
   1509 /* movbeq $rd,$rn */
   1510   {
   1511     EPIPHANY_INSN_CMOV16BEQ, "cmov16BEQ", "movbeq", 16,
   1512     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1513   },
   1514 /* movbeq $rd6,$rn6 */
   1515   {
   1516     EPIPHANY_INSN_CMOVBEQ, "cmovBEQ", "movbeq", 32,
   1517     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1518   },
   1519 /* movbne $rd,$rn */
   1520   {
   1521     EPIPHANY_INSN_CMOV16BNE, "cmov16BNE", "movbne", 16,
   1522     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1523   },
   1524 /* movbne $rd6,$rn6 */
   1525   {
   1526     EPIPHANY_INSN_CMOVBNE, "cmovBNE", "movbne", 32,
   1527     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1528   },
   1529 /* movblt $rd,$rn */
   1530   {
   1531     EPIPHANY_INSN_CMOV16BLT, "cmov16BLT", "movblt", 16,
   1532     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1533   },
   1534 /* movblt $rd6,$rn6 */
   1535   {
   1536     EPIPHANY_INSN_CMOVBLT, "cmovBLT", "movblt", 32,
   1537     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1538   },
   1539 /* movblte $rd,$rn */
   1540   {
   1541     EPIPHANY_INSN_CMOV16BLTE, "cmov16BLTE", "movblte", 16,
   1542     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1543   },
   1544 /* movblte $rd6,$rn6 */
   1545   {
   1546     EPIPHANY_INSN_CMOVBLTE, "cmovBLTE", "movblte", 32,
   1547     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1548   },
   1549 /* movts $sn,$rd */
   1550   {
   1551     EPIPHANY_INSN_MOVTS16, "movts16", "movts", 16,
   1552     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1553   },
   1554 /* movts $sn6,$rd6 */
   1555   {
   1556     EPIPHANY_INSN_MOVTS6, "movts6", "movts", 32,
   1557     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1558   },
   1559 /* movts $sndma,$rd6 */
   1560   {
   1561     EPIPHANY_INSN_MOVTSDMA, "movtsdma", "movts", 32,
   1562     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1563   },
   1564 /* movts $snmem,$rd6 */
   1565   {
   1566     EPIPHANY_INSN_MOVTSMEM, "movtsmem", "movts", 32,
   1567     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1568   },
   1569 /* movts $snmesh,$rd6 */
   1570   {
   1571     EPIPHANY_INSN_MOVTSMESH, "movtsmesh", "movts", 32,
   1572     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1573   },
   1574 /* movfs $rd,$sn */
   1575   {
   1576     EPIPHANY_INSN_MOVFS16, "movfs16", "movfs", 16,
   1577     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1578   },
   1579 /* movfs $rd6,$sn6 */
   1580   {
   1581     EPIPHANY_INSN_MOVFS6, "movfs6", "movfs", 32,
   1582     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1583   },
   1584 /* movfs $rd6,$sndma */
   1585   {
   1586     EPIPHANY_INSN_MOVFSDMA, "movfsdma", "movfs", 32,
   1587     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1588   },
   1589 /* movfs $rd6,$snmem */
   1590   {
   1591     EPIPHANY_INSN_MOVFSMEM, "movfsmem", "movfs", 32,
   1592     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1593   },
   1594 /* movfs $rd6,$snmesh */
   1595   {
   1596     EPIPHANY_INSN_MOVFSMESH, "movfsmesh", "movfs", 32,
   1597     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1598   },
   1599 /* nop */
   1600   {
   1601     EPIPHANY_INSN_NOP, "nop", "nop", 16,
   1602     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1603   },
   1604 /* snop */
   1605   {
   1606     EPIPHANY_INSN_SNOP, "snop", "snop", 16,
   1607     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1608   },
   1609 /* unimpl */
   1610   {
   1611     EPIPHANY_INSN_UNIMPL, "unimpl", "unimpl", 32,
   1612     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1613   },
   1614 /* idle */
   1615   {
   1616     EPIPHANY_INSN_IDLE, "idle", "idle", 16,
   1617     { 0, { { { (1<<MACH_BASE), 0 } } } }
   1618   },
   1619 /* bkpt */
   1620   {
   1621     EPIPHANY_INSN_BKPT, "bkpt", "bkpt", 16,
   1622     { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1623   },
   1624 /* mbkpt */
   1625   {
   1626     EPIPHANY_INSN_MBKPT, "mbkpt", "mbkpt", 16,
   1627     { 0|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
   1628   },
   1629 /* rti */
   1630   {
   1631     EPIPHANY_INSN_RTI, "rti", "rti", 16,
   1632     { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
   1633   },
   1634 /* wand */
   1635   {
   1636     EPIPHANY_INSN_WAND, "wand", "wand", 16,
   1637     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1638   },
   1639 /* sync */
   1640   {
   1641     EPIPHANY_INSN_SYNC, "sync", "sync", 16,
   1642     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1643   },
   1644 /* gie */
   1645   {
   1646     EPIPHANY_INSN_GIEN, "gien", "gie", 16,
   1647     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1648   },
   1649 /* gid */
   1650   {
   1651     EPIPHANY_INSN_GIDIS, "gidis", "gid", 16,
   1652     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1653   },
   1654 /* swi $swi_num */
   1655   {
   1656     EPIPHANY_INSN_SWI_NUM, "swi_num", "swi", 16,
   1657     { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1658   },
   1659 /* swi */
   1660   {
   1661     -1, "swi", "swi", 16,
   1662     { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(ALIAS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1663   },
   1664 /* trap $trapnum6 */
   1665   {
   1666     EPIPHANY_INSN_TRAP16, "trap16", "trap", 16,
   1667     { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
   1668   },
   1669 /* add $rd,$rn,$rm */
   1670   {
   1671     EPIPHANY_INSN_ADD16, "add16", "add", 16,
   1672     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1673   },
   1674 /* add $rd6,$rn6,$rm6 */
   1675   {
   1676     EPIPHANY_INSN_ADD, "add", "add", 32,
   1677     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1678   },
   1679 /* sub $rd,$rn,$rm */
   1680   {
   1681     EPIPHANY_INSN_SUB16, "sub16", "sub", 16,
   1682     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1683   },
   1684 /* sub $rd6,$rn6,$rm6 */
   1685   {
   1686     EPIPHANY_INSN_SUB, "sub", "sub", 32,
   1687     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1688   },
   1689 /* and $rd,$rn,$rm */
   1690   {
   1691     EPIPHANY_INSN_AND16, "and16", "and", 16,
   1692     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1693   },
   1694 /* and $rd6,$rn6,$rm6 */
   1695   {
   1696     EPIPHANY_INSN_AND, "and", "and", 32,
   1697     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1698   },
   1699 /* orr $rd,$rn,$rm */
   1700   {
   1701     EPIPHANY_INSN_ORR16, "orr16", "orr", 16,
   1702     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1703   },
   1704 /* orr $rd6,$rn6,$rm6 */
   1705   {
   1706     EPIPHANY_INSN_ORR, "orr", "orr", 32,
   1707     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1708   },
   1709 /* eor $rd,$rn,$rm */
   1710   {
   1711     EPIPHANY_INSN_EOR16, "eor16", "eor", 16,
   1712     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1713   },
   1714 /* eor $rd6,$rn6,$rm6 */
   1715   {
   1716     EPIPHANY_INSN_EOR, "eor", "eor", 32,
   1717     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1718   },
   1719 /* add.s $rd,$rn,$simm3 */
   1720   {
   1721     EPIPHANY_INSN_ADDI16, "addi16", "add.s", 16,
   1722     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1723   },
   1724 /* add.l $rd6,$rn6,$simm11 */
   1725   {
   1726     EPIPHANY_INSN_ADDI, "addi", "add.l", 32,
   1727     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1728   },
   1729 /* sub.s $rd,$rn,$simm3 */
   1730   {
   1731     EPIPHANY_INSN_SUBI16, "subi16", "sub.s", 16,
   1732     { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1733   },
   1734 /* sub.l $rd6,$rn6,$simm11 */
   1735   {
   1736     EPIPHANY_INSN_SUBI, "subi", "sub.l", 32,
   1737     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1738   },
   1739 /* asr $rd,$rn,$rm */
   1740   {
   1741     EPIPHANY_INSN_ASR16, "asr16", "asr", 16,
   1742     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1743   },
   1744 /* asr $rd6,$rn6,$rm6 */
   1745   {
   1746     EPIPHANY_INSN_ASR, "asr", "asr", 32,
   1747     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1748   },
   1749 /* lsr $rd,$rn,$rm */
   1750   {
   1751     EPIPHANY_INSN_LSR16, "lsr16", "lsr", 16,
   1752     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1753   },
   1754 /* lsr $rd6,$rn6,$rm6 */
   1755   {
   1756     EPIPHANY_INSN_LSR, "lsr", "lsr", 32,
   1757     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1758   },
   1759 /* lsl $rd,$rn,$rm */
   1760   {
   1761     EPIPHANY_INSN_LSL16, "lsl16", "lsl", 16,
   1762     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1763   },
   1764 /* lsl $rd6,$rn6,$rm6 */
   1765   {
   1766     EPIPHANY_INSN_LSL, "lsl", "lsl", 32,
   1767     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1768   },
   1769 /* lsr $rd,$rn,$shift */
   1770   {
   1771     EPIPHANY_INSN_LSRI16, "lsri16", "lsr", 16,
   1772     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1773   },
   1774 /* lsr $rd6,$rn6,$shift */
   1775   {
   1776     EPIPHANY_INSN_LSRI32, "lsri32", "lsr", 32,
   1777     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1778   },
   1779 /* lsl $rd,$rn,$shift */
   1780   {
   1781     EPIPHANY_INSN_LSLI16, "lsli16", "lsl", 16,
   1782     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1783   },
   1784 /* lsl $rd6,$rn6,$shift */
   1785   {
   1786     EPIPHANY_INSN_LSLI32, "lsli32", "lsl", 32,
   1787     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1788   },
   1789 /* asr $rd,$rn,$shift */
   1790   {
   1791     EPIPHANY_INSN_ASRI16, "asri16", "asr", 16,
   1792     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1793   },
   1794 /* asr $rd6,$rn6,$shift */
   1795   {
   1796     EPIPHANY_INSN_ASRI32, "asri32", "asr", 32,
   1797     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1798   },
   1799 /* bitr $rd,$rn */
   1800   {
   1801     EPIPHANY_INSN_BITR16, "bitr16", "bitr", 16,
   1802     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1803   },
   1804 /* bitr $rd6,$rn6 */
   1805   {
   1806     EPIPHANY_INSN_BITR, "bitr", "bitr", 32,
   1807     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1808   },
   1809 /* fext $rd6,$rn6,$rm6 */
   1810   {
   1811     EPIPHANY_INSN_FEXT, "fext", "fext", 32,
   1812     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1813   },
   1814 /* fdep $rd6,$rn6,$rm6 */
   1815   {
   1816     EPIPHANY_INSN_FDEP, "fdep", "fdep", 32,
   1817     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1818   },
   1819 /* lfsr $rd6,$rn6,$rm6 */
   1820   {
   1821     EPIPHANY_INSN_LFSR, "lfsr", "lfsr", 32,
   1822     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1823   },
   1824 /* mov.b $rd,$imm8 */
   1825   {
   1826     EPIPHANY_INSN_MOV8, "mov8", "mov.b", 16,
   1827     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1828   },
   1829 /* mov.l $rd6,$imm16 */
   1830   {
   1831     EPIPHANY_INSN_MOV16, "mov16", "mov.l", 32,
   1832     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1833   },
   1834 /* movt $rd6,$imm16 */
   1835   {
   1836     EPIPHANY_INSN_MOVT, "movt", "movt", 32,
   1837     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1838   },
   1839 /* fadd $rd,$rn,$rm */
   1840   {
   1841     EPIPHANY_INSN_F_ADDF16, "f_addf16", "fadd", 16,
   1842     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1843   },
   1844 /* fadd $rd6,$rn6,$rm6 */
   1845   {
   1846     EPIPHANY_INSN_F_ADDF32, "f_addf32", "fadd", 32,
   1847     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1848   },
   1849 /* fsub $rd,$rn,$rm */
   1850   {
   1851     EPIPHANY_INSN_F_SUBF16, "f_subf16", "fsub", 16,
   1852     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1853   },
   1854 /* fsub $rd6,$rn6,$rm6 */
   1855   {
   1856     EPIPHANY_INSN_F_SUBF32, "f_subf32", "fsub", 32,
   1857     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1858   },
   1859 /* fmul $rd,$rn,$rm */
   1860   {
   1861     EPIPHANY_INSN_F_MULF16, "f_mulf16", "fmul", 16,
   1862     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1863   },
   1864 /* fmul $rd6,$rn6,$rm6 */
   1865   {
   1866     EPIPHANY_INSN_F_MULF32, "f_mulf32", "fmul", 32,
   1867     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1868   },
   1869 /* fmadd $rd,$rn,$rm */
   1870   {
   1871     EPIPHANY_INSN_F_MADDF16, "f_maddf16", "fmadd", 16,
   1872     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1873   },
   1874 /* fmadd $rd6,$rn6,$rm6 */
   1875   {
   1876     EPIPHANY_INSN_F_MADDF32, "f_maddf32", "fmadd", 32,
   1877     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1878   },
   1879 /* fmsub $rd,$rn,$rm */
   1880   {
   1881     EPIPHANY_INSN_F_MSUBF16, "f_msubf16", "fmsub", 16,
   1882     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1883   },
   1884 /* fmsub $rd6,$rn6,$rm6 */
   1885   {
   1886     EPIPHANY_INSN_F_MSUBF32, "f_msubf32", "fmsub", 32,
   1887     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1888   },
   1889 /* fabs rd,rn */
   1890   {
   1891     EPIPHANY_INSN_F_ABSF16, "f_absf16", "fabs", 16,
   1892     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1893   },
   1894 /* fabs $rd6,$rn6 */
   1895   {
   1896     EPIPHANY_INSN_F_ABSF32, "f_absf32", "fabs", 32,
   1897     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1898   },
   1899 /* float $rd,$rn */
   1900   {
   1901     EPIPHANY_INSN_F_LOATF16, "f_loatf16", "float", 16,
   1902     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1903   },
   1904 /* float $rd6,$rn6 */
   1905   {
   1906     EPIPHANY_INSN_F_LOATF32, "f_loatf32", "float", 32,
   1907     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1908   },
   1909 /* fix $rd,$rn */
   1910   {
   1911     EPIPHANY_INSN_F_IXF16, "f_ixf16", "fix", 16,
   1912     { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1913   },
   1914 /* fix $rd6,$rn6 */
   1915   {
   1916     EPIPHANY_INSN_F_IXF32, "f_ixf32", "fix", 32,
   1917     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1918   },
   1919 /* frecip $frd6,$frn6 */
   1920   {
   1921     EPIPHANY_INSN_F_RECIPF32, "f_recipf32", "frecip", 32,
   1922     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1923   },
   1924 /* fsqrt $frd6,$frn6 */
   1925   {
   1926     EPIPHANY_INSN_F_SQRTF32, "f_sqrtf32", "fsqrt", 32,
   1927     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
   1928   },
   1929 };
   1930 
   1931 #undef OP
   1932 #undef A
   1933 
   1934 /* Initialize anything needed to be done once, before any cpu_open call.  */
   1935 
   1936 static void
   1937 init_tables (void)
   1938 {
   1939 }
   1940 
   1941 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
   1942 static void build_hw_table      (CGEN_CPU_TABLE *);
   1943 static void build_ifield_table  (CGEN_CPU_TABLE *);
   1944 static void build_operand_table (CGEN_CPU_TABLE *);
   1945 static void build_insn_table    (CGEN_CPU_TABLE *);
   1946 static void epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *);
   1947 
   1948 /* Subroutine of epiphany_cgen_cpu_open to look up a mach via its bfd name.  */
   1949 
   1950 static const CGEN_MACH *
   1951 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
   1952 {
   1953   while (table->name)
   1954     {
   1955       if (strcmp (name, table->bfd_name) == 0)
   1956 	return table;
   1957       ++table;
   1958     }
   1959   abort ();
   1960 }
   1961 
   1962 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table.  */
   1963 
   1964 static void
   1965 build_hw_table (CGEN_CPU_TABLE *cd)
   1966 {
   1967   int i;
   1968   int machs = cd->machs;
   1969   const CGEN_HW_ENTRY *init = & epiphany_cgen_hw_table[0];
   1970   /* MAX_HW is only an upper bound on the number of selected entries.
   1971      However each entry is indexed by it's enum so there can be holes in
   1972      the table.  */
   1973   const CGEN_HW_ENTRY **selected =
   1974     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
   1975 
   1976   cd->hw_table.init_entries = init;
   1977   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
   1978   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
   1979   /* ??? For now we just use machs to determine which ones we want.  */
   1980   for (i = 0; init[i].name != NULL; ++i)
   1981     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
   1982 	& machs)
   1983       selected[init[i].type] = &init[i];
   1984   cd->hw_table.entries = selected;
   1985   cd->hw_table.num_entries = MAX_HW;
   1986 }
   1987 
   1988 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table.  */
   1989 
   1990 static void
   1991 build_ifield_table (CGEN_CPU_TABLE *cd)
   1992 {
   1993   cd->ifld_table = & epiphany_cgen_ifld_table[0];
   1994 }
   1995 
   1996 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table.  */
   1997 
   1998 static void
   1999 build_operand_table (CGEN_CPU_TABLE *cd)
   2000 {
   2001   int i;
   2002   int machs = cd->machs;
   2003   const CGEN_OPERAND *init = & epiphany_cgen_operand_table[0];
   2004   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
   2005      However each entry is indexed by it's enum so there can be holes in
   2006      the table.  */
   2007   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
   2008 
   2009   cd->operand_table.init_entries = init;
   2010   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
   2011   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
   2012   /* ??? For now we just use mach to determine which ones we want.  */
   2013   for (i = 0; init[i].name != NULL; ++i)
   2014     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
   2015 	& machs)
   2016       selected[init[i].type] = &init[i];
   2017   cd->operand_table.entries = selected;
   2018   cd->operand_table.num_entries = MAX_OPERANDS;
   2019 }
   2020 
   2021 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table.
   2022    ??? This could leave out insns not supported by the specified mach/isa,
   2023    but that would cause errors like "foo only supported by bar" to become
   2024    "unknown insn", so for now we include all insns and require the app to
   2025    do the checking later.
   2026    ??? On the other hand, parsing of such insns may require their hardware or
   2027    operand elements to be in the table [which they mightn't be].  */
   2028 
   2029 static void
   2030 build_insn_table (CGEN_CPU_TABLE *cd)
   2031 {
   2032   int i;
   2033   const CGEN_IBASE *ib = & epiphany_cgen_insn_table[0];
   2034   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
   2035 
   2036   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
   2037   for (i = 0; i < MAX_INSNS; ++i)
   2038     insns[i].base = &ib[i];
   2039   cd->insn_table.init_entries = insns;
   2040   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
   2041   cd->insn_table.num_init_entries = MAX_INSNS;
   2042 }
   2043 
   2044 /* Subroutine of epiphany_cgen_cpu_open to rebuild the tables.  */
   2045 
   2046 static void
   2047 epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
   2048 {
   2049   int i;
   2050   CGEN_BITSET *isas = cd->isas;
   2051   unsigned int machs = cd->machs;
   2052 
   2053   cd->int_insn_p = CGEN_INT_INSN_P;
   2054 
   2055   /* Data derived from the isa spec.  */
   2056 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
   2057   cd->default_insn_bitsize = UNSET;
   2058   cd->base_insn_bitsize = UNSET;
   2059   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
   2060   cd->max_insn_bitsize = 0;
   2061   for (i = 0; i < MAX_ISAS; ++i)
   2062     if (cgen_bitset_contains (isas, i))
   2063       {
   2064 	const CGEN_ISA *isa = & epiphany_cgen_isa_table[i];
   2065 
   2066 	/* Default insn sizes of all selected isas must be
   2067 	   equal or we set the result to 0, meaning "unknown".  */
   2068 	if (cd->default_insn_bitsize == UNSET)
   2069 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
   2070 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
   2071 	  ; /* This is ok.  */
   2072 	else
   2073 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
   2074 
   2075 	/* Base insn sizes of all selected isas must be equal
   2076 	   or we set the result to 0, meaning "unknown".  */
   2077 	if (cd->base_insn_bitsize == UNSET)
   2078 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
   2079 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
   2080 	  ; /* This is ok.  */
   2081 	else
   2082 	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
   2083 
   2084 	/* Set min,max insn sizes.  */
   2085 	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
   2086 	  cd->min_insn_bitsize = isa->min_insn_bitsize;
   2087 	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
   2088 	  cd->max_insn_bitsize = isa->max_insn_bitsize;
   2089       }
   2090 
   2091   /* Data derived from the mach spec.  */
   2092   for (i = 0; i < MAX_MACHS; ++i)
   2093     if (((1 << i) & machs) != 0)
   2094       {
   2095 	const CGEN_MACH *mach = & epiphany_cgen_mach_table[i];
   2096 
   2097 	if (mach->insn_chunk_bitsize != 0)
   2098 	{
   2099 	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
   2100 	    {
   2101 	      fprintf (stderr, "epiphany_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
   2102 		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
   2103 	      abort ();
   2104 	    }
   2105 
   2106  	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
   2107 	}
   2108       }
   2109 
   2110   /* Determine which hw elements are used by MACH.  */
   2111   build_hw_table (cd);
   2112 
   2113   /* Build the ifield table.  */
   2114   build_ifield_table (cd);
   2115 
   2116   /* Determine which operands are used by MACH/ISA.  */
   2117   build_operand_table (cd);
   2118 
   2119   /* Build the instruction table.  */
   2120   build_insn_table (cd);
   2121 }
   2122 
   2123 /* Initialize a cpu table and return a descriptor.
   2124    It's much like opening a file, and must be the first function called.
   2125    The arguments are a set of (type/value) pairs, terminated with
   2126    CGEN_CPU_OPEN_END.
   2127 
   2128    Currently supported values:
   2129    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
   2130    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
   2131    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
   2132    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
   2133    CGEN_CPU_OPEN_END:     terminates arguments
   2134 
   2135    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
   2136    precluded.  */
   2137 
   2138 CGEN_CPU_DESC
   2139 epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
   2140 {
   2141   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
   2142   static int init_p;
   2143   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
   2144   unsigned int machs = 0; /* 0 = "unspecified" */
   2145   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
   2146   va_list ap;
   2147 
   2148   if (! init_p)
   2149     {
   2150       init_tables ();
   2151       init_p = 1;
   2152     }
   2153 
   2154   memset (cd, 0, sizeof (*cd));
   2155 
   2156   va_start (ap, arg_type);
   2157   while (arg_type != CGEN_CPU_OPEN_END)
   2158     {
   2159       switch (arg_type)
   2160 	{
   2161 	case CGEN_CPU_OPEN_ISAS :
   2162 	  isas = va_arg (ap, CGEN_BITSET *);
   2163 	  break;
   2164 	case CGEN_CPU_OPEN_MACHS :
   2165 	  machs = va_arg (ap, unsigned int);
   2166 	  break;
   2167 	case CGEN_CPU_OPEN_BFDMACH :
   2168 	  {
   2169 	    const char *name = va_arg (ap, const char *);
   2170 	    const CGEN_MACH *mach =
   2171 	      lookup_mach_via_bfd_name (epiphany_cgen_mach_table, name);
   2172 
   2173 	    machs |= 1 << mach->num;
   2174 	    break;
   2175 	  }
   2176 	case CGEN_CPU_OPEN_ENDIAN :
   2177 	  endian = va_arg (ap, enum cgen_endian);
   2178 	  break;
   2179 	default :
   2180 	  fprintf (stderr, "epiphany_cgen_cpu_open: unsupported argument `%d'\n",
   2181 		   arg_type);
   2182 	  abort (); /* ??? return NULL? */
   2183 	}
   2184       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
   2185     }
   2186   va_end (ap);
   2187 
   2188   /* Mach unspecified means "all".  */
   2189   if (machs == 0)
   2190     machs = (1 << MAX_MACHS) - 1;
   2191   /* Base mach is always selected.  */
   2192   machs |= 1;
   2193   if (endian == CGEN_ENDIAN_UNKNOWN)
   2194     {
   2195       /* ??? If target has only one, could have a default.  */
   2196       fprintf (stderr, "epiphany_cgen_cpu_open: no endianness specified\n");
   2197       abort ();
   2198     }
   2199 
   2200   cd->isas = cgen_bitset_copy (isas);
   2201   cd->machs = machs;
   2202   cd->endian = endian;
   2203   /* FIXME: for the sparc case we can determine insn-endianness statically.
   2204      The worry here is where both data and insn endian can be independently
   2205      chosen, in which case this function will need another argument.
   2206      Actually, will want to allow for more arguments in the future anyway.  */
   2207   cd->insn_endian = endian;
   2208 
   2209   /* Table (re)builder.  */
   2210   cd->rebuild_tables = epiphany_cgen_rebuild_tables;
   2211   epiphany_cgen_rebuild_tables (cd);
   2212 
   2213   /* Default to not allowing signed overflow.  */
   2214   cd->signed_overflow_ok_p = 0;
   2215 
   2216   return (CGEN_CPU_DESC) cd;
   2217 }
   2218 
   2219 /* Cover fn to epiphany_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
   2220    MACH_NAME is the bfd name of the mach.  */
   2221 
   2222 CGEN_CPU_DESC
   2223 epiphany_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
   2224 {
   2225   return epiphany_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
   2226 			       CGEN_CPU_OPEN_ENDIAN, endian,
   2227 			       CGEN_CPU_OPEN_END);
   2228 }
   2229 
   2230 /* Close a cpu table.
   2231    ??? This can live in a machine independent file, but there's currently
   2232    no place to put this file (there's no libcgen).  libopcodes is the wrong
   2233    place as some simulator ports use this but they don't use libopcodes.  */
   2234 
   2235 void
   2236 epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
   2237 {
   2238   unsigned int i;
   2239   const CGEN_INSN *insns;
   2240 
   2241   if (cd->macro_insn_table.init_entries)
   2242     {
   2243       insns = cd->macro_insn_table.init_entries;
   2244       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
   2245 	if (CGEN_INSN_RX ((insns)))
   2246 	  regfree (CGEN_INSN_RX (insns));
   2247     }
   2248 
   2249   if (cd->insn_table.init_entries)
   2250     {
   2251       insns = cd->insn_table.init_entries;
   2252       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
   2253 	if (CGEN_INSN_RX (insns))
   2254 	  regfree (CGEN_INSN_RX (insns));
   2255     }
   2256 
   2257   if (cd->macro_insn_table.init_entries)
   2258     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
   2259 
   2260   if (cd->insn_table.init_entries)
   2261     free ((CGEN_INSN *) cd->insn_table.init_entries);
   2262 
   2263   if (cd->hw_table.entries)
   2264     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
   2265 
   2266   if (cd->operand_table.entries)
   2267     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
   2268 
   2269   free (cd);
   2270 }
   2271 
   2272