| /external/llvm/lib/CodeGen/ |
| PatchableFunction.cpp | 72 auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(),
78 MIB.addOperand(MO);
|
| XRayInstrumentation.cpp | 76 auto MIB = BuildMI(MBB, T, T.getDebugLoc(),
80 MIB.addOperand(MO);
|
| ImplicitNullChecks.cpp | 502 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_LOAD_OP), DefReg)
507 MIB.addOperand(MO);
509 MIB.setMemRefs(LoadMI->memoperands_begin(), LoadMI->memoperands_end());
511 return MIB;
|
| MachineInstrBundle.cpp | 123 MachineInstrBuilder MIB =
125 Bundle.prepend(MIB);
204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
213 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 122 MachineInstrBuilder MIB;
124 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
129 MIB.addMemOperand(MMO);
130 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg);
131 MIB.addReg(Reg, RegState::Kill).addImm(0);
132 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
133 AddDefaultPred(MIB);
|
| Thumb2InstrInfo.cpp | 156 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
157 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
158 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
159 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
160 AddDefaultPred(MIB);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
202 AddDefaultPred(MIB);
[all...] |
| ThumbRegisterInfo.cpp | 164 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
166 MIB = AddDefaultT1CC(MIB);
168 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
170 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
171 AddDefaultPred(MIB);
304 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
306 MIB = AddDefaultT1CC(MIB);
307 MIB.addReg(BaseReg, RegState::Kill)
[all...] |
| MLxExpansionPass.cpp | 293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
297 MIB.addImm(LaneImm);
298 MIB.addImm(Pred).addReg(PredReg);
300 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
305 MIB.addReg(TmpReg, getKillRegState(true))
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
310 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb1FrameLowering.cpp | 452 MachineInstrBuilder MIB =
458 MIB.addOperand(MO);
459 MIB.addReg(ARM::PC, RegState::Define);
534 MachineInstrBuilder MIB =
541 MIB.addOperand(MO);
547 MBB.erase(MIB.getInstr());
582 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
583 AddDefaultPred(MIB);
601 MIB.addReg(Reg, getKillRegState(isKill));
603 MIB.setMIFlags(MachineInstr::FrameSetup)
[all...] |
| Thumb2ITBlockPass.cpp | 201 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
209 MachineBasicBlock::iterator InsertPos = MIB.getInstr();
258 MIB.addImm(Mask);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 112 MachineInstrBuilder MIB =
118 MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 172 MachineInstrBuilder MIB;
190 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));
193 MIB.addOperand(MII->getOperand(i));
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 102 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
106 MIB.addReg(Cond[i].getReg());
108 MIB.addImm(Cond[i].getImm());
112 MIB.addMBB(TBB);
399 MachineInstrBuilder MIB;
430 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
440 MIB->RemoveOperand(0);
443 MIB.addOperand(I->getOperand(J));
446 MIB.addImm(0);
451 MIB.addOperand(I->getOperand(0))
[all...] |
| Mips16InstrInfo.cpp | 82 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
85 MIB.addReg(DestReg, RegState::Define);
88 MIB.addReg(SrcReg, getKillRegState(KillSrc));
169 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
183 MIB.addReg(Reg, Flags);
202 MachineInstrBuilder MIB;
204 MIB = BuildMI(MBB, I, DL, get(Opc));
206 addSaveRestoreRegs(MIB, CSI);
208 MIB.addReg(Mips::S2);
210 MIB.addImm(FrameSize)
[all...] |
| MipsLongBranch.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
235 MIB.addReg(MO.getReg());
238 MIB.addMBB(MBBOpnd);
245 MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
|
| /external/llvm/lib/Target/X86/ |
| X86ExpandPseudo.cpp | 112 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
114 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
118 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
125 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
127 MIB.addOperand(MBBI->getOperand(i));
171 MachineInstrBuilder MIB;
173 MIB = BuildMI(MBB, MBBI, DL,
176 MIB = BuildMI(MBB, MBBI, DL,
187 MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
190 MIB.addOperand(MBBI->getOperand(I))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 302 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
303 AddDefaultPred(MIB);
321 MIB.addReg(Reg, getKillRegState(isKill));
323 MIB.setMIFlags(MachineInstr::FrameSetup);
341 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
342 AddDefaultPred(MIB);
352 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
355 MIB.addReg(Reg, getDefRegState(true));
361 MBB.insert(MI, &*MIB);
363 MF.DeleteMachineInstr(MIB);
[all...] |
| Thumb1RegisterInfo.cpp | 129 MachineInstrBuilder MIB =
132 MIB = AddDefaultT1CC(MIB);
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
137 AddDefaultPred(MIB);
241 const MachineInstrBuilder MIB =
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
262 MIB = AddDefaultT1CC(MIB)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 360 MachineInstrBuilder MIB;
368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
374 MIB = BuildMI(&MBB, DL, get(SPU::BR));
375 MIB.addMBB(TBB);
378 DEBUG((*MIB).dump());
382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
383 MIB.addSym(branchLabel);
384 MIB.addMBB(TBB);
388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
389 MIB.addReg(Cond[1].getReg()).addMBB(TBB)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 153 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
156 MIB.addReg(DestReg, RegState::Define);
159 MIB.addReg(ZeroReg);
162 MIB.addReg(SrcReg, getKillRegState(KillSrc));
219 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
221 return &*MIB;
361 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
364 MIB.addReg(Cond[i].getReg());
366 MIB.addMBB(TBB);
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 264 MachineInstrBuilder MIB =
269 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
271 MIB.addReg(0);
272 MIB.addReg(LowReg, RegState::Kill);
274 MIB.addReg(HighReg, RegState::Kill);
282 MIB.addReg(Reg, RegState::ImplicitKill);
329 MachineInstrBuilder MIB =
333 MIB.addReg(LowReg, RegState::Define);
335 MIB.addReg(HighReg, RegState::Define);
337 MIB.addReg(hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE))
395 return &*MIB;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 284 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
287 DEBUG(dbgs() << " adding copy: " << *MIB);
289 return MIB;
|
| AArch64BranchRelaxation.cpp | 440 MachineInstrBuilder MIB = BuildMI(
445 MIB.addOperand(MI->getOperand(1));
447 invertBccCondition(MIB);
448 MIB.addMBB(NextBB);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 379 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
381 MIB.addReg(SP::G0);
382 MIB.addReg(Src);
383 MovMI = MIB.getInstr();
|
