| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 80 unsigned ResultReg;
96 ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {}
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFastISel.cpp | 516 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
518 TII.get(WebAssembly::COPY), ResultReg)
520 return ResultReg;
528 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ?
534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
536 return ResultReg;
544 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ?
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
552 return ResultReg;
606 unsigned ResultReg = createResultReg(RC)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 351 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
354 if (ResultReg == 0) return false;
357 UpdateValueMap(I, ResultReg);
380 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
382 if (ResultReg == 0) return false;
385 UpdateValueMap(I, ResultReg);
391 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
393 if (ResultReg != 0) {
395 UpdateValueMap(I, ResultReg);
408 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT()
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 414 unsigned ResultReg =
417 if (!ResultReg)
421 updateValueMap(I, ResultReg);
448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
450 if (!ResultReg)
454 updateValueMap(I, ResultReg);
460 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
462 if (ResultReg) {
464 updateValueMap(I, ResultReg);
475 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT()
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| AArch64FastISel.cpp | 323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
325 ResultReg)
329 return ResultReg;
346 unsigned ResultReg = createResultReg(RC);
348 ResultReg).addReg(ZeroReg, getKillRegState(true));
349 return ResultReg;
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
385 TII.get(TargetOpcode::COPY), ResultReg)
388 return ResultReg;
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 133 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
279 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
280 if (!ResultReg)
283 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
284 return ResultReg;
298 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
300 ResultReg)
303 return ResultReg;
319 unsigned ResultReg = createResultReg(RC);
323 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 157 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
443 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
445 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
446 Addr.Base.Reg = ResultReg;
462 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
468 // If ResultReg is given, it determines the register class of the load.
476 (ResultReg ? MRI.getRegClass(ResultReg) :
524 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | 176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
190 unsigned &ResultReg);
280 unsigned ResultReg = createResultReg(RC);
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
284 return ResultReg;
290 unsigned ResultReg = createResultReg(RC);
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
300 TII.get(TargetOpcode::COPY), ResultReg)
303 return ResultReg;
310 unsigned ResultReg = createResultReg(RC)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FastISel.cpp | 87 unsigned &ResultReg);
177 unsigned &ResultReg) {
224 ResultReg = createResultReg(RC);
226 DL, TII.get(Opc), ResultReg), AM);
312 unsigned &ResultReg) {
317 ResultReg = RR;
811 unsigned ResultReg = 0;
812 if (X86FastEmitLoad(VT, AM, ResultReg)) {
813 UpdateValueMap(I, ResultReg);
896 unsigned ResultReg = createResultReg(&X86::GR8RegClass)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 165 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
281 unsigned ResultReg = createResultReg(RC);
289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
294 TII.get(TargetOpcode::COPY), ResultReg)
297 return ResultReg;
304 unsigned ResultReg = createResultReg(RC);
314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
322 TII.get(TargetOpcode::COPY), ResultReg)
325 return ResultReg;
332 unsigned ResultReg = createResultReg(RC)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 89 unsigned &ResultReg, unsigned Alignment = 1);
98 unsigned &ResultReg);
349 MachineMemOperand *MMO, unsigned &ResultReg,
488 ResultReg = createResultReg(RC);
490 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
697 unsigned &ResultReg) {
703 ResultReg = RR;
[all...] |
