| /external/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.cpp | 570 unsigned TmpReg = MI.getOperand(0).getReg();
574 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
577 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
581 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
586 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
|
| MLxExpansionPass.cpp | 290 unsigned TmpReg = MRI->createVirtualRegister(
293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
305 MIB.addReg(TmpReg, getKillRegState(true))
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 227 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC);
229 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), TmpReg)
232 MI.getOperand(I).setReg(TmpReg);
|
| SIRegisterInfo.cpp | 518 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
545 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
567 .addReg(TmpReg, RegState::Kill) // src
587 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
615 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
623 .addReg(TmpReg, RegState::Kill)
668 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
670 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
672 FIOp.ChangeToRegister(TmpReg, false, false, true);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 223 unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI));
225 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID1, TmpReg)
237 MIB.addReg(TmpReg, getKillRegState(true))
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 289 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
302 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
304 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
305 .addReg(TmpReg, RegState::Kill)
310 .addReg(TmpReg);
|
| PPCFrameLowering.cpp | 664 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
674 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
676 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
677 .addReg(TmpReg, RegState::Kill)
682 .addReg(TmpReg);
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 590 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
599 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
604 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
605 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
|
| MipsFastISel.cpp | 333 unsigned TmpReg = createResultReg(RC);
334 emitInst(Mips::LUi, TmpReg).addImm(Hi);
335 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 338 unsigned TmpReg = FromReg;
340 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
344 TmpReg = Def->getOperand(1).getReg();
346 if (TmpReg == ToReg)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCFrameLowering.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 379 unsigned TmpReg = createResultReg(RC);
380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
386 .addReg(TmpReg, getKillRegState(true));
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale;
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
385 BaseReg = TmpReg;
388 IndexReg = TmpReg;
422 BaseReg = TmpReg;
425 IndexReg = TmpReg;
455 TmpReg = Reg;
512 IndexReg = TmpReg;
601 BaseReg = TmpReg;
604 IndexReg = TmpReg;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
