1 /****************************************************************************** 2 * 3 * Copyright (C) 1999-2012 Broadcom Corporation 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 19 /****************************************************************************** 20 * 21 * This file contains function of the HCIC unit to format and send HCI 22 * commands. 23 * 24 ******************************************************************************/ 25 26 #include "bt_common.h" 27 #include "bt_target.h" 28 #include "btu.h" 29 #include "hcidefs.h" 30 #include "hcimsgs.h" 31 32 #include <stddef.h> 33 #include <string.h> 34 35 #include "btm_int.h" /* Included for UIPC_* macro definitions */ 36 37 void btsnd_hcic_inquiry(const LAP inq_lap, uint8_t duration, 38 uint8_t response_cnt) { 39 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 40 uint8_t* pp = (uint8_t*)(p + 1); 41 42 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_INQUIRY; 43 p->offset = 0; 44 45 UINT16_TO_STREAM(pp, HCI_INQUIRY); 46 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_INQUIRY); 47 48 LAP_TO_STREAM(pp, inq_lap); 49 UINT8_TO_STREAM(pp, duration); 50 UINT8_TO_STREAM(pp, response_cnt); 51 52 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 53 } 54 55 void btsnd_hcic_inq_cancel(void) { 56 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 57 uint8_t* pp = (uint8_t*)(p + 1); 58 59 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_INQ_CANCEL; 60 p->offset = 0; 61 UINT16_TO_STREAM(pp, HCI_INQUIRY_CANCEL); 62 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_INQ_CANCEL); 63 64 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 65 } 66 67 void btsnd_hcic_per_inq_mode(uint16_t max_period, uint16_t min_period, 68 const LAP inq_lap, uint8_t duration, 69 uint8_t response_cnt) { 70 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 71 uint8_t* pp = (uint8_t*)(p + 1); 72 73 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PER_INQ_MODE; 74 p->offset = 0; 75 76 UINT16_TO_STREAM(pp, HCI_PERIODIC_INQUIRY_MODE); 77 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PER_INQ_MODE); 78 79 UINT16_TO_STREAM(pp, max_period); 80 UINT16_TO_STREAM(pp, min_period); 81 LAP_TO_STREAM(pp, inq_lap); 82 UINT8_TO_STREAM(pp, duration); 83 UINT8_TO_STREAM(pp, response_cnt); 84 85 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 86 } 87 88 void btsnd_hcic_exit_per_inq(void) { 89 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 90 uint8_t* pp = (uint8_t*)(p + 1); 91 92 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXIT_PER_INQ; 93 p->offset = 0; 94 UINT16_TO_STREAM(pp, HCI_EXIT_PERIODIC_INQUIRY_MODE); 95 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXIT_PER_INQ); 96 97 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 98 } 99 100 void btsnd_hcic_create_conn(BD_ADDR dest, uint16_t packet_types, 101 uint8_t page_scan_rep_mode, uint8_t page_scan_mode, 102 uint16_t clock_offset, uint8_t allow_switch) { 103 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 104 uint8_t* pp = (uint8_t*)(p + 1); 105 106 #ifndef BT_10A 107 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN; 108 #else 109 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN - 1; 110 #endif 111 p->offset = 0; 112 113 UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION); 114 #ifndef BT_10A 115 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN); 116 #else 117 UINT8_TO_STREAM(pp, (HCIC_PARAM_SIZE_CREATE_CONN - 1)); 118 #endif 119 BDADDR_TO_STREAM(pp, dest); 120 UINT16_TO_STREAM(pp, packet_types); 121 UINT8_TO_STREAM(pp, page_scan_rep_mode); 122 UINT8_TO_STREAM(pp, page_scan_mode); 123 UINT16_TO_STREAM(pp, clock_offset); 124 #if !defined(BT_10A) 125 UINT8_TO_STREAM(pp, allow_switch); 126 #endif 127 btm_acl_paging(p, dest); 128 } 129 130 void btsnd_hcic_disconnect(uint16_t handle, uint8_t reason) { 131 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 132 uint8_t* pp = (uint8_t*)(p + 1); 133 134 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT; 135 p->offset = 0; 136 137 UINT16_TO_STREAM(pp, HCI_DISCONNECT); 138 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DISCONNECT); 139 UINT16_TO_STREAM(pp, handle); 140 UINT8_TO_STREAM(pp, reason); 141 142 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 143 } 144 145 #if (BTM_SCO_INCLUDED == TRUE) 146 void btsnd_hcic_add_SCO_conn(uint16_t handle, uint16_t packet_types) { 147 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 148 uint8_t* pp = (uint8_t*)(p + 1); 149 150 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN; 151 p->offset = 0; 152 153 UINT16_TO_STREAM(pp, HCI_ADD_SCO_CONNECTION); 154 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ADD_SCO_CONN); 155 156 UINT16_TO_STREAM(pp, handle); 157 UINT16_TO_STREAM(pp, packet_types); 158 159 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 160 } 161 #endif /* BTM_SCO_INCLUDED */ 162 163 void btsnd_hcic_create_conn_cancel(BD_ADDR dest) { 164 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 165 uint8_t* pp = (uint8_t*)(p + 1); 166 167 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL; 168 p->offset = 0; 169 170 UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION_CANCEL); 171 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL); 172 173 BDADDR_TO_STREAM(pp, dest); 174 175 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 176 } 177 178 void btsnd_hcic_accept_conn(BD_ADDR dest, uint8_t role) { 179 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 180 uint8_t* pp = (uint8_t*)(p + 1); 181 182 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_CONN; 183 p->offset = 0; 184 185 UINT16_TO_STREAM(pp, HCI_ACCEPT_CONNECTION_REQUEST); 186 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_CONN); 187 BDADDR_TO_STREAM(pp, dest); 188 UINT8_TO_STREAM(pp, role); 189 190 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 191 } 192 193 void btsnd_hcic_reject_conn(BD_ADDR dest, uint8_t reason) { 194 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 195 uint8_t* pp = (uint8_t*)(p + 1); 196 197 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN; 198 p->offset = 0; 199 200 UINT16_TO_STREAM(pp, HCI_REJECT_CONNECTION_REQUEST); 201 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_CONN); 202 203 BDADDR_TO_STREAM(pp, dest); 204 UINT8_TO_STREAM(pp, reason); 205 206 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 207 } 208 209 void btsnd_hcic_link_key_req_reply(BD_ADDR bd_addr, LINK_KEY link_key) { 210 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 211 uint8_t* pp = (uint8_t*)(p + 1); 212 213 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY; 214 p->offset = 0; 215 216 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_REPLY); 217 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY); 218 219 BDADDR_TO_STREAM(pp, bd_addr); 220 ARRAY16_TO_STREAM(pp, link_key); 221 222 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 223 } 224 225 void btsnd_hcic_link_key_neg_reply(BD_ADDR bd_addr) { 226 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 227 uint8_t* pp = (uint8_t*)(p + 1); 228 229 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY; 230 p->offset = 0; 231 232 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_NEG_REPLY); 233 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY); 234 235 BDADDR_TO_STREAM(pp, bd_addr); 236 237 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 238 } 239 240 void btsnd_hcic_pin_code_req_reply(BD_ADDR bd_addr, uint8_t pin_code_len, 241 PIN_CODE pin_code) { 242 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 243 uint8_t* pp = (uint8_t*)(p + 1); 244 int i; 245 246 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY; 247 p->offset = 0; 248 249 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_REPLY); 250 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY); 251 252 BDADDR_TO_STREAM(pp, bd_addr); 253 UINT8_TO_STREAM(pp, pin_code_len); 254 255 for (i = 0; i < pin_code_len; i++) *pp++ = *pin_code++; 256 257 for (; i < PIN_CODE_LEN; i++) *pp++ = 0; 258 259 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 260 } 261 262 void btsnd_hcic_pin_code_neg_reply(BD_ADDR bd_addr) { 263 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 264 uint8_t* pp = (uint8_t*)(p + 1); 265 266 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY; 267 p->offset = 0; 268 269 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_NEG_REPLY); 270 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY); 271 272 BDADDR_TO_STREAM(pp, bd_addr); 273 274 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 275 } 276 277 void btsnd_hcic_change_conn_type(uint16_t handle, uint16_t packet_types) { 278 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 279 uint8_t* pp = (uint8_t*)(p + 1); 280 281 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE; 282 p->offset = 0; 283 284 UINT16_TO_STREAM(pp, HCI_CHANGE_CONN_PACKET_TYPE); 285 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE); 286 287 UINT16_TO_STREAM(pp, handle); 288 UINT16_TO_STREAM(pp, packet_types); 289 290 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 291 } 292 293 void btsnd_hcic_auth_request(uint16_t handle) { 294 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 295 uint8_t* pp = (uint8_t*)(p + 1); 296 297 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 298 p->offset = 0; 299 300 UINT16_TO_STREAM(pp, HCI_AUTHENTICATION_REQUESTED); 301 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 302 303 UINT16_TO_STREAM(pp, handle); 304 305 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 306 } 307 308 void btsnd_hcic_set_conn_encrypt(uint16_t handle, bool enable) { 309 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 310 uint8_t* pp = (uint8_t*)(p + 1); 311 312 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT; 313 p->offset = 0; 314 315 UINT16_TO_STREAM(pp, HCI_SET_CONN_ENCRYPTION); 316 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT); 317 318 UINT16_TO_STREAM(pp, handle); 319 UINT8_TO_STREAM(pp, enable); 320 321 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 322 } 323 324 void btsnd_hcic_rmt_name_req(BD_ADDR bd_addr, uint8_t page_scan_rep_mode, 325 uint8_t page_scan_mode, uint16_t clock_offset) { 326 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 327 uint8_t* pp = (uint8_t*)(p + 1); 328 329 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_NAME_REQ; 330 p->offset = 0; 331 332 UINT16_TO_STREAM(pp, HCI_RMT_NAME_REQUEST); 333 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_NAME_REQ); 334 335 BDADDR_TO_STREAM(pp, bd_addr); 336 UINT8_TO_STREAM(pp, page_scan_rep_mode); 337 UINT8_TO_STREAM(pp, page_scan_mode); 338 UINT16_TO_STREAM(pp, clock_offset); 339 340 btm_acl_paging(p, bd_addr); 341 } 342 343 void btsnd_hcic_rmt_name_req_cancel(BD_ADDR bd_addr) { 344 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 345 uint8_t* pp = (uint8_t*)(p + 1); 346 347 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL; 348 p->offset = 0; 349 350 UINT16_TO_STREAM(pp, HCI_RMT_NAME_REQUEST_CANCEL); 351 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL); 352 353 BDADDR_TO_STREAM(pp, bd_addr); 354 355 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 356 } 357 358 void btsnd_hcic_rmt_features_req(uint16_t handle) { 359 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 360 uint8_t* pp = (uint8_t*)(p + 1); 361 362 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 363 p->offset = 0; 364 365 UINT16_TO_STREAM(pp, HCI_READ_RMT_FEATURES); 366 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 367 368 UINT16_TO_STREAM(pp, handle); 369 370 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 371 } 372 373 void btsnd_hcic_rmt_ext_features(uint16_t handle, uint8_t page_num) { 374 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 375 uint8_t* pp = (uint8_t*)(p + 1); 376 377 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES; 378 p->offset = 0; 379 380 UINT16_TO_STREAM(pp, HCI_READ_RMT_EXT_FEATURES); 381 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES); 382 383 UINT16_TO_STREAM(pp, handle); 384 UINT8_TO_STREAM(pp, page_num); 385 386 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 387 } 388 389 void btsnd_hcic_rmt_ver_req(uint16_t handle) { 390 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 391 uint8_t* pp = (uint8_t*)(p + 1); 392 393 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 394 p->offset = 0; 395 396 UINT16_TO_STREAM(pp, HCI_READ_RMT_VERSION_INFO); 397 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 398 399 UINT16_TO_STREAM(pp, handle); 400 401 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 402 } 403 404 void btsnd_hcic_read_rmt_clk_offset(uint16_t handle) { 405 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 406 uint8_t* pp = (uint8_t*)(p + 1); 407 408 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 409 p->offset = 0; 410 411 UINT16_TO_STREAM(pp, HCI_READ_RMT_CLOCK_OFFSET); 412 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 413 414 UINT16_TO_STREAM(pp, handle); 415 416 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 417 } 418 419 void btsnd_hcic_read_lmp_handle(uint16_t handle) { 420 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 421 uint8_t* pp = (uint8_t*)(p + 1); 422 423 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 424 p->offset = 0; 425 426 UINT16_TO_STREAM(pp, HCI_READ_LMP_HANDLE); 427 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 428 429 UINT16_TO_STREAM(pp, handle); 430 431 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 432 } 433 434 void btsnd_hcic_setup_esco_conn(uint16_t handle, uint32_t transmit_bandwidth, 435 uint32_t receive_bandwidth, 436 uint16_t max_latency, uint16_t voice, 437 uint8_t retrans_effort, uint16_t packet_types) { 438 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 439 uint8_t* pp = (uint8_t*)(p + 1); 440 441 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO; 442 p->offset = 0; 443 444 UINT16_TO_STREAM(pp, HCI_SETUP_ESCO_CONNECTION); 445 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SETUP_ESCO); 446 447 UINT16_TO_STREAM(pp, handle); 448 UINT32_TO_STREAM(pp, transmit_bandwidth); 449 UINT32_TO_STREAM(pp, receive_bandwidth); 450 UINT16_TO_STREAM(pp, max_latency); 451 UINT16_TO_STREAM(pp, voice); 452 UINT8_TO_STREAM(pp, retrans_effort); 453 UINT16_TO_STREAM(pp, packet_types); 454 455 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 456 } 457 458 void btsnd_hcic_accept_esco_conn(BD_ADDR bd_addr, uint32_t transmit_bandwidth, 459 uint32_t receive_bandwidth, 460 uint16_t max_latency, uint16_t content_fmt, 461 uint8_t retrans_effort, 462 uint16_t packet_types) { 463 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 464 uint8_t* pp = (uint8_t*)(p + 1); 465 466 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO; 467 p->offset = 0; 468 469 UINT16_TO_STREAM(pp, HCI_ACCEPT_ESCO_CONNECTION); 470 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_ESCO); 471 472 BDADDR_TO_STREAM(pp, bd_addr); 473 UINT32_TO_STREAM(pp, transmit_bandwidth); 474 UINT32_TO_STREAM(pp, receive_bandwidth); 475 UINT16_TO_STREAM(pp, max_latency); 476 UINT16_TO_STREAM(pp, content_fmt); 477 UINT8_TO_STREAM(pp, retrans_effort); 478 UINT16_TO_STREAM(pp, packet_types); 479 480 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 481 } 482 483 void btsnd_hcic_reject_esco_conn(BD_ADDR bd_addr, uint8_t reason) { 484 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 485 uint8_t* pp = (uint8_t*)(p + 1); 486 487 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO; 488 p->offset = 0; 489 490 UINT16_TO_STREAM(pp, HCI_REJECT_ESCO_CONNECTION); 491 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_ESCO); 492 493 BDADDR_TO_STREAM(pp, bd_addr); 494 UINT8_TO_STREAM(pp, reason); 495 496 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 497 } 498 499 void btsnd_hcic_hold_mode(uint16_t handle, uint16_t max_hold_period, 500 uint16_t min_hold_period) { 501 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 502 uint8_t* pp = (uint8_t*)(p + 1); 503 504 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE; 505 p->offset = 0; 506 507 UINT16_TO_STREAM(pp, HCI_HOLD_MODE); 508 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_HOLD_MODE); 509 510 UINT16_TO_STREAM(pp, handle); 511 UINT16_TO_STREAM(pp, max_hold_period); 512 UINT16_TO_STREAM(pp, min_hold_period); 513 514 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 515 } 516 517 void btsnd_hcic_sniff_mode(uint16_t handle, uint16_t max_sniff_period, 518 uint16_t min_sniff_period, uint16_t sniff_attempt, 519 uint16_t sniff_timeout) { 520 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 521 uint8_t* pp = (uint8_t*)(p + 1); 522 523 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE; 524 p->offset = 0; 525 526 UINT16_TO_STREAM(pp, HCI_SNIFF_MODE); 527 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_MODE); 528 529 UINT16_TO_STREAM(pp, handle); 530 UINT16_TO_STREAM(pp, max_sniff_period); 531 UINT16_TO_STREAM(pp, min_sniff_period); 532 UINT16_TO_STREAM(pp, sniff_attempt); 533 UINT16_TO_STREAM(pp, sniff_timeout); 534 535 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 536 } 537 538 void btsnd_hcic_exit_sniff_mode(uint16_t handle) { 539 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 540 uint8_t* pp = (uint8_t*)(p + 1); 541 542 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 543 p->offset = 0; 544 545 UINT16_TO_STREAM(pp, HCI_EXIT_SNIFF_MODE); 546 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 547 548 UINT16_TO_STREAM(pp, handle); 549 550 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 551 } 552 553 void btsnd_hcic_park_mode(uint16_t handle, uint16_t beacon_max_interval, 554 uint16_t beacon_min_interval) { 555 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 556 uint8_t* pp = (uint8_t*)(p + 1); 557 558 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE; 559 p->offset = 0; 560 561 UINT16_TO_STREAM(pp, HCI_PARK_MODE); 562 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PARK_MODE); 563 564 UINT16_TO_STREAM(pp, handle); 565 UINT16_TO_STREAM(pp, beacon_max_interval); 566 UINT16_TO_STREAM(pp, beacon_min_interval); 567 568 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 569 } 570 571 void btsnd_hcic_exit_park_mode(uint16_t handle) { 572 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 573 uint8_t* pp = (uint8_t*)(p + 1); 574 575 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 576 p->offset = 0; 577 578 UINT16_TO_STREAM(pp, HCI_EXIT_PARK_MODE); 579 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 580 581 UINT16_TO_STREAM(pp, handle); 582 583 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 584 } 585 586 void btsnd_hcic_qos_setup(uint16_t handle, uint8_t flags, uint8_t service_type, 587 uint32_t token_rate, uint32_t peak, uint32_t latency, 588 uint32_t delay_var) { 589 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 590 uint8_t* pp = (uint8_t*)(p + 1); 591 592 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_QOS_SETUP; 593 p->offset = 0; 594 595 UINT16_TO_STREAM(pp, HCI_QOS_SETUP); 596 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_QOS_SETUP); 597 598 UINT16_TO_STREAM(pp, handle); 599 UINT8_TO_STREAM(pp, flags); 600 UINT8_TO_STREAM(pp, service_type); 601 UINT32_TO_STREAM(pp, token_rate); 602 UINT32_TO_STREAM(pp, peak); 603 UINT32_TO_STREAM(pp, latency); 604 UINT32_TO_STREAM(pp, delay_var); 605 606 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 607 } 608 609 void btsnd_hcic_switch_role(BD_ADDR bd_addr, uint8_t role) { 610 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 611 uint8_t* pp = (uint8_t*)(p + 1); 612 613 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE; 614 p->offset = 0; 615 616 UINT16_TO_STREAM(pp, HCI_SWITCH_ROLE); 617 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SWITCH_ROLE); 618 619 BDADDR_TO_STREAM(pp, bd_addr); 620 UINT8_TO_STREAM(pp, role); 621 622 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 623 } 624 625 void btsnd_hcic_write_policy_set(uint16_t handle, uint16_t settings) { 626 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 627 uint8_t* pp = (uint8_t*)(p + 1); 628 629 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET; 630 p->offset = 0; 631 UINT16_TO_STREAM(pp, HCI_WRITE_POLICY_SETTINGS); 632 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET); 633 634 UINT16_TO_STREAM(pp, handle); 635 UINT16_TO_STREAM(pp, settings); 636 637 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 638 } 639 640 void btsnd_hcic_write_def_policy_set(uint16_t settings) { 641 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 642 uint8_t* pp = (uint8_t*)(p + 1); 643 644 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET; 645 p->offset = 0; 646 UINT16_TO_STREAM(pp, HCI_WRITE_DEF_POLICY_SETTINGS); 647 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET); 648 649 UINT16_TO_STREAM(pp, settings); 650 651 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 652 } 653 654 void btsnd_hcic_set_event_filter(uint8_t filt_type, uint8_t filt_cond_type, 655 uint8_t* filt_cond, uint8_t filt_cond_len) { 656 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 657 uint8_t* pp = (uint8_t*)(p + 1); 658 659 p->offset = 0; 660 661 UINT16_TO_STREAM(pp, HCI_SET_EVENT_FILTER); 662 663 if (filt_type) { 664 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len); 665 UINT8_TO_STREAM(pp, (uint8_t)(2 + filt_cond_len)); 666 667 UINT8_TO_STREAM(pp, filt_type); 668 UINT8_TO_STREAM(pp, filt_cond_type); 669 670 if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) { 671 DEVCLASS_TO_STREAM(pp, filt_cond); 672 filt_cond += DEV_CLASS_LEN; 673 DEVCLASS_TO_STREAM(pp, filt_cond); 674 filt_cond += DEV_CLASS_LEN; 675 676 filt_cond_len -= (2 * DEV_CLASS_LEN); 677 } else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) { 678 BDADDR_TO_STREAM(pp, filt_cond); 679 filt_cond += BD_ADDR_LEN; 680 681 filt_cond_len -= BD_ADDR_LEN; 682 } 683 684 if (filt_cond_len) ARRAY_TO_STREAM(pp, filt_cond, filt_cond_len); 685 } else { 686 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 1); 687 UINT8_TO_STREAM(pp, 1); 688 689 UINT8_TO_STREAM(pp, filt_type); 690 } 691 692 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 693 } 694 695 void btsnd_hcic_write_pin_type(uint8_t type) { 696 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 697 uint8_t* pp = (uint8_t*)(p + 1); 698 699 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 700 p->offset = 0; 701 702 UINT16_TO_STREAM(pp, HCI_WRITE_PIN_TYPE); 703 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 704 705 UINT8_TO_STREAM(pp, type); 706 707 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 708 } 709 710 void btsnd_hcic_delete_stored_key(BD_ADDR bd_addr, bool delete_all_flag) { 711 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 712 uint8_t* pp = (uint8_t*)(p + 1); 713 714 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY; 715 p->offset = 0; 716 717 UINT16_TO_STREAM(pp, HCI_DELETE_STORED_LINK_KEY); 718 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY); 719 720 BDADDR_TO_STREAM(pp, bd_addr); 721 UINT8_TO_STREAM(pp, delete_all_flag); 722 723 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 724 } 725 726 void btsnd_hcic_change_name(BD_NAME name) { 727 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 728 uint8_t* pp = (uint8_t*)(p + 1); 729 uint16_t len = strlen((char*)name) + 1; 730 731 memset(pp, 0, HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME); 732 733 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME; 734 p->offset = 0; 735 736 UINT16_TO_STREAM(pp, HCI_CHANGE_LOCAL_NAME); 737 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_NAME); 738 739 if (len > HCIC_PARAM_SIZE_CHANGE_NAME) len = HCIC_PARAM_SIZE_CHANGE_NAME; 740 741 ARRAY_TO_STREAM(pp, name, len); 742 743 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 744 } 745 746 void btsnd_hcic_read_name(void) { 747 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 748 uint8_t* pp = (uint8_t*)(p + 1); 749 750 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 751 p->offset = 0; 752 753 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_NAME); 754 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD); 755 756 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 757 } 758 759 void btsnd_hcic_write_page_tout(uint16_t timeout) { 760 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 761 uint8_t* pp = (uint8_t*)(p + 1); 762 763 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 764 p->offset = 0; 765 766 UINT16_TO_STREAM(pp, HCI_WRITE_PAGE_TOUT); 767 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 768 769 UINT16_TO_STREAM(pp, timeout); 770 771 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 772 } 773 774 void btsnd_hcic_write_scan_enable(uint8_t flag) { 775 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 776 uint8_t* pp = (uint8_t*)(p + 1); 777 778 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 779 p->offset = 0; 780 781 UINT16_TO_STREAM(pp, HCI_WRITE_SCAN_ENABLE); 782 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 783 784 UINT8_TO_STREAM(pp, flag); 785 786 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 787 } 788 789 void btsnd_hcic_write_pagescan_cfg(uint16_t interval, uint16_t window) { 790 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 791 uint8_t* pp = (uint8_t*)(p + 1); 792 793 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG; 794 p->offset = 0; 795 796 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_CFG); 797 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG); 798 799 UINT16_TO_STREAM(pp, interval); 800 UINT16_TO_STREAM(pp, window); 801 802 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 803 } 804 805 void btsnd_hcic_write_inqscan_cfg(uint16_t interval, uint16_t window) { 806 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 807 uint8_t* pp = (uint8_t*)(p + 1); 808 809 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG; 810 p->offset = 0; 811 812 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRYSCAN_CFG); 813 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG); 814 815 UINT16_TO_STREAM(pp, interval); 816 UINT16_TO_STREAM(pp, window); 817 818 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 819 } 820 821 void btsnd_hcic_write_auth_enable(uint8_t flag) { 822 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 823 uint8_t* pp = (uint8_t*)(p + 1); 824 825 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 826 p->offset = 0; 827 828 UINT16_TO_STREAM(pp, HCI_WRITE_AUTHENTICATION_ENABLE); 829 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 830 831 UINT8_TO_STREAM(pp, flag); 832 833 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 834 } 835 836 void btsnd_hcic_write_dev_class(DEV_CLASS dev_class) { 837 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 838 uint8_t* pp = (uint8_t*)(p + 1); 839 840 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3; 841 p->offset = 0; 842 843 UINT16_TO_STREAM(pp, HCI_WRITE_CLASS_OF_DEVICE); 844 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM3); 845 846 DEVCLASS_TO_STREAM(pp, dev_class); 847 848 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 849 } 850 851 void btsnd_hcic_write_voice_settings(uint16_t flags) { 852 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 853 uint8_t* pp = (uint8_t*)(p + 1); 854 855 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 856 p->offset = 0; 857 858 UINT16_TO_STREAM(pp, HCI_WRITE_VOICE_SETTINGS); 859 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 860 861 UINT16_TO_STREAM(pp, flags); 862 863 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 864 } 865 866 void btsnd_hcic_write_auto_flush_tout(uint16_t handle, uint16_t tout) { 867 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 868 uint8_t* pp = (uint8_t*)(p + 1); 869 870 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTO_FLUSH_TOUT; 871 p->offset = 0; 872 873 UINT16_TO_STREAM(pp, HCI_WRITE_AUTO_FLUSH_TOUT); 874 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_AUTO_FLUSH_TOUT); 875 876 UINT16_TO_STREAM(pp, handle); 877 UINT16_TO_STREAM(pp, tout); 878 879 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 880 } 881 882 void btsnd_hcic_read_tx_power(uint16_t handle, uint8_t type) { 883 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 884 uint8_t* pp = (uint8_t*)(p + 1); 885 886 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER; 887 p->offset = 0; 888 889 UINT16_TO_STREAM(pp, HCI_READ_TRANSMIT_POWER_LEVEL); 890 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_TX_POWER); 891 892 UINT16_TO_STREAM(pp, handle); 893 UINT8_TO_STREAM(pp, type); 894 895 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 896 } 897 898 void btsnd_hcic_host_num_xmitted_pkts(uint8_t num_handles, uint16_t* handle, 899 uint16_t* num_pkts) { 900 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 901 uint8_t* pp = (uint8_t*)(p + 1); 902 903 p->len = HCIC_PREAMBLE_SIZE + 1 + (num_handles * 4); 904 p->offset = 0; 905 906 UINT16_TO_STREAM(pp, HCI_HOST_NUM_PACKETS_DONE); 907 UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE); 908 909 UINT8_TO_STREAM(pp, num_handles); 910 911 for (int i = 0; i < num_handles; i++) { 912 UINT16_TO_STREAM(pp, handle[i]); 913 UINT16_TO_STREAM(pp, num_pkts[i]); 914 } 915 916 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 917 } 918 919 void btsnd_hcic_write_link_super_tout(uint8_t local_controller_id, 920 uint16_t handle, uint16_t timeout) { 921 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 922 uint8_t* pp = (uint8_t*)(p + 1); 923 924 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT; 925 p->offset = 0; 926 927 UINT16_TO_STREAM(pp, HCI_WRITE_LINK_SUPER_TOUT); 928 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT); 929 930 UINT16_TO_STREAM(pp, handle); 931 UINT16_TO_STREAM(pp, timeout); 932 933 btu_hcif_send_cmd(local_controller_id, p); 934 } 935 936 void btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac, LAP* const iac_lap) { 937 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 938 uint8_t* pp = (uint8_t*)(p + 1); 939 940 p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac); 941 p->offset = 0; 942 943 UINT16_TO_STREAM(pp, HCI_WRITE_CURRENT_IAC_LAP); 944 UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE); 945 946 UINT8_TO_STREAM(pp, num_cur_iac); 947 948 for (int i = 0; i < num_cur_iac; i++) LAP_TO_STREAM(pp, iac_lap[i]); 949 950 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 951 } 952 953 /****************************************** 954 * Lisbon Features 955 ******************************************/ 956 #if (BTM_SSR_INCLUDED == TRUE) 957 958 void btsnd_hcic_sniff_sub_rate(uint16_t handle, uint16_t max_lat, 959 uint16_t min_remote_lat, 960 uint16_t min_local_lat) { 961 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 962 uint8_t* pp = (uint8_t*)(p + 1); 963 964 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE; 965 p->offset = 0; 966 967 UINT16_TO_STREAM(pp, HCI_SNIFF_SUB_RATE); 968 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE); 969 970 UINT16_TO_STREAM(pp, handle); 971 UINT16_TO_STREAM(pp, max_lat); 972 UINT16_TO_STREAM(pp, min_remote_lat); 973 UINT16_TO_STREAM(pp, min_local_lat); 974 975 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 976 } 977 #endif /* BTM_SSR_INCLUDED */ 978 979 /**** Extended Inquiry Response Commands ****/ 980 void btsnd_hcic_write_ext_inquiry_response(void* buffer, uint8_t fec_req) { 981 BT_HDR* p = (BT_HDR*)buffer; 982 uint8_t* pp = (uint8_t*)(p + 1); 983 984 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP; 985 p->offset = 0; 986 987 UINT16_TO_STREAM(pp, HCI_WRITE_EXT_INQ_RESPONSE); 988 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXT_INQ_RESP); 989 990 UINT8_TO_STREAM(pp, fec_req); 991 992 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 993 } 994 995 void btsnd_hcic_io_cap_req_reply(BD_ADDR bd_addr, uint8_t capability, 996 uint8_t oob_present, uint8_t auth_req) { 997 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 998 uint8_t* pp = (uint8_t*)(p + 1); 999 1000 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP; 1001 p->offset = 0; 1002 1003 UINT16_TO_STREAM(pp, HCI_IO_CAPABILITY_REQUEST_REPLY); 1004 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_RESP); 1005 1006 BDADDR_TO_STREAM(pp, bd_addr); 1007 UINT8_TO_STREAM(pp, capability); 1008 UINT8_TO_STREAM(pp, oob_present); 1009 UINT8_TO_STREAM(pp, auth_req); 1010 1011 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1012 } 1013 1014 void btsnd_hcic_enhanced_set_up_synchronous_connection( 1015 uint16_t conn_handle, enh_esco_params_t* p_params) { 1016 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1017 uint8_t* pp = (uint8_t*)(p + 1); 1018 1019 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN; 1020 p->offset = 0; 1021 1022 UINT16_TO_STREAM(pp, HCI_ENH_SETUP_ESCO_CONNECTION); 1023 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN); 1024 1025 UINT16_TO_STREAM(pp, conn_handle); 1026 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth); 1027 UINT32_TO_STREAM(pp, p_params->receive_bandwidth); 1028 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format); 1029 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id); 1030 UINT16_TO_STREAM(pp, 1031 p_params->transmit_coding_format.vendor_specific_codec_id); 1032 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format); 1033 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id); 1034 UINT16_TO_STREAM(pp, 1035 p_params->receive_coding_format.vendor_specific_codec_id); 1036 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size); 1037 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size); 1038 UINT32_TO_STREAM(pp, p_params->input_bandwidth); 1039 UINT32_TO_STREAM(pp, p_params->output_bandwidth); 1040 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format); 1041 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id); 1042 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id); 1043 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format); 1044 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id); 1045 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id); 1046 UINT16_TO_STREAM(pp, p_params->input_coded_data_size); 1047 UINT16_TO_STREAM(pp, p_params->output_coded_data_size); 1048 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format); 1049 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format); 1050 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position); 1051 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position); 1052 UINT8_TO_STREAM(pp, p_params->input_data_path); 1053 UINT8_TO_STREAM(pp, p_params->output_data_path); 1054 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size); 1055 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size); 1056 UINT16_TO_STREAM(pp, p_params->max_latency_ms); 1057 UINT16_TO_STREAM(pp, p_params->packet_types); 1058 UINT8_TO_STREAM(pp, p_params->retransmission_effort); 1059 1060 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1061 } 1062 1063 void btsnd_hcic_enhanced_accept_synchronous_connection( 1064 BD_ADDR bd_addr, enh_esco_params_t* p_params) { 1065 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1066 uint8_t* pp = (uint8_t*)(p + 1); 1067 1068 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN; 1069 p->offset = 0; 1070 1071 UINT16_TO_STREAM(pp, HCI_ENH_ACCEPT_ESCO_CONNECTION); 1072 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN); 1073 1074 BDADDR_TO_STREAM(pp, bd_addr); 1075 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth); 1076 UINT32_TO_STREAM(pp, p_params->receive_bandwidth); 1077 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format); 1078 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id); 1079 UINT16_TO_STREAM(pp, 1080 p_params->transmit_coding_format.vendor_specific_codec_id); 1081 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format); 1082 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id); 1083 UINT16_TO_STREAM(pp, 1084 p_params->receive_coding_format.vendor_specific_codec_id); 1085 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size); 1086 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size); 1087 UINT32_TO_STREAM(pp, p_params->input_bandwidth); 1088 UINT32_TO_STREAM(pp, p_params->output_bandwidth); 1089 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format); 1090 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id); 1091 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id); 1092 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format); 1093 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id); 1094 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id); 1095 UINT16_TO_STREAM(pp, p_params->input_coded_data_size); 1096 UINT16_TO_STREAM(pp, p_params->output_coded_data_size); 1097 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format); 1098 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format); 1099 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position); 1100 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position); 1101 UINT8_TO_STREAM(pp, p_params->input_data_path); 1102 UINT8_TO_STREAM(pp, p_params->output_data_path); 1103 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size); 1104 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size); 1105 UINT16_TO_STREAM(pp, p_params->max_latency_ms); 1106 UINT16_TO_STREAM(pp, p_params->packet_types); 1107 UINT8_TO_STREAM(pp, p_params->retransmission_effort); 1108 1109 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1110 } 1111 1112 void btsnd_hcic_io_cap_req_neg_reply(BD_ADDR bd_addr, uint8_t err_code) { 1113 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1114 uint8_t* pp = (uint8_t*)(p + 1); 1115 1116 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY; 1117 p->offset = 0; 1118 1119 UINT16_TO_STREAM(pp, HCI_IO_CAP_REQ_NEG_REPLY); 1120 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY); 1121 1122 BDADDR_TO_STREAM(pp, bd_addr); 1123 UINT8_TO_STREAM(pp, err_code); 1124 1125 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1126 } 1127 1128 void btsnd_hcic_read_local_oob_data(void) { 1129 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1130 uint8_t* pp = (uint8_t*)(p + 1); 1131 1132 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB; 1133 p->offset = 0; 1134 1135 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_DATA); 1136 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB); 1137 1138 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1139 } 1140 1141 void btsnd_hcic_user_conf_reply(BD_ADDR bd_addr, bool is_yes) { 1142 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1143 uint8_t* pp = (uint8_t*)(p + 1); 1144 1145 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY; 1146 p->offset = 0; 1147 1148 if (!is_yes) { 1149 /* Negative reply */ 1150 UINT16_TO_STREAM(pp, HCI_USER_CONF_VALUE_NEG_REPLY); 1151 } else { 1152 /* Confirmation */ 1153 UINT16_TO_STREAM(pp, HCI_USER_CONF_REQUEST_REPLY); 1154 } 1155 1156 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_UCONF_REPLY); 1157 1158 BDADDR_TO_STREAM(pp, bd_addr); 1159 1160 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1161 } 1162 1163 void btsnd_hcic_user_passkey_reply(BD_ADDR bd_addr, uint32_t value) { 1164 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1165 uint8_t* pp = (uint8_t*)(p + 1); 1166 1167 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY; 1168 p->offset = 0; 1169 1170 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_REPLY); 1171 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_REPLY); 1172 1173 BDADDR_TO_STREAM(pp, bd_addr); 1174 UINT32_TO_STREAM(pp, value); 1175 1176 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1177 } 1178 1179 void btsnd_hcic_user_passkey_neg_reply(BD_ADDR bd_addr) { 1180 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1181 uint8_t* pp = (uint8_t*)(p + 1); 1182 1183 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY; 1184 p->offset = 0; 1185 1186 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_NEG_REPLY); 1187 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY); 1188 1189 BDADDR_TO_STREAM(pp, bd_addr); 1190 1191 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1192 } 1193 1194 void btsnd_hcic_rem_oob_reply(BD_ADDR bd_addr, uint8_t* p_c, uint8_t* p_r) { 1195 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1196 uint8_t* pp = (uint8_t*)(p + 1); 1197 1198 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY; 1199 p->offset = 0; 1200 1201 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_REPLY); 1202 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_REPLY); 1203 1204 BDADDR_TO_STREAM(pp, bd_addr); 1205 ARRAY16_TO_STREAM(pp, p_c); 1206 ARRAY16_TO_STREAM(pp, p_r); 1207 1208 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1209 } 1210 1211 void btsnd_hcic_rem_oob_neg_reply(BD_ADDR bd_addr) { 1212 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1213 uint8_t* pp = (uint8_t*)(p + 1); 1214 1215 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY; 1216 p->offset = 0; 1217 1218 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY); 1219 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY); 1220 1221 BDADDR_TO_STREAM(pp, bd_addr); 1222 1223 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1224 } 1225 1226 void btsnd_hcic_read_inq_tx_power(void) { 1227 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1228 uint8_t* pp = (uint8_t*)(p + 1); 1229 1230 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_TX_POWER; 1231 p->offset = 0; 1232 1233 UINT16_TO_STREAM(pp, HCI_READ_INQ_TX_POWER_LEVEL); 1234 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_TX_POWER); 1235 1236 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1237 } 1238 1239 void btsnd_hcic_send_keypress_notif(BD_ADDR bd_addr, uint8_t notif) { 1240 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1241 uint8_t* pp = (uint8_t*)(p + 1); 1242 1243 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF; 1244 p->offset = 0; 1245 1246 UINT16_TO_STREAM(pp, HCI_SEND_KEYPRESS_NOTIF); 1247 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF); 1248 1249 BDADDR_TO_STREAM(pp, bd_addr); 1250 UINT8_TO_STREAM(pp, notif); 1251 1252 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1253 } 1254 1255 /**** end of Simple Pairing Commands ****/ 1256 1257 #if (L2CAP_NON_FLUSHABLE_PB_INCLUDED == TRUE) 1258 void btsnd_hcic_enhanced_flush(uint16_t handle, uint8_t packet_type) { 1259 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1260 uint8_t* pp = (uint8_t*)(p + 1); 1261 1262 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENHANCED_FLUSH; 1263 p->offset = 0; 1264 UINT16_TO_STREAM(pp, HCI_ENHANCED_FLUSH); 1265 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENHANCED_FLUSH); 1266 1267 UINT16_TO_STREAM(pp, handle); 1268 UINT8_TO_STREAM(pp, packet_type); 1269 1270 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1271 } 1272 #endif 1273 1274 /************************* 1275 * End of Lisbon Commands 1276 *************************/ 1277 1278 void btsnd_hcic_get_link_quality(uint16_t handle) { 1279 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1280 uint8_t* pp = (uint8_t*)(p + 1); 1281 1282 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1283 p->offset = 0; 1284 1285 UINT16_TO_STREAM(pp, HCI_GET_LINK_QUALITY); 1286 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1287 1288 UINT16_TO_STREAM(pp, handle); 1289 1290 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1291 } 1292 1293 void btsnd_hcic_read_rssi(uint16_t handle) { 1294 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1295 uint8_t* pp = (uint8_t*)(p + 1); 1296 1297 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1298 p->offset = 0; 1299 1300 UINT16_TO_STREAM(pp, HCI_READ_RSSI); 1301 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1302 1303 UINT16_TO_STREAM(pp, handle); 1304 1305 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1306 } 1307 1308 void btsnd_hcic_enable_test_mode(void) { 1309 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1310 uint8_t* pp = (uint8_t*)(p + 1); 1311 1312 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 1313 p->offset = 0; 1314 1315 UINT16_TO_STREAM(pp, HCI_ENABLE_DEV_UNDER_TEST_MODE); 1316 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD); 1317 1318 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1319 } 1320 1321 void btsnd_hcic_write_inqscan_type(uint8_t type) { 1322 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1323 uint8_t* pp = (uint8_t*)(p + 1); 1324 1325 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1326 p->offset = 0; 1327 1328 UINT16_TO_STREAM(pp, HCI_WRITE_INQSCAN_TYPE); 1329 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1330 1331 UINT8_TO_STREAM(pp, type); 1332 1333 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1334 } 1335 1336 void btsnd_hcic_write_inquiry_mode(uint8_t mode) { 1337 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1338 uint8_t* pp = (uint8_t*)(p + 1); 1339 1340 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1341 p->offset = 0; 1342 1343 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRY_MODE); 1344 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1345 1346 UINT8_TO_STREAM(pp, mode); 1347 1348 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1349 } 1350 1351 void btsnd_hcic_write_pagescan_type(uint8_t type) { 1352 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1353 uint8_t* pp = (uint8_t*)(p + 1); 1354 1355 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1356 p->offset = 0; 1357 1358 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_TYPE); 1359 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1360 1361 UINT8_TO_STREAM(pp, type); 1362 1363 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1364 } 1365 1366 /* Must have room to store BT_HDR + max VSC length + callback pointer */ 1367 #if (HCI_CMD_BUF_SIZE < 268) 1368 #error "HCI_CMD_BUF_SIZE must be larger than 268" 1369 #endif 1370 1371 void btsnd_hcic_vendor_spec_cmd(void* buffer, uint16_t opcode, uint8_t len, 1372 uint8_t* p_data, void* p_cmd_cplt_cback) { 1373 BT_HDR* p = (BT_HDR*)buffer; 1374 uint8_t* pp = (uint8_t*)(p + 1); 1375 1376 p->len = HCIC_PREAMBLE_SIZE + len; 1377 p->offset = sizeof(void*); 1378 1379 *((void**)pp) = 1380 p_cmd_cplt_cback; /* Store command complete callback in buffer */ 1381 pp += sizeof(void*); /* Skip over callback pointer */ 1382 1383 UINT16_TO_STREAM(pp, HCI_GRP_VENDOR_SPECIFIC | opcode); 1384 UINT8_TO_STREAM(pp, len); 1385 ARRAY_TO_STREAM(pp, p_data, len); 1386 1387 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1388 } 1389
