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      1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Mips implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsInstrInfo.h"
     15 #include "InstPrinter/MipsInstPrinter.h"
     16 #include "MipsMachineFunction.h"
     17 #include "MipsSubtarget.h"
     18 #include "llvm/ADT/STLExtras.h"
     19 #include "llvm/CodeGen/MachineInstrBuilder.h"
     20 #include "llvm/CodeGen/MachineRegisterInfo.h"
     21 #include "llvm/Support/ErrorHandling.h"
     22 #include "llvm/Support/TargetRegistry.h"
     23 
     24 using namespace llvm;
     25 
     26 #define GET_INSTRINFO_CTOR_DTOR
     27 #include "MipsGenInstrInfo.inc"
     28 
     29 // Pin the vtable to this file.
     30 void MipsInstrInfo::anchor() {}
     31 
     32 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
     33     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     34       Subtarget(STI), UncondBrOpc(UncondBr) {}
     35 
     36 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
     37   if (STI.inMips16Mode())
     38     return llvm::createMips16InstrInfo(STI);
     39 
     40   return llvm::createMipsSEInstrInfo(STI);
     41 }
     42 
     43 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
     44   return op.isImm() && op.getImm() == 0;
     45 }
     46 
     47 /// insertNoop - If data hazard condition is found insert the target nop
     48 /// instruction.
     49 // FIXME: This appears to be dead code.
     50 void MipsInstrInfo::
     51 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
     52 {
     53   DebugLoc DL;
     54   BuildMI(MBB, MI, DL, get(Mips::NOP));
     55 }
     56 
     57 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
     58                                                 unsigned Flag) const {
     59   MachineFunction &MF = *MBB.getParent();
     60   MachineFrameInfo &MFI = *MF.getFrameInfo();
     61   unsigned Align = MFI.getObjectAlignment(FI);
     62 
     63   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
     64                                  Flag, MFI.getObjectSize(FI), Align);
     65 }
     66 
     67 //===----------------------------------------------------------------------===//
     68 // Branch Analysis
     69 //===----------------------------------------------------------------------===//
     70 
     71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
     72                                   MachineBasicBlock *&BB,
     73                                   SmallVectorImpl<MachineOperand> &Cond) const {
     74   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
     75   int NumOp = Inst->getNumExplicitOperands();
     76 
     77   // for both int and fp branches, the last explicit operand is the
     78   // MBB.
     79   BB = Inst->getOperand(NumOp-1).getMBB();
     80   Cond.push_back(MachineOperand::CreateImm(Opc));
     81 
     82   for (int i=0; i<NumOp-1; i++)
     83     Cond.push_back(Inst->getOperand(i));
     84 }
     85 
     86 bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
     87                                   MachineBasicBlock *&TBB,
     88                                   MachineBasicBlock *&FBB,
     89                                   SmallVectorImpl<MachineOperand> &Cond,
     90                                   bool AllowModify) const {
     91   SmallVector<MachineInstr*, 2> BranchInstrs;
     92   BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
     93 
     94   return (BT == BT_None) || (BT == BT_Indirect);
     95 }
     96 
     97 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     98                                 const DebugLoc &DL,
     99                                 ArrayRef<MachineOperand> Cond) const {
    100   unsigned Opc = Cond[0].getImm();
    101   const MCInstrDesc &MCID = get(Opc);
    102   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
    103 
    104   for (unsigned i = 1; i < Cond.size(); ++i) {
    105     if (Cond[i].isReg())
    106       MIB.addReg(Cond[i].getReg());
    107     else if (Cond[i].isImm())
    108       MIB.addImm(Cond[i].getImm());
    109     else
    110        assert(false && "Cannot copy operand");
    111   }
    112   MIB.addMBB(TBB);
    113 }
    114 
    115 unsigned MipsInstrInfo::InsertBranch(MachineBasicBlock &MBB,
    116                                      MachineBasicBlock *TBB,
    117                                      MachineBasicBlock *FBB,
    118                                      ArrayRef<MachineOperand> Cond,
    119                                      const DebugLoc &DL) const {
    120   // Shouldn't be a fall through.
    121   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    122 
    123   // # of condition operands:
    124   //  Unconditional branches: 0
    125   //  Floating point branches: 1 (opc)
    126   //  Int BranchZero: 2 (opc, reg)
    127   //  Int Branch: 3 (opc, reg0, reg1)
    128   assert((Cond.size() <= 3) &&
    129          "# of Mips branch conditions must be <= 3!");
    130 
    131   // Two-way Conditional branch.
    132   if (FBB) {
    133     BuildCondBr(MBB, TBB, DL, Cond);
    134     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
    135     return 2;
    136   }
    137 
    138   // One way branch.
    139   // Unconditional branch.
    140   if (Cond.empty())
    141     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
    142   else // Conditional branch.
    143     BuildCondBr(MBB, TBB, DL, Cond);
    144   return 1;
    145 }
    146 
    147 unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
    148   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    149   MachineBasicBlock::reverse_iterator FirstBr;
    150   unsigned removed;
    151 
    152   // Skip all the debug instructions.
    153   while (I != REnd && I->isDebugValue())
    154     ++I;
    155 
    156   FirstBr = I;
    157 
    158   // Up to 2 branches are removed.
    159   // Note that indirect branches are not removed.
    160   for (removed = 0; I != REnd && removed < 2; ++I, ++removed)
    161     if (!getAnalyzableBrOpc(I->getOpcode()))
    162       break;
    163 
    164   MBB.erase(I.base(), FirstBr.base());
    165 
    166   return removed;
    167 }
    168 
    169 /// ReverseBranchCondition - Return the inverse opcode of the
    170 /// specified Branch instruction.
    171 bool MipsInstrInfo::ReverseBranchCondition(
    172     SmallVectorImpl<MachineOperand> &Cond) const {
    173   assert( (Cond.size() && Cond.size() <= 3) &&
    174           "Invalid Mips branch condition!");
    175   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
    176   return false;
    177 }
    178 
    179 MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
    180     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
    181     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
    182     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
    183 
    184   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    185 
    186   // Skip all the debug instructions.
    187   while (I != REnd && I->isDebugValue())
    188     ++I;
    189 
    190   if (I == REnd || !isUnpredicatedTerminator(*I)) {
    191     // This block ends with no branches (it just falls through to its succ).
    192     // Leave TBB/FBB null.
    193     TBB = FBB = nullptr;
    194     return BT_NoBranch;
    195   }
    196 
    197   MachineInstr *LastInst = &*I;
    198   unsigned LastOpc = LastInst->getOpcode();
    199   BranchInstrs.push_back(LastInst);
    200 
    201   // Not an analyzable branch (e.g., indirect jump).
    202   if (!getAnalyzableBrOpc(LastOpc))
    203     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
    204 
    205   // Get the second to last instruction in the block.
    206   unsigned SecondLastOpc = 0;
    207   MachineInstr *SecondLastInst = nullptr;
    208 
    209   if (++I != REnd) {
    210     SecondLastInst = &*I;
    211     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
    212 
    213     // Not an analyzable branch (must be an indirect jump).
    214     if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
    215       return BT_None;
    216   }
    217 
    218   // If there is only one terminator instruction, process it.
    219   if (!SecondLastOpc) {
    220     // Unconditional branch.
    221     if (LastInst->isUnconditionalBranch()) {
    222       TBB = LastInst->getOperand(0).getMBB();
    223       return BT_Uncond;
    224     }
    225 
    226     // Conditional branch
    227     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
    228     return BT_Cond;
    229   }
    230 
    231   // If we reached here, there are two branches.
    232   // If there are three terminators, we don't know what sort of block this is.
    233   if (++I != REnd && isUnpredicatedTerminator(*I))
    234     return BT_None;
    235 
    236   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
    237 
    238   // If second to last instruction is an unconditional branch,
    239   // analyze it and remove the last instruction.
    240   if (SecondLastInst->isUnconditionalBranch()) {
    241     // Return if the last instruction cannot be removed.
    242     if (!AllowModify)
    243       return BT_None;
    244 
    245     TBB = SecondLastInst->getOperand(0).getMBB();
    246     LastInst->eraseFromParent();
    247     BranchInstrs.pop_back();
    248     return BT_Uncond;
    249   }
    250 
    251   // Conditional branch followed by an unconditional branch.
    252   // The last one must be unconditional.
    253   if (!LastInst->isUnconditionalBranch())
    254     return BT_None;
    255 
    256   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
    257   FBB = LastInst->getOperand(0).getMBB();
    258 
    259   return BT_CondUncond;
    260 }
    261 
    262 /// Return the corresponding compact (no delay slot) form of a branch.
    263 unsigned MipsInstrInfo::getEquivalentCompactForm(
    264     const MachineBasicBlock::iterator I) const {
    265   unsigned Opcode = I->getOpcode();
    266   bool canUseShortMicroMipsCTI = false;
    267 
    268   if (Subtarget.inMicroMipsMode()) {
    269     switch (Opcode) {
    270     case Mips::BNE:
    271     case Mips::BEQ:
    272     // microMIPS has NE,EQ branches that do not have delay slots provided one
    273     // of the operands is zero.
    274       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
    275         canUseShortMicroMipsCTI = true;
    276       break;
    277     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
    278     // expanded to JR_MM, so they can be replaced with JRC16_MM.
    279     case Mips::JR:
    280     case Mips::PseudoReturn:
    281     case Mips::PseudoIndirectBranch:
    282       canUseShortMicroMipsCTI = true;
    283       break;
    284     }
    285   }
    286 
    287   // MIPSR6 forbids both operands being the zero register.
    288   if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
    289       (I->getOperand(0).isReg() &&
    290        (I->getOperand(0).getReg() == Mips::ZERO ||
    291         I->getOperand(0).getReg() == Mips::ZERO_64)) &&
    292       (I->getOperand(1).isReg() &&
    293        (I->getOperand(1).getReg() == Mips::ZERO ||
    294         I->getOperand(1).getReg() == Mips::ZERO_64)))
    295     return 0;
    296 
    297   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
    298     switch (Opcode) {
    299     case Mips::B:
    300       return Mips::BC;
    301     case Mips::BAL:
    302       return Mips::BALC;
    303     case Mips::BEQ:
    304       if (canUseShortMicroMipsCTI)
    305         return Mips::BEQZC_MM;
    306       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
    307         return 0;
    308       return Mips::BEQC;
    309     case Mips::BNE:
    310       if (canUseShortMicroMipsCTI)
    311         return Mips::BNEZC_MM;
    312       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
    313         return 0;
    314       return Mips::BNEC;
    315     case Mips::BGE:
    316       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
    317         return 0;
    318       return Mips::BGEC;
    319     case Mips::BGEU:
    320       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
    321         return 0;
    322       return Mips::BGEUC;
    323     case Mips::BGEZ:
    324       return Mips::BGEZC;
    325     case Mips::BGTZ:
    326       return Mips::BGTZC;
    327     case Mips::BLEZ:
    328       return Mips::BLEZC;
    329     case Mips::BLT:
    330       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
    331         return 0;
    332       return Mips::BLTC;
    333     case Mips::BLTU:
    334       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
    335         return 0;
    336       return Mips::BLTUC;
    337     case Mips::BLTZ:
    338       return Mips::BLTZC;
    339     // For MIPSR6, the instruction 'jic' can be used for these cases. Some
    340     // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
    341     case Mips::JR:
    342     case Mips::PseudoReturn:
    343     case Mips::PseudoIndirectBranch:
    344       if (canUseShortMicroMipsCTI)
    345         return Mips::JRC16_MM;
    346       return Mips::JIC;
    347     case Mips::JALRPseudo:
    348       return Mips::JIALC;
    349     case Mips::JR64:
    350     case Mips::PseudoReturn64:
    351     case Mips::PseudoIndirectBranch64:
    352       return Mips::JIC64;
    353     case Mips::JALR64Pseudo:
    354       return Mips::JIALC64;
    355     default:
    356       return 0;
    357     }
    358   }
    359 
    360   return 0;
    361 }
    362 
    363 /// Predicate for distingushing between control transfer instructions and all
    364 /// other instructions for handling forbidden slots. Consider inline assembly
    365 /// as unsafe as well.
    366 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
    367   if (MI.isInlineAsm())
    368     return false;
    369 
    370   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
    371 
    372 }
    373 
    374 /// Predicate for distingushing instructions that have forbidden slots.
    375 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
    376   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
    377 }
    378 
    379 /// Return the number of bytes of code the specified instruction may be.
    380 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
    381   switch (MI.getOpcode()) {
    382   default:
    383     return MI.getDesc().getSize();
    384   case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
    385     const MachineFunction *MF = MI.getParent()->getParent();
    386     const char *AsmStr = MI.getOperand(0).getSymbolName();
    387     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
    388   }
    389   case Mips::CONSTPOOL_ENTRY:
    390     // If this machine instr is a constant pool entry, its size is recorded as
    391     // operand #2.
    392     return MI.getOperand(2).getImm();
    393   }
    394 }
    395 
    396 MachineInstrBuilder
    397 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
    398                                   MachineBasicBlock::iterator I) const {
    399   MachineInstrBuilder MIB;
    400 
    401   // Certain branches have two forms: e.g beq $1, $zero, dst vs beqz $1, dest
    402   // Pick the zero form of the branch for readable assembly and for greater
    403   // branch distance in non-microMIPS mode.
    404   // FIXME: Certain atomic sequences on mips64 generate 32bit references to
    405   // Mips::ZERO, which is incorrect. This test should be updated to use
    406   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
    407   // are fixed.
    408   bool BranchWithZeroOperand =
    409       (I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() &&
    410        (I->getOperand(1).getReg() == Mips::ZERO ||
    411         I->getOperand(1).getReg() == Mips::ZERO_64));
    412 
    413   if (BranchWithZeroOperand) {
    414     switch (NewOpc) {
    415     case Mips::BEQC:
    416       NewOpc = Mips::BEQZC;
    417       break;
    418     case Mips::BNEC:
    419       NewOpc = Mips::BNEZC;
    420       break;
    421     case Mips::BGEC:
    422       NewOpc = Mips::BGEZC;
    423       break;
    424     case Mips::BLTC:
    425       NewOpc = Mips::BLTZC;
    426       break;
    427     }
    428   }
    429 
    430   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
    431 
    432   // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
    433   // immediate 0 as an operand and requires the removal of it's %RA<imp-def>
    434   // implicit operand as copying the implicit operations of the instructio we're
    435   // looking at will give us the correct flags.
    436   if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
    437       NewOpc == Mips::JIALC64) {
    438 
    439     if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
    440       MIB->RemoveOperand(0);
    441 
    442     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
    443       MIB.addOperand(I->getOperand(J));
    444     }
    445 
    446     MIB.addImm(0);
    447 
    448  } else if (BranchWithZeroOperand) {
    449     // For MIPSR6 and microMIPS branches with an explicit zero operand, copy
    450     // everything after the zero.
    451      MIB.addOperand(I->getOperand(0));
    452 
    453     for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) {
    454       MIB.addOperand(I->getOperand(J));
    455     }
    456   } else {
    457     // All other cases copy all other operands.
    458     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
    459       MIB.addOperand(I->getOperand(J));
    460     }
    461   }
    462 
    463   MIB.copyImplicitOps(*I);
    464 
    465   MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
    466   return MIB;
    467 }
    468