1 /* 2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <cci400.h> 36 #include <console.h> 37 #include <ctype.h> 38 #include <debug.h> 39 #include <errno.h> 40 #include <gpio.h> 41 #include <hi6220.h> 42 #include <hi6553.h> 43 #include <mmio.h> 44 #include <partitions.h> 45 #include <platform.h> 46 #include <platform_def.h> 47 #include <sp804_timer.h> 48 #include <string.h> 49 #include "../../bl1/bl1_private.h" 50 #include "hikey_def.h" 51 #include "hikey_private.h" 52 53 /******************************************************************************* 54 * Declarations of linker defined symbols which will help us find the layout 55 * of trusted RAM 56 ******************************************************************************/ 57 extern unsigned long __COHERENT_RAM_START__; 58 extern unsigned long __COHERENT_RAM_END__; 59 60 /* 61 * The next 2 constants identify the extents of the coherent memory region. 62 * These addresses are used by the MMU setup code and therefore they must be 63 * page-aligned. It is the responsibility of the linker script to ensure that 64 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 65 * page-aligned addresses. 66 */ 67 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 68 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 69 70 /* Data structure which holds the extents of the trusted RAM for BL1 */ 71 static meminfo_t bl1_tzram_layout; 72 73 static void hi6220_pmussi_init(void); 74 static void hikey_gpio_init(void); 75 static void hikey_hi6553_init(void); 76 static int query_boot_mode(void); 77 78 meminfo_t *bl1_plat_sec_mem_layout(void) 79 { 80 return &bl1_tzram_layout; 81 } 82 83 /******************************************************************************* 84 * Perform any BL1 specific platform actions. 85 ******************************************************************************/ 86 void bl1_early_platform_setup(void) 87 { 88 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 89 90 /* Initialize the console to provide early debug support */ 91 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 92 93 hi6220_timer_init(); 94 /* 95 * Enable CCI-400 for this cluster. No need for locks as no other cpu is 96 * active at the moment 97 */ 98 cci_init(CCI400_BASE, 99 CCI400_SL_IFACE3_CLUSTER_IX, 100 CCI400_SL_IFACE4_CLUSTER_IX); 101 cci_enable_cluster_coherency(read_mpidr()); 102 103 /* Allow BL1 to see the whole Trusted RAM */ 104 bl1_tzram_layout.total_base = BL1_RW_BASE; 105 bl1_tzram_layout.total_size = BL1_RW_SIZE; 106 107 /* Calculate how much RAM BL1 is using and how much remains free */ 108 bl1_tzram_layout.free_base = BL1_RW_BASE; 109 bl1_tzram_layout.free_size = BL1_RW_SIZE; 110 reserve_mem(&bl1_tzram_layout.free_base, 111 &bl1_tzram_layout.free_size, 112 BL1_RAM_BASE, 113 bl1_size); 114 115 INFO("BL1: 0x%lx - 0x%lx [size = %u]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 116 bl1_size); 117 } 118 119 /******************************************************************************* 120 * Perform the very early platform specific architecture setup here. At the 121 * moment this only does basic initialization. Later architectural setup 122 * (bl1_arch_setup()) does not do anything platform specific. 123 ******************************************************************************/ 124 void bl1_plat_arch_setup(void) 125 { 126 configure_mmu_el3(bl1_tzram_layout.total_base, 127 bl1_tzram_layout.total_size, 128 BL1_RO_BASE, 129 BL1_RO_LIMIT, 130 BL1_COHERENT_RAM_BASE, 131 BL1_COHERENT_RAM_LIMIT); 132 } 133 134 static int sd_card_detect(void) 135 { 136 int ret; 137 /* configure GPIO8 as nopull */ 138 mmio_write_32(0xf8001830, 0); 139 gpio_direction_input(8); 140 ret = gpio_get_value(8); 141 if (!ret) 142 return 1; 143 return 0; 144 } 145 146 static void hikey_sd_init(void) 147 { 148 int ret; 149 150 /* switch pinmux to SD */ 151 mmio_write_32(0xf701000c, 0); 152 mmio_write_32(0xf7010010, 0); 153 mmio_write_32(0xf7010014, 0); 154 mmio_write_32(0xf7010018, 0); 155 mmio_write_32(0xf701001c, 0); 156 mmio_write_32(0xf7010020, 0); 157 158 /* input, 16mA or 12mA */ 159 mmio_write_32(0xf701080c, 0x64); 160 mmio_write_32(0xf7010810, 0x54); 161 mmio_write_32(0xf7010814, 0x54); 162 mmio_write_32(0xf7010818, 0x54); 163 mmio_write_32(0xf701081c, 0x54); 164 mmio_write_32(0xf7010820, 0x54); 165 ret = sd_card_detect(); 166 if (ret) 167 INFO("SD Card has been detected.\n"); 168 } 169 170 static void hikey_jumper_init(void) 171 { 172 /* configure GPIO24 as nopull */ 173 mmio_write_32(0xf7010950, 0); 174 /* configure GPIO24 as gpio */ 175 mmio_write_32(0xf7010140, 0); 176 gpio_direction_input(24); 177 VERBOSE("Jumper value:%d\n", gpio_get_value(24)); 178 } 179 180 static inline char hex2str(unsigned int data) 181 { 182 data &= 0xf; 183 if ((data >= 0) && (data <= 9)) 184 return (char)(data + 0x30); 185 return (char)(data - 10 + 0x41); 186 } 187 188 static uint64_t rand(unsigned int data) 189 { 190 int64_t quotient, remainder, t; 191 192 quotient = data / 127773; 193 remainder = data % 127773; 194 t = 16807 * remainder - 2836 * quotient; 195 if (t <= 0) 196 t += RANDOM_MAX; 197 return (t % ((uint64_t)RANDOM_MAX + 1)); 198 } 199 200 void generate_serialno(struct random_serial_num *random) 201 { 202 unsigned int data, t; 203 int i; 204 205 data = mmio_read_32(AO_SC_SYSTEST_SLICER_CNT0); 206 t = rand(data); 207 random->data = ((uint64_t)t << 32) | data; 208 for (i = 0; i < 8; i++) { 209 random->serialno[i] = hex2str((t >> ((7 - i) << 2)) & 0xf); 210 } 211 for (i = 0; i < 8; i++) { 212 random->serialno[i + 8] = hex2str((data >> ((7 - i) << 2)) & 0xf); 213 } 214 random->serialno[16] = '\0'; 215 random->magic = RANDOM_MAGIC; 216 } 217 218 int assign_serialno(char *cmdbuf, struct random_serial_num *random) 219 { 220 int offset, i; 221 222 offset = 0; 223 while (*(cmdbuf + offset) == ' ') 224 offset++; 225 for (i = 0; i < 16; i++) { 226 if (isxdigit(*(cmdbuf + offset + i))) 227 continue; 228 return -EINVAL; 229 } 230 memcpy(random->serialno, cmdbuf + offset, 16); 231 random->serialno[16] = '\0'; 232 random->magic = RANDOM_MAGIC; 233 return 0; 234 } 235 236 static void hikey_verify_serialno(struct random_serial_num *random) 237 { 238 char *serialno; 239 240 serialno = load_serialno(); 241 if (serialno == NULL) { 242 generate_serialno(random); 243 flush_random_serialno((unsigned long)&random, sizeof(random)); 244 } 245 } 246 247 /******************************************************************************* 248 * Function which will perform any remaining platform-specific setup that can 249 * occur after the MMU and data cache have been enabled. 250 ******************************************************************************/ 251 void bl1_platform_setup(void) 252 { 253 struct random_serial_num random; 254 255 hikey_gpio_init(); 256 hi6220_pmussi_init(); 257 hikey_hi6553_init(); 258 hi6220_pll_init(); 259 hikey_sd_init(); 260 hikey_jumper_init(); 261 262 io_setup(); 263 get_partition(); 264 INFO("Hisilicon HiKey platform is initialized\n"); 265 if (query_boot_mode()) { 266 NOTICE("Enter fastboot mode...\n"); 267 flush_loader_image(); 268 hikey_verify_serialno(&random); 269 usb_download(); 270 } 271 } 272 273 /* Get the boot mode (normal boot/usb download/uart download) */ 274 static int query_boot_mode(void) 275 { 276 int boot_mode; 277 278 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE); 279 if ((boot_mode < 0) || (boot_mode > 2)) { 280 NOTICE("Invalid boot mode is found:%d\n", boot_mode); 281 panic(); 282 } 283 return boot_mode; 284 } 285 286 /* PMU SSI is the device that could map external PMU register to IO */ 287 static void hi6220_pmussi_init(void) 288 { 289 uint32_t data; 290 291 /* 292 * After reset, PMUSSI stays in reset mode. 293 * Now make it out of reset. 294 */ 295 mmio_write_32(AO_SC_PERIPH_RSTDIS4, 296 AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 297 do { 298 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 299 } while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 300 301 /* set PMU SSI clock latency for read operation */ 302 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3); 303 data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK; 304 data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3; 305 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data); 306 307 /* enable PMUSSI clock */ 308 data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU | 309 AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU; 310 mmio_write_32(AO_SC_PERIPH_CLKEN5, data); 311 data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI; 312 mmio_write_32(AO_SC_PERIPH_CLKEN4, data); 313 314 /* output high on gpio0 */ 315 gpio_direction_output(0); 316 gpio_set_value(0, 1); 317 } 318 319 static void hikey_hi6553_init(void) 320 { 321 int data; 322 323 hi6553_write_8(PERI_EN_MARK, 0x1e); 324 hi6553_write_8(NP_REG_ADJ1, 0); 325 data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC | 326 DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2; 327 hi6553_write_8(DISABLE6_XO_CLK, data); 328 329 /* configure BUCK0 & BUCK1 */ 330 hi6553_write_8(BUCK01_CTRL2, 0x5e); 331 hi6553_write_8(BUCK0_CTRL7, 0x10); 332 hi6553_write_8(BUCK1_CTRL7, 0x10); 333 hi6553_write_8(BUCK0_CTRL5, 0x1e); 334 hi6553_write_8(BUCK1_CTRL5, 0x1e); 335 hi6553_write_8(BUCK0_CTRL1, 0xfc); 336 hi6553_write_8(BUCK1_CTRL1, 0xfc); 337 338 /* configure BUCK2 */ 339 hi6553_write_8(BUCK2_REG1, 0x4f); 340 hi6553_write_8(BUCK2_REG5, 0x99); 341 hi6553_write_8(BUCK2_REG6, 0x45); 342 mdelay(1); 343 hi6553_write_8(VSET_BUCK2_ADJ, 0x22); 344 mdelay(1); 345 346 /* configure BUCK3 */ 347 hi6553_write_8(BUCK3_REG3, 0x02); 348 hi6553_write_8(BUCK3_REG5, 0x99); 349 hi6553_write_8(BUCK3_REG6, 0x41); 350 hi6553_write_8(VSET_BUCK3_ADJ, 0x02); 351 mdelay(1); 352 353 /* configure BUCK4 */ 354 hi6553_write_8(BUCK4_REG2, 0x9a); 355 hi6553_write_8(BUCK4_REG5, 0x99); 356 hi6553_write_8(BUCK4_REG6, 0x45); 357 358 /* configure LDO20 */ 359 hi6553_write_8(LDO20_REG_ADJ, 0x50); 360 361 hi6553_write_8(NP_REG_CHG, 0x0f); 362 hi6553_write_8(CLK_TOP0, 0x06); 363 hi6553_write_8(CLK_TOP3, 0xc0); 364 hi6553_write_8(CLK_TOP4, 0x00); 365 366 /* configure LDO7 & LDO10 for SD slot */ 367 data = hi6553_read_8(LDO7_REG_ADJ); 368 data = (data & 0xf8) | 0x2; 369 hi6553_write_8(LDO7_REG_ADJ, data); 370 mdelay(5); 371 /* enable LDO7 */ 372 hi6553_write_8(ENABLE2_LDO1_8, 1 << 6); 373 mdelay(5); 374 data = hi6553_read_8(LDO10_REG_ADJ); 375 data = (data & 0xf8) | 0x5; 376 hi6553_write_8(LDO10_REG_ADJ, data); 377 mdelay(5); 378 /* enable LDO10 */ 379 hi6553_write_8(ENABLE3_LDO9_16, 1 << 1); 380 mdelay(5); 381 /* enable LDO15 */ 382 data = hi6553_read_8(LDO15_REG_ADJ); 383 data = (data & 0xf8) | 0x4; 384 hi6553_write_8(LDO15_REG_ADJ, data); 385 hi6553_write_8(ENABLE3_LDO9_16, 1 << 6); 386 mdelay(5); 387 /* enable LDO22 */ 388 data = hi6553_read_8(LDO22_REG_ADJ); 389 data = (data & 0xf8) | 0x7; 390 hi6553_write_8(LDO22_REG_ADJ, data); 391 hi6553_write_8(ENABLE4_LDO17_22, 1 << 5); 392 mdelay(5); 393 394 /* select 32.764KHz */ 395 hi6553_write_8(CLK19M2_600_586_EN, 0x01); 396 } 397 398 static void hikey_gpio_init(void) 399 { 400 gpio_register_device(GPIO0_BASE); 401 gpio_register_device(GPIO1_BASE); 402 gpio_register_device(GPIO2_BASE); 403 gpio_register_device(GPIO3_BASE); 404 gpio_register_device(GPIO4_BASE); 405 gpio_register_device(GPIO5_BASE); 406 gpio_register_device(GPIO6_BASE); 407 gpio_register_device(GPIO7_BASE); 408 gpio_register_device(GPIO8_BASE); 409 gpio_register_device(GPIO9_BASE); 410 gpio_register_device(GPIO10_BASE); 411 gpio_register_device(GPIO11_BASE); 412 gpio_register_device(GPIO12_BASE); 413 gpio_register_device(GPIO13_BASE); 414 gpio_register_device(GPIO14_BASE); 415 gpio_register_device(GPIO15_BASE); 416 gpio_register_device(GPIO16_BASE); 417 gpio_register_device(GPIO17_BASE); 418 gpio_register_device(GPIO18_BASE); 419 gpio_register_device(GPIO19_BASE); 420 421 /* Power on indicator LED (User LED0). */ 422 gpio_direction_output(32); 423 gpio_set_value(32, 1); 424 gpio_direction_output(33); 425 gpio_direction_output(34); 426 gpio_direction_output(35); 427 428 /* Initialize PWR_HOLD GPIO */ 429 gpio_set_value(0, 1); 430 gpio_direction_output(0); 431 } 432 433 /******************************************************************************* 434 * Before calling this function BL2 is loaded in memory and its entrypoint 435 * is set by load_image. This is a placeholder for the platform to change 436 * the entrypoint of BL2 and set SPSR and security state. 437 * On Juno we are only setting the security state, entrypoint 438 ******************************************************************************/ 439 void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, 440 entry_point_info_t *bl2_ep) 441 { 442 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); 443 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 444 } 445
