1 /* NDS32-specific support for 32-bit ELF. 2 Copyright (C) 2012-2014 Free Software Foundation, Inc. 3 Contributed by Andes Technology Corporation. 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22 23 #include <config.h> 24 25 #include <stdlib.h> 26 #include <stdint.h> 27 #include <string.h> 28 #include <assert.h> 29 30 #include "safe-ctype.h" 31 #include "libiberty.h" 32 #include "hashtab.h" 33 #include "bfd.h" 34 35 #include "opcode/nds32.h" 36 #include "nds32-asm.h" 37 38 /* There at at most MAX_LEX_NUM lexical elements in a syntax. */ 39 #define MAX_LEX_NUM 32 40 /* A operand in syntax string should be at most this long. */ 41 #define MAX_LEX_LEN 64 42 /* The max length of a keyword can be. */ 43 #define MAX_KEYWORD_LEN 32 44 /* This LEX is a plain char or operand. */ 45 #define IS_LEX_CHAR(c) (((c) >> 7) == 0) 46 #define LEX_SET_FIELD(c) ((c) | SYN_FIELD) 47 #define LEX_GET_FIELD(c) operand_fields[((c) & 0xff)] 48 /* Get the char in this lexical element. */ 49 #define LEX_CHAR(c) ((c) & 0xff) 50 51 #define USRIDX(group, usr) ((group) | ((usr) << 5)) 52 #define SRIDX(major, minor, ext) \ 53 (((major) << 7) | ((minor) << 3) | (ext)) 54 55 static int parse_re (struct nds32_asm_desc *, struct nds32_asm_insn *, 56 char **, int64_t *); 57 static int parse_re2 (struct nds32_asm_desc *, struct nds32_asm_insn *, 58 char **, int64_t *); 59 static int parse_fe5 (struct nds32_asm_desc *, struct nds32_asm_insn *, 60 char **, int64_t *); 61 static int parse_pi5 (struct nds32_asm_desc *, struct nds32_asm_insn *, 62 char **, int64_t *); 63 static int parse_aext_reg (char **, int *, int); 64 static int parse_a30b20 (struct nds32_asm_desc *, struct nds32_asm_insn *, 65 char **, int64_t *); 66 static int parse_rt21 (struct nds32_asm_desc *, struct nds32_asm_insn *, 67 char **, int64_t *); 68 static int parse_rte_start (struct nds32_asm_desc *, struct nds32_asm_insn *, 69 char **, int64_t *); 70 static int parse_rte_end (struct nds32_asm_desc *, struct nds32_asm_insn *, 71 char **, int64_t *); 72 static int parse_rte69_start (struct nds32_asm_desc *, struct nds32_asm_insn *, 73 char **, int64_t *); 74 static int parse_rte69_end (struct nds32_asm_desc *, struct nds32_asm_insn *, 75 char **, int64_t *); 76 static int parse_im5_ip (struct nds32_asm_desc *, struct nds32_asm_insn *, 77 char **, int64_t *); 78 static int parse_im5_mr (struct nds32_asm_desc *, struct nds32_asm_insn *, 79 char **, int64_t *); 80 static int parse_im6_ip (struct nds32_asm_desc *, struct nds32_asm_insn *, 81 char **, int64_t *); 82 static int parse_im6_iq (struct nds32_asm_desc *, struct nds32_asm_insn *, 83 char **, int64_t *); 84 static int parse_im6_mr (struct nds32_asm_desc *, struct nds32_asm_insn *, 85 char **, int64_t *); 86 static int parse_im6_ms (struct nds32_asm_desc *, struct nds32_asm_insn *, 87 char **, int64_t *); 88 89 /* These are operand prefixes for input/output semantic. 90 91 % input 92 = output 93 & both 94 {} optional operand 95 96 Field table for operands and bit-fields. */ 97 98 const field_t operand_fields[] = 99 { 100 {"rt", 20, 5, 0, HW_GPR, NULL}, 101 {"ra", 15, 5, 0, HW_GPR, NULL}, 102 {"rb", 10, 5, 0, HW_GPR, NULL}, 103 {"rd", 5, 5, 0, HW_GPR, NULL}, 104 {"re", 10, 5, 0, HW_GPR, parse_re}, /* lmw smw lmwa smwa. */ 105 {"fst", 20, 5, 0, HW_FSR, NULL}, 106 {"fsa", 15, 5, 0, HW_FSR, NULL}, 107 {"fsb", 10, 5, 0, HW_FSR, NULL}, 108 {"fdt", 20, 5, 0, HW_FDR, NULL}, 109 {"fda", 15, 5, 0, HW_FDR, NULL}, 110 {"fdb", 10, 5, 0, HW_FDR, NULL}, 111 {"cprt", 20, 5, 0, HW_CPR, NULL}, 112 {"cp", 13, 2, 0, HW_CP, NULL}, 113 {"sh", 5, 5, 0, HW_UINT, NULL}, /* sh in ALU instructions. */ 114 {"sv", 8, 2, 0, HW_UINT, NULL}, /* sv in MEM instructions. */ 115 {"dt", 21, 1, 0, HW_DXR, NULL}, 116 {"usr", 10, 10, 0, HW_USR, NULL}, /* User Special Registers. */ 117 {"sr", 10, 10, 0, HW_SR, NULL}, /* System Registers. */ 118 {"ridx", 10, 10, 0, HW_UINT, NULL}, /* Raw value for mfusr/mfsr. */ 119 {"enb4", 6, 4, 0, HW_UINT, NULL}, /* Enable4 for LSMW. */ 120 {"swid", 5, 15, 0, HW_UINT, NULL}, 121 {"stdby_st", 5, 2, 0, HW_STANDBY_ST, NULL}, 122 {"tlbop_st", 5, 5, 0, HW_TLBOP_ST, NULL}, 123 {"tlbop_stx", 5, 5, 0, HW_UINT, NULL}, 124 {"cctl_st0", 5, 5, 0, HW_CCTL_ST0, NULL}, 125 {"cctl_st1", 5, 5, 0, HW_CCTL_ST1, NULL}, 126 {"cctl_st2", 5, 5, 0, HW_CCTL_ST2, NULL}, 127 {"cctl_st3", 5, 5, 0, HW_CCTL_ST3, NULL}, 128 {"cctl_st4", 5, 5, 0, HW_CCTL_ST4, NULL}, 129 {"cctl_st5", 5, 5, 0, HW_CCTL_ST5, NULL}, 130 {"cctl_stx", 5, 5, 0, HW_UINT, NULL}, 131 {"cctl_lv", 10, 1, 0, HW_CCTL_LV, NULL}, 132 {"msync_st", 5, 3, 0, HW_MSYNC_ST, NULL}, 133 {"msync_stx", 5, 3, 0, HW_UINT, NULL}, 134 {"dpref_st", 20, 4, 0, HW_DPREF_ST, NULL}, 135 {"rt5", 5, 5, 0, HW_GPR, NULL}, 136 {"ra5", 0, 5, 0, HW_GPR, NULL}, 137 {"rt4", 5, 4, 0, HW_GPR, NULL}, 138 {"rt3", 6, 3, 0, HW_GPR, NULL}, 139 {"rt38", 8, 3, 0, HW_GPR, NULL}, /* rt3 used in 38 form. */ 140 {"ra3", 3, 3, 0, HW_GPR, NULL}, 141 {"rb3", 0, 3, 0, HW_GPR, NULL}, 142 {"rt5e", 4, 4, 1, HW_GPR, NULL}, /* for movd44. */ 143 {"ra5e", 0, 4, 1, HW_GPR, NULL}, /* for movd44. */ 144 {"re2", 5, 2, 0, HW_GPR, parse_re2}, /* re in push25/pop25. */ 145 {"fe5", 0, 5, 2, HW_UINT, parse_fe5}, /* imm5u in lwi45.fe. */ 146 {"pi5", 0, 5, 0, HW_UINT, parse_pi5}, /* imm5u in movpi45. */ 147 {"abdim", 2, 3, 0, HW_ABDIM, NULL}, /* Flags for LSMW. */ 148 {"abm", 2, 3, 0, HW_ABM, NULL}, /* Flags for LSMWZB. */ 149 {"dtiton", 8, 2, 0, HW_DTITON, NULL}, 150 {"dtitoff", 8, 2, 0, HW_DTITOFF, NULL}, 151 152 {"i5s", 0, 5, 0, HW_INT, NULL}, 153 {"i10s", 0, 10, 0, HW_INT, NULL}, 154 {"i15s", 0, 15, 0, HW_INT, NULL}, 155 {"i19s", 0, 19, 0, HW_INT, NULL}, 156 {"i20s", 0, 20, 0, HW_INT, NULL}, 157 {"i8s1", 0, 8, 1, HW_INT, NULL}, 158 {"i11br3", 8, 11, 0, HW_INT, NULL}, 159 {"i14s1", 0, 14, 1, HW_INT, NULL}, 160 {"i15s1", 0, 15, 1, HW_INT, NULL}, 161 {"i16s1", 0, 16, 1, HW_INT, NULL}, 162 {"i18s1", 0, 18, 1, HW_INT, NULL}, 163 {"i24s1", 0, 24, 1, HW_INT, NULL}, 164 {"i8s2", 0, 8, 2, HW_INT, NULL}, 165 {"i12s2", 0, 12, 2, HW_INT, NULL}, 166 {"i15s2", 0, 15, 2, HW_INT, NULL}, 167 {"i17s2", 0, 17, 2, HW_INT, NULL}, 168 {"i19s2", 0, 19, 2, HW_INT, NULL}, 169 {"i3u", 0, 3, 0, HW_UINT, NULL}, 170 {"i5u", 0, 5, 0, HW_UINT, NULL}, 171 {"ib5u", 10, 5, 0, HW_UINT, NULL}, /* imm5 field in ALU. */ 172 {"ib5s", 10, 5, 0, HW_INT, NULL}, /* imm5 field in ALU. */ 173 {"i9u", 0, 9, 0, HW_UINT, NULL}, /* for ex9.it. */ 174 {"ia3u", 3, 3, 0, HW_UINT, NULL}, /* for bmski33, fexti33. */ 175 {"i8u", 0, 8, 0, HW_UINT, NULL}, 176 {"ib8u", 7, 8, 0, HW_UINT, NULL}, /* for ffbi. */ 177 {"i15u", 0, 15, 0, HW_UINT, NULL}, 178 {"i20u", 0, 20, 0, HW_UINT, NULL}, 179 {"i3u1", 0, 3, 1, HW_UINT, NULL}, 180 {"i9u1", 0, 9, 1, HW_UINT, NULL}, 181 {"i3u2", 0, 3, 2, HW_UINT, NULL}, 182 {"i6u2", 0, 6, 2, HW_UINT, NULL}, 183 {"i7u2", 0, 7, 2, HW_UINT, NULL}, 184 {"i5u3", 0, 5, 3, HW_UINT, NULL}, /* for pop25/pop25. */ 185 {"i15s3", 0, 15, 3, HW_INT, NULL}, /* for dprefi.d. */ 186 187 {"a_rt", 15, 5, 0, HW_GPR, NULL}, /* for audio-extension. */ 188 {"a_ru", 10, 5, 0, HW_GPR, NULL}, /* for audio-extension. */ 189 {"a_dx", 9, 1, 0, HW_DXR, NULL}, /* for audio-extension. */ 190 {"a_a30", 16, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */ 191 {"a_b20", 12, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */ 192 {"a_rt21", 5, 7, 0, HW_GPR, parse_rt21}, /* for audio-extension. */ 193 {"a_rte", 5, 7, 0, HW_GPR, parse_rte_start}, /* for audio-extension. */ 194 {"a_rte1", 5, 7, 0, HW_GPR, parse_rte_end}, /* for audio-extension. */ 195 {"a_rte69", 6, 4, 0, HW_GPR, parse_rte69_start}, /* for audio-extension. */ 196 {"a_rte69_1", 6, 4, 0, HW_GPR, parse_rte69_end}, /* for audio-extension. */ 197 {"dhy", 5, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */ 198 {"dxh", 15, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */ 199 {"aridx", 0, 5, 0, HW_AEXT_ARIDX, NULL}, /* for audio-extension. */ 200 {"aridx2", 0, 5, 0, HW_AEXT_ARIDX2, NULL}, /* for audio-extension. */ 201 {"aridxi", 16, 4, 0, HW_AEXT_ARIDXI, NULL}, /* for audio-extension. */ 202 {"imm16", 0, 16, 0, HW_UINT, NULL}, /* for audio-extension. */ 203 {"im5_i", 0, 5, 0, HW_AEXT_IM_I, parse_im5_ip}, /* for audio-extension. */ 204 {"im5_m", 0, 5, 0, HW_AEXT_IM_M, parse_im5_mr}, /* for audio-extension. */ 205 {"im6_ip", 0, 2, 0, HW_AEXT_IM_I, parse_im6_ip}, /* for audio-extension. */ 206 {"im6_iq", 0, 2, 0, HW_AEXT_IM_I, parse_im6_iq}, /* for audio-extension. */ 207 {"im6_mr", 2, 2, 0, HW_AEXT_IM_M, parse_im6_mr}, /* for audio-extension. */ 208 {"im6_ms", 4, 2, 0, HW_AEXT_IM_M, parse_im6_ms}, /* for audio-extension. */ 209 {"cp45", 4, 2, 0, HW_CP, NULL}, /* for cop-extension. */ 210 {"i12u", 8, 12, 0, HW_UINT, NULL}, /* for cop-extension. */ 211 {"cpi19", 6, 19, 0, HW_UINT, NULL}, /* for cop-extension. */ 212 {NULL, 0, 0, 0, 0, NULL} 213 }; 214 215 #define DEF_REG(r) (__BIT (r)) 216 #define USE_REG(r) (__BIT (r)) 217 #define RT(r) (r << 20) 218 #define RA(r) (r << 15) 219 #define RB(r) (r << 10) 220 #define RA5(r) (r) 221 222 struct nds32_opcode nds32_opcodes[] = 223 { 224 /* opc6_encoding table OPC_6. */ 225 {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 226 {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 227 {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 228 {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 229 {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 230 {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 231 {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 232 {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 233 {"swi", "%rt,[%ra{+%i15s2}]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 234 {"sbi.bi", "%rt,[%ra],%i15s", OP6 (SBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 235 {"shi.bi", "%rt,[%ra],%i15s1", OP6 (SHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 236 {"swi.bi", "%rt,[%ra],%i15s2", OP6 (SWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 237 238 {"lbsi", "=rt,[%ra{+%i15s}]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 239 {"lhsi", "=rt,[%ra{+%i15s1}]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 240 {"lbsi.bi", "=rt,[%ra],%i15s", OP6 (LBSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 241 {"lhsi.bi", "=rt,[%ra],%i15s1", OP6 (LHSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 242 {"movi", "=rt,%i20s", OP6 (MOVI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 243 {"sethi", "=rt,%i20u", OP6 (SETHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 244 {"addi", "=rt,%ra,%i15s", OP6 (ADDI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 245 {"subri", "=rt,%ra,%i15s", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 246 {"andi", "=rt,%ra,%i15u", OP6 (ANDI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 247 {"xori", "=rt,%ra,%i15u", OP6 (XORI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 248 {"ori", "=rt,%ra,%i15u", OP6 (ORI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 249 {"slti", "=rt,%ra,%i15s", OP6 (SLTI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 250 {"sltsi", "=rt,%ra,%i15s", OP6 (SLTSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 251 {"bitci", "=rt,%ra,%i15u", OP6 (BITCI), 4, ATTR_V3, 0, NULL, 0, NULL}, 252 253 /* seg-DPREFI. */ 254 {"dprefi.w", "%dpref_st,[%ra{+%i15s2}]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 255 {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | __BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 256 /* seg-LBGP. */ 257 {"lbi.gp", "=rt,[+%i19s]", OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 258 {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 259 /* seg-LWC/0. */ 260 {"cplwi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (LWC), 4, 0, 0, NULL, 0, NULL}, 261 {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, 262 /* seg-SWC/0. */ 263 {"cpswi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (SWC), 4, 0, 0, NULL, 0, NULL}, 264 {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, 265 /* seg-LDC/0. */ 266 {"cpldi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (LDC), 4, 0, 0, NULL, 0, NULL}, 267 {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, 268 /* seg-SDC/0. */ 269 {"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (SDC), 4, 0, 0, NULL, 0, NULL}, 270 {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, 271 /* seg-LSMW. */ 272 {"lmw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL}, 273 {"lmwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 274 {"lmwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, 275 {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL}, 276 {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | __BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 277 {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | __BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, 278 /* seg-HWGP. */ 279 {"lhi.gp", "=rt,[+%i18s1]", OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 280 {"lhsi.gp", "=rt,[+%i18s1]", OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 281 {"shi.gp", "%rt,[+%i18s1]", OP6 (HWGP) | (4 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 282 {"lwi.gp", "=rt,[+%i17s2]", OP6 (HWGP) | (6 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 283 {"swi.gp", "%rt,[+%i17s2]", OP6 (HWGP) | (7 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 284 285 /* seg-SBGP. */ 286 {"sbi.gp", "%rt,[+%i19s]", OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 287 {"addi.gp", "=rt,%i19s", OP6 (SBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, 288 /* seg-JI. */ 289 {"j", "%i24s1", OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 290 {"jal", "%i24s1", OP6 (JI) | __BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 291 /* seg-JREG. */ 292 {"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, 293 {"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, 294 {"jrnez", "%rb", JREG (JRNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, 295 {"jralnez", "%rt,%rb", JREG (JRALNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, 296 {"ret", "%rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, 297 {"ifret", "", JREG (JR) | JREG_IFC | JREG_RET, 4, ATTR (BRANCH) | ATTR (IFC_EXT), 0, NULL, 0, NULL}, 298 {"jral", "%rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, 299 {"jralnez", "%rb", JREG (JRALNEZ) | RT (30), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, 300 {"ret", "", JREG (JR) | JREG_RET | RB (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, 301 {"jr", "%dtitoff %rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 302 {"ret", "%dtitoff %rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 303 {"jral", "%dtiton %rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, 304 {"jral", "%dtiton %rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, 305 /* seg-BR1. */ 306 {"beq", "%rt,%ra,%i14s1", OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 307 {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | __BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 308 /* seg-BR2. */ 309 #define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16)) 310 {"ifcall", "%i16s1", BR2 (IFCALL), 4, ATTR (IFC_EXT), 0, NULL, 0, NULL}, 311 {"beqz", "%rt,%i16s1", BR2 (BEQZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 312 {"bnez", "%rt,%i16s1", BR2 (BNEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 313 {"bgez", "%rt,%i16s1", BR2 (BGEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 314 {"bltz", "%rt,%i16s1", BR2 (BLTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 315 {"bgtz", "%rt,%i16s1", BR2 (BGTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 316 {"blez", "%rt,%i16s1", BR2 (BLEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 317 {"bgezal", "%rt,%i16s1", BR2 (BGEZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 318 {"bltzal", "%rt,%i16s1", BR2 (BLTZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 319 /* seg-BR3. */ 320 {"beqc", "%rt,%i11br3,%i8s1", OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL}, 321 {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | __BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL}, 322 /* seg-SIMD. */ 323 {"pbsad", "%rt,%ra,%rb", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, 324 {"pbsada", "%rt,%ra,%rb", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, 325 /* seg-ALU1. */ 326 {"add", "=rt,%ra,%rb", ALU1 (ADD), 4, ATTR_ALL, 0, NULL, 0, NULL}, 327 {"sub", "=rt,%ra,%rb", ALU1 (SUB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 328 {"and", "=rt,%ra,%rb", ALU1 (AND), 4, ATTR_ALL, 0, NULL, 0, NULL}, 329 {"xor", "=rt,%ra,%rb", ALU1 (XOR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 330 {"or", "=rt,%ra,%rb", ALU1 (OR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 331 {"nor", "=rt,%ra,%rb", ALU1 (NOR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 332 {"slt", "=rt,%ra,%rb", ALU1 (SLT), 4, ATTR_ALL, 0, NULL, 0, NULL}, 333 {"slts", "=rt,%ra,%rb", ALU1 (SLTS), 4, ATTR_ALL, 0, NULL, 0, NULL}, 334 {"slli", "=rt,%ra,%ib5u", ALU1 (SLLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 335 {"srli", "=rt,%ra,%ib5u", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 336 {"srai", "=rt,%ra,%ib5u", ALU1 (SRAI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 337 {"rotri", "=rt,%ra,%ib5u", ALU1 (ROTRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 338 {"sll", "=rt,%ra,%rb", ALU1 (SLL), 4, ATTR_ALL, 0, NULL, 0, NULL}, 339 {"srl", "=rt,%ra,%rb", ALU1 (SRL), 4, ATTR_ALL, 0, NULL, 0, NULL}, 340 {"sra", "=rt,%ra,%rb", ALU1 (SRA), 4, ATTR_ALL, 0, NULL, 0, NULL}, 341 {"rotr", "=rt,%ra,%rb", ALU1 (ROTR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 342 {"seb", "=rt,%ra", ALU1 (SEB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 343 {"seh", "=rt,%ra", ALU1 (SEH), 4, ATTR_ALL, 0, NULL, 0, NULL}, 344 {"bitc", "=rt,%ra,%rb", ALU1 (BITC), 4, ATTR_V3, 0, NULL, 0, NULL}, 345 {"zeh", "=rt,%ra", ALU1 (ZEH), 4, ATTR_ALL, 0, NULL, 0, NULL}, 346 {"wsbh", "=rt,%ra", ALU1 (WSBH), 4, ATTR_ALL, 0, NULL, 0, NULL}, 347 {"divsr", "=rt,=rd,%ra,%rb", ALU1 (DIVSR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL}, 348 {"divr", "=rt,=rd,%ra,%rb", ALU1 (DIVR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL}, 349 {"sva", "=rt,%ra,%rb", ALU1 (SVA), 4, ATTR_ALL, 0, NULL, 0, NULL}, 350 {"svs", "=rt,%ra,%rb", ALU1 (SVS), 4, ATTR_ALL, 0, NULL, 0, NULL}, 351 {"cmovz", "=rt,%ra,%rb", ALU1 (CMOVZ), 4, ATTR_ALL, 0, NULL, 0, NULL}, 352 {"cmovn", "=rt,%ra,%rb", ALU1 (CMOVN), 4, ATTR_ALL, 0, NULL, 0, NULL}, 353 {"or_srli", "=rt,%ra,%rb,%sh", ALU1 (OR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, 354 {"add_srli", "=rt,%ra,%rb,%sh", ALU1 (ADD_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, 355 {"sub_srli", "=rt,%ra,%rb,%sh", ALU1 (SUB_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, 356 {"and_srli", "=rt,%ra,%rb,%sh", ALU1 (AND_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, 357 {"xor_srli", "=rt,%ra,%rb,%sh", ALU1 (XOR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, 358 {"add_slli", "=rt,%ra,%rb,%sh", ALU1 (ADD), 4, ATTR_V3, 0, NULL, 0, NULL}, 359 {"sub_slli", "=rt,%ra,%rb,%sh", ALU1 (SUB), 4, ATTR_V3, 0, NULL, 0, NULL}, 360 {"and_slli", "=rt,%ra,%rb,%sh", ALU1 (AND), 4, ATTR_V3, 0, NULL, 0, NULL}, 361 {"xor_slli", "=rt,%ra,%rb,%sh", ALU1 (XOR), 4, ATTR_V3, 0, NULL, 0, NULL}, 362 {"or_slli", "=rt,%ra,%rb,%sh", ALU1 (OR), 4, ATTR_V3, 0, NULL, 0, NULL}, 363 {"nop", "", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 364 /* seg-ALU2. */ 365 {"max", "=rt,%ra,%rb", ALU2 (MAX), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 366 {"min", "=rt,%ra,%rb", ALU2 (MIN), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 367 {"ave", "=rt,%ra,%rb", ALU2 (AVE), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 368 {"abs", "=rt,%ra", ALU2 (ABS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 369 {"clips", "=rt,%ra,%ib5u", ALU2 (CLIPS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 370 {"clip", "=rt,%ra,%ib5u", ALU2 (CLIP), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 371 {"clo", "=rt,%ra", ALU2 (CLO), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 372 {"clz", "=rt,%ra", ALU2 (CLZ), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 373 {"bset", "=rt,%ra,%ib5u", ALU2 (BSET), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 374 {"bclr", "=rt,%ra,%ib5u", ALU2 (BCLR), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 375 {"btgl", "=rt,%ra,%ib5u", ALU2 (BTGL), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 376 {"btst", "=rt,%ra,%ib5u", ALU2 (BTST), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, 377 {"bse", "=rt,%ra,=rb", ALU2 (BSE), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, 378 {"bsp", "=rt,%ra,=rb", ALU2 (BSP), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, 379 {"ffzmism", "=rt,%ra,%rb", ALU2 (FFZMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, 380 {"mfusr", "=rt,%usr", ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 381 {"mtusr", "%rt,%usr", ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 382 {"mfusr", "=rt,%ridx", ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 383 {"mtusr", "%rt,%ridx", ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 384 {"mul", "=rt,%ra,%rb", ALU2 (MUL), 4, ATTR_ALL, 0, NULL, 0, NULL}, 385 {"madds64", "=dt,%ra,%rb", ALU2 (MADDS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL}, 386 {"madd64", "=dt,%ra,%rb", ALU2 (MADD64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL}, 387 {"msubs64", "=dt,%ra,%rb", ALU2 (MSUBS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL}, 388 {"msub64", "=dt,%ra,%rb", ALU2 (MSUB64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL}, 389 {"divs", "=dt,%ra,%rb", ALU2 (DIVS), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL}, 390 {"div", "=dt,%ra,%rb", ALU2 (DIV), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL}, 391 {"mult32", "=dt,%ra,%rb", ALU2 (MULT32), 4, ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, 392 393 /* seg-ALU2_FFBI. */ 394 {"ffb", "=rt,%ra,%rb", ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, 395 {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, 396 /* seg-ALU2_FLMISM. */ 397 {"ffmism", "=rt,%ra,%rb", ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, 398 {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, 399 /* seg-ALU2_MULSR64. */ 400 {"mults64", "=dt,%ra,%rb", ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL}, 401 {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 402 /* seg-ALU2_MULR64. */ 403 {"mult64", "=dt,%ra,%rb", ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL}, 404 {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 405 /* seg-ALU2_MADDR32. */ 406 {"madd32", "=dt,%ra,%rb", ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, 407 {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL}, 408 /* seg-ALU2_MSUBR32. */ 409 {"msub32", "=dt,%ra,%rb", ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, 410 {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL}, 411 412 /* seg-MISC. */ 413 {"standby", "%stdby_st", MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL}, 414 {"mfsr", "=rt,%sr", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 415 {"iret", "", MISC (IRET), 4, ATTR_ALL, 0, NULL, 0, NULL}, 416 {"trap", "%swid", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 417 {"teqz", "%rt{,%swid}", MISC (TEQZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 418 {"tnez", "%rt{,%swid}", MISC (TNEZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 419 {"dsb", "", MISC (DSB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 420 {"isb", "", MISC (ISB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 421 {"break", "%swid", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL}, 422 {"syscall", "%swid", MISC (SYSCALL), 4, ATTR_ALL, 0, NULL, 0, NULL}, 423 {"msync", "%msync_st", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL}, 424 {"isync", "%rt", MISC (ISYNC), 4, ATTR_ALL, 0, NULL, 0, NULL}, 425 /* seg-MISC_MTSR. */ 426 {"mtsr", "%rt,%sr", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 427 /* seg-MISC_SETEND. */ 428 {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL}, 429 {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL}, 430 /* seg-MISC_SETGIE. */ 431 {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL}, 432 {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL}, 433 {"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 434 {"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, 435 {"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 436 {"break", "", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL}, 437 {"msync", "", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL}, 438 /* seg-MISC_TLBOP. */ 439 {"tlbop", "%ra,%tlbop_st", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL}, 440 {"tlbop", "%ra,%tlbop_stx", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL}, 441 {"tlbop", "%rt,%ra,pb", MISC (TLBOP) | (5 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL}, 442 {"tlbop", "flua", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL}, 443 {"tlbop", "flushall", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL}, 444 445 /* seg-MEM. */ 446 {"lb", "=rt,[%ra+(%rb<<%sv)]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 447 {"lb", "=rt,[%ra+%rb{<<%sv}]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 448 {"lh", "=rt,[%ra+(%rb<<%sv)]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL}, 449 {"lh", "=rt,[%ra+%rb{<<%sv}]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL}, 450 {"lw", "=rt,[%ra+(%rb<<%sv)]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL}, 451 {"lw", "=rt,[%ra+%rb{<<%sv}]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL}, 452 {"ld", "=rt,[%ra+(%rb<<%sv)]", MEM (LD), 4, ATTR_ALL, 0, NULL, 0, NULL}, 453 {"lb.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 454 {"lb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 455 {"lb.p", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 456 {"lh.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 457 {"lh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 458 {"lh.p", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 459 {"lw.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 460 {"lw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 461 {"lw.p", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 462 {"ld.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 463 {"sb", "=rt,[%ra+(%rb<<%sv)]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 464 {"sb", "%rt,[%ra+%rb{<<%sv}]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL}, 465 {"sh", "=rt,[%ra+(%rb<<%sv)]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL}, 466 {"sh", "%rt,[%ra+%rb{<<%sv}]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL}, 467 {"sw", "=rt,[%ra+(%rb<<%sv)]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL}, 468 {"sw", "%rt,[%ra+%rb{<<%sv}]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL}, 469 {"sd", "=rt,[%ra+(%rb<<%sv)]", MEM (SD), 4, ATTR_ALL, 0, NULL, 0, NULL}, 470 {"sb.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 471 {"sb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 472 {"sb.p", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 473 {"sh.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 474 {"sh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 475 {"sh.p", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 476 {"sw.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 477 {"sw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 478 {"sw.p", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 479 {"sd.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 480 481 {"lbs", "=rt,[%ra+(%rb<<%sv)]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL}, 482 {"lbs", "=rt,[%ra+%rb{<<%sv}]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL}, 483 {"lhs", "=rt,[%ra+(%rb<<%sv)]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL}, 484 {"lhs", "=rt,[%ra+%rb{<<%sv}]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL}, 485 {"lbs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, 486 {"lbs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 487 {"lbs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, 488 {"lhs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, 489 {"lhs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 490 {"lhs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, 491 {"llw", "=rt,[%ra+(%rb<<%sv)]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 492 {"llw", "=rt,[%ra+%rb{<<%sv}]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 493 {"scw", "%rt,[%ra+(%rb<<%sv)]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 494 {"scw", "%rt,[%ra+%rb{<<%sv}]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 495 496 {"lbup", "=rt,[%ra+(%rb<<%sv)]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 497 {"lbup", "=rt,[%ra+%rb{<<%sv}]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 498 {"lwup", "=rt,[%ra+(%rb<<%sv)]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 499 {"lwup", "=rt,[%ra+%rb{<<%sv}]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 500 {"sbup", "%rt,[%ra+(%rb<<%sv)]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 501 {"sbup", "%rt,[%ra+%rb{<<%sv}]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, 502 {"swup", "%rt,[%ra+(%rb<<%sv)]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 503 {"swup", "%rt,[%ra+%rb{<<%sv}]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 504 505 {"dpref", "%dpref_st,[%ra]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 506 {"dpref", "%dpref_st,[%ra+(%rb<<%sv)]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 507 {"dpref", "%dpref_st,[%ra+%rb{<<%sv}]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 508 509 /* For missing-operand-load/store instructions. */ 510 {"lb", "=rt,[%ra]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 511 {"lh", "=rt,[%ra]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 512 {"lw", "=rt,[%ra]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 513 {"lbs", "=rt,[%ra]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 514 {"lhs", "=rt,[%ra]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 515 {"sb", "%rt,[%ra]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 516 {"sh", "%rt,[%ra]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 517 {"sw", "%rt,[%ra]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 518 519 /* seg-LWC0. */ 520 {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 521 {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 522 /* seg-SWC0. */ 523 {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 524 {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 525 /* seg-LDC0. */ 526 {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 527 {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 528 /* seg-SDC0. */ 529 {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 530 {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, 531 532 /* seg-FPU_FS1. */ 533 {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 534 {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 535 {"fcpynss", "=fst,%fsa,%fsb", FS1 (FCPYNSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 536 {"fcpyss", "=fst,%fsa,%fsb", FS1 (FCPYSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 537 {"fmadds", "=fst,%fsa,%fsb", FS1 (FMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 538 {"fmsubs", "=fst,%fsa,%fsb", FS1 (FMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 539 {"fcmovns", "=fst,%fsa,%fsb", FS1 (FCMOVNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 540 {"fcmovzs", "=fst,%fsa,%fsb", FS1 (FCMOVZS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 541 {"fnmadds", "=fst,%fsa,%fsb", FS1 (FNMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 542 {"fnmsubs", "=fst,%fsa,%fsb", FS1 (FNMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 543 {"fmuls", "=fst,%fsa,%fsb", FS1 (FMULS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 544 {"fdivs", "=fst,%fsa,%fsb", FS1 (FDIVS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 545 546 /* seg-FPU_FS1_F2OP. */ 547 {"fs2d", "=fdt,%fsa", FS1_F2OP (FS2D), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 548 {"fsqrts", "=fst,%fsa", FS1_F2OP (FSQRTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 549 {"fabss", "=fst,%fsa", FS1_F2OP (FABSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 550 {"fui2s", "=fst,%fsa", FS1_F2OP (FUI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 551 {"fsi2s", "=fst,%fsa", FS1_F2OP (FSI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 552 {"fs2ui", "=fst,%fsa", FS1_F2OP (FS2UI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 553 {"fs2ui.z", "=fst,%fsa", FS1_F2OP (FS2UI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 554 {"fs2si", "=fst,%fsa", FS1_F2OP (FS2SI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 555 {"fs2si.z", "=fst,%fsa", FS1_F2OP (FS2SI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 556 /* seg-FPU_FS2. */ 557 {"fcmpeqs", "=fst,%fsa,%fsb", FS2 (FCMPEQS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 558 {"fcmpeqs.e", "=fst,%fsa,%fsb", FS2 (FCMPEQS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 559 {"fcmplts", "=fst,%fsa,%fsb", FS2 (FCMPLTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 560 {"fcmplts.e", "=fst,%fsa,%fsb", FS2 (FCMPLTS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 561 {"fcmples", "=fst,%fsa,%fsb", FS2 (FCMPLES), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 562 {"fcmples.e", "=fst,%fsa,%fsb", FS2 (FCMPLES_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 563 {"fcmpuns", "=fst,%fsa,%fsb", FS2 (FCMPUNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 564 {"fcmpuns.e", "=fst,%fsa,%fsb", FS2 (FCMPUNS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, 565 /* seg-FPU_FD1. */ 566 {"faddd", "=fdt,%fda,%fdb", FD1 (FADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 567 {"fsubd", "=fdt,%fda,%fdb", FD1 (FSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 568 {"fcpynsd", "=fdt,%fda,%fdb", FD1 (FCPYNSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 569 {"fcpysd", "=fdt,%fda,%fdb", FD1 (FCPYSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 570 {"fmaddd", "=fdt,%fda,%fdb", FD1 (FMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 571 {"fmsubd", "=fdt,%fda,%fdb", FD1 (FMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 572 {"fcmovnd", "=fdt,%fda,%fsb", FD1 (FCMOVND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 573 {"fcmovzd", "=fdt,%fda,%fsb", FD1 (FCMOVZD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 574 {"fnmaddd", "=fdt,%fda,%fdb", FD1 (FNMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 575 {"fnmsubd", "=fdt,%fda,%fdb", FD1 (FNMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 576 {"fmuld", "=fdt,%fda,%fdb", FD1 (FMULD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 577 {"fdivd", "=fdt,%fda,%fdb", FD1 (FDIVD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 578 /* seg-FPU_FD1_F2OP. */ 579 {"fd2s", "=fst,%fda", FD1_F2OP (FD2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 580 {"fsqrtd", "=fdt,%fda", FD1_F2OP (FSQRTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 581 {"fabsd", "=fdt,%fda", FD1_F2OP (FABSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 582 {"fui2d", "=fdt,%fsa", FD1_F2OP (FUI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 583 {"fsi2d", "=fdt,%fsa", FD1_F2OP (FSI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 584 {"fd2ui", "=fst,%fda", FD1_F2OP (FD2UI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 585 {"fd2ui.z", "=fst,%fda", FD1_F2OP (FD2UI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 586 {"fd2si", "=fst,%fda", FD1_F2OP (FD2SI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 587 {"fd2si.z", "=fst,%fda", FD1_F2OP (FD2SI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 588 /* seg-FPU_FD2. */ 589 {"fcmpeqd", "=fst,%fda,%fdb", FD2 (FCMPEQD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 590 {"fcmpeqd.e", "=fst,%fda,%fdb", FD2 (FCMPEQD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 591 {"fcmpltd", "=fst,%fda,%fdb", FD2 (FCMPLTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 592 {"fcmpltd.e", "=fst,%fda,%fdb", FD2 (FCMPLTD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 593 {"fcmpled", "=fst,%fda,%fdb", FD2 (FCMPLED), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 594 {"fcmpled.e", "=fst,%fda,%fdb", FD2 (FCMPLED_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 595 {"fcmpund", "=fst,%fda,%fdb", FD2 (FCMPUND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 596 {"fcmpund.e", "=fst,%fda,%fdb", FD2 (FCMPUND_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, 597 /* seg-FPU_MFCP. */ 598 {"fmfsr", "=rt,%fsa", MFCP (FMFSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, 599 {"fmfdr", "=rt,%fda", MFCP (FMFDR), 4, ATTR (FPU), 0, NULL, 0, NULL}, 600 /* seg-FPU_MFCP_XR. */ 601 {"fmfcfg", "=rt", MFCP_XR(FMFCFG), 4, ATTR (FPU), 0, NULL, 0, NULL}, 602 {"fmfcsr", "=rt", MFCP_XR(FMFCSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, 603 /* seg-FPU_MTCP. */ 604 605 {"fmtsr", "%rt,=fsa", MTCP (FMTSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, 606 {"fmtdr", "%rt,=fda", MTCP (FMTDR), 4, ATTR (FPU), 0, NULL, 0, NULL}, 607 /* seg-FPU_MTCP_XR. */ 608 {"fmtcsr", "%rt", MTCP_XR(FMTCSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, 609 /* seg-FPU_FLS. */ 610 {"fls", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 611 {"fls.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 612 /* seg-FPU_FLD. */ 613 {"fld", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 614 {"fld.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 615 /* seg-FPU_FSS. */ 616 {"fss", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 617 {"fss.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 618 /* seg-FPU_FSD. */ 619 {"fsd", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 620 {"fsd.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 621 {"fls", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 622 {"fls.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 623 {"fld", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 624 {"fld.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 625 {"fss", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 626 {"fss.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, 627 {"fsd", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 628 {"fsd.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, 629 {"cctl", "%ra,%cctl_st0", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 630 {"cctl", "%ra,%cctl_st1{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 631 {"cctl", "=rt,%ra,%cctl_st2", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 632 {"cctl", "%rt,%ra,%cctl_st3", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 633 {"cctl", "%cctl_st4", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 634 {"cctl", "%cctl_st5{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3, 0, NULL, 0, NULL}, 635 {"cctl", "=rt,%ra,%cctl_stx,%cctl_lv", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, 636 /* seg-Alias instructions. */ 637 {"neg", "=rt,%ra", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, 638 {"zeb", "=rt,%ra", OP6 (ANDI) | 0xff, 4, ATTR_ALL, 0, NULL, 0, NULL}, 639 640 /* seg-COP. */ 641 {"cpe1", "%cp45,%cpi19", OP6 (COP) | 0x00, 4, ATTR_ALL, 0, NULL, 0, NULL}, 642 {"cpe2", "%cp45,%cpi19", OP6 (COP) | 0x04, 4, ATTR_ALL, 0, NULL, 0, NULL}, 643 {"cpe3", "%cp45,%cpi19", OP6 (COP) | 0x08, 4, ATTR_ALL, 0, NULL, 0, NULL}, 644 {"cpe4", "%cp45,%cpi19", OP6 (COP) | 0x0C, 4, ATTR_ALL, 0, NULL, 0, NULL}, 645 /* seg-COP-MFCPX. */ 646 {"mfcpw", "%cp45,=rt,%i12u", OP6 (COP) | 0x01, 4, ATTR_ALL, 0, NULL, 0, NULL}, 647 {"mfcpd", "%cp45,=rt,%i12u", OP6 (COP) | 0x41, 4, ATTR_ALL, 0, NULL, 0, NULL}, 648 {"mfcppw", "%cp45,=rt,%i12u", OP6 (COP) | 0xc1, 4, ATTR_ALL, 0, NULL, 0, NULL}, 649 /* seg-COP-CPLW. */ 650 {"cplw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x02, 4, ATTR_ALL, 0, NULL, 0, NULL}, 651 {"cplw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x82, 4, ATTR_ALL, 0, NULL, 0, NULL}, 652 /* seg-COP-CPLD. */ 653 {"cpld", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x03, 4, ATTR_ALL, 0, NULL, 0, NULL}, 654 {"cpld.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x83, 4, ATTR_ALL, 0, NULL, 0, NULL}, 655 /* seg-COP-MTCPX. */ 656 {"mtcpw", "%cp45,%rt,%i12u", OP6 (COP) | 0x09, 4, ATTR_ALL, 0, NULL, 0, NULL}, 657 {"mtcpd", "%cp45,%rt,%i12u", OP6 (COP) | 0x49, 4, ATTR_ALL, 0, NULL, 0, NULL}, 658 {"mtcppw", "%cp45,%rt,%i12u", OP6 (COP) | 0xc9, 4, ATTR_ALL, 0, NULL, 0, NULL}, 659 /* seg-COP-CPSW. */ 660 {"cpsw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0a, 4, ATTR_ALL, 0, NULL, 0, NULL}, 661 {"cpsw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8a, 4, ATTR_ALL, 0, NULL, 0, NULL}, 662 /* seg-COP-CPSD. */ 663 {"cpsd", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0b, 4, ATTR_ALL, 0, NULL, 0, NULL}, 664 {"cpsd.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8b, 4, ATTR_ALL, 0, NULL, 0, NULL}, 665 666 /* 16-bit instructions. */ 667 /* get bit14~bit11 of 16-bit instruction. */ 668 {"beqz38", "%rt38,%i8s1", 0xc000, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 669 {"bnez38", "%rt38,%i8s1", 0xc800, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 670 {"beqs38", "%rt38,%i8s1", 0xd000, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, 671 {"bnes38", "%rt38,%i8s1", 0xd800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, 672 673 /* SEG00, get bit10. */ 674 {"mov55", "=rt5,%ra5", 0x8000, 2, ATTR_ALL, 0, NULL, 0, NULL}, 675 {"movi55", "=rt5,%i5s", 0x8400, 2, ATTR_ALL, 0, NULL, 0, NULL}, 676 /* SEG01 bit10~bit9. */ 677 {"add45", "=rt4,%ra5", 0x8800, 2, ATTR_ALL, 0, NULL, 0, NULL}, 678 {"sub45", "=rt4,%ra5", 0x8a00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 679 {"addi45", "=rt4,%i5u", 0x8c00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 680 {"subi45", "=rt4,%i5u", 0x8e00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 681 /* SEG02 bit10~bit9. */ 682 {"srai45", "=rt4,%i5u", 0x9000, 2, ATTR_ALL, 0, NULL, 0, NULL}, 683 {"srli45", "=rt4,%i5u", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL}, 684 {"slli333", "=rt3,%ra3,%i3u", 0x9400, 2, ATTR_ALL, 0, NULL, 0, NULL}, 685 /* SEG03 bit10~bit9. */ 686 {"add333", "=rt3,%ra3,%rb3", 0x9800, 2, ATTR_ALL, 0, NULL, 0, NULL}, 687 {"sub333", "=rt3,%ra3,%rb3", 0x9a00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 688 {"addi333", "=rt3,%ra3,%i3u", 0x9c00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 689 {"subi333", "=rt3,%ra3,%i3u", 0x9e00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 690 /* SEG04 bit10~bit9. */ 691 {"lwi333", "=rt3,[%ra3{+%i3u2}]", 0xa000, 2, ATTR_ALL, 0, NULL, 0, NULL}, 692 {"lwi333.bi", "=rt3,[%ra3],%i3u2", 0xa200, 2, ATTR_ALL, 0, NULL, 0, NULL}, 693 {"lhi333", "=rt3,[%ra3{+%i3u1}]", 0xa400, 2, ATTR_ALL, 0, NULL, 0, NULL}, 694 {"lbi333", "=rt3,[%ra3{+%i3u}]", 0xa600, 2, ATTR_ALL, 0, NULL, 0, NULL}, 695 /* SEG05 bit10~bit9. */ 696 {"swi333", "%rt3,[%ra3{+%i3u2}]", 0xa800, 2, ATTR_ALL, 0, NULL, 0, NULL}, 697 {"swi333.bi", "%rt3,[%ra3],%i3u2", 0xaa00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 698 {"shi333", "%rt3,[%ra3{+%i3u1}]", 0xac00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 699 {"sbi333", "%rt3,[%ra3{+%i3u}]", 0xae00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 700 /* SEG06 bit10~bit9. */ 701 {"addri36.sp", "%rt3,%i6u2", 0xb000, 2, ATTR_V3MUP, USE_REG (31), NULL, 0, NULL}, 702 {"lwi45.fe", "=rt4,%fe5", 0xb200, 2, ATTR_V3MUP, USE_REG (8), NULL, 0, NULL}, 703 {"lwi450", "=rt4,[%ra5]", 0xb400, 2, ATTR_ALL, 0, NULL, 0, NULL}, 704 {"swi450", "%rt4,[%ra5]", 0xb600, 2, ATTR_ALL, 0, NULL, 0, NULL}, 705 /* SEG07 bit7. */ 706 {"lwi37", "=rt38,[$fp{+%i7u2}]", 0xb800, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL}, 707 {"swi37", "%rt38,[$fp{+%i7u2}]", 0xb880, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL}, 708 /* SEG10_1 if Rt3=5. */ 709 {"j8", "%i8s1", 0xd500, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, 710 /* SEG11_2 bit7~bit5. */ 711 {"jr5", "%ra5", 0xdd00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 712 {"jral5", "%ra5", 0xdd20, 2, ATTR_ALL, 0, NULL, 0, NULL}, 713 {"ex9.it", "%i5u", 0xdd40, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL}, 714 {"ret5", "%ra5", 0xdd80, 2, ATTR_ALL, 0, NULL, 0, NULL}, 715 {"add5.pc", "%ra5", 0xdda0, 2, ATTR_V3, 0, NULL, 0, NULL}, 716 /* SEG11_3 if Ra5=30. */ 717 {"ret5", "", 0xdd80 | RA5 (30), 2, ATTR_ALL, 0, NULL, 0, NULL}, 718 /* SEG12 bit10~bit9. */ 719 {"slts45", "%rt4,%ra5", 0xe000, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, 720 {"slt45", "%rt4,%ra5", 0xe200, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, 721 {"sltsi45", "%rt4,%i5u", 0xe400, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, 722 {"slti45", "%rt4,%i5u", 0xe600, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, 723 /* SEG13 bit10~bit9. */ 724 {"break16", "%i5u", 0xea00, 2, ATTR_ALL, 0, NULL, 0, NULL}, 725 {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, 726 {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, 727 /* SEG13_1 bit8. */ 728 {"beqzs8", "%i8s1", 0xe800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL}, 729 {"bnezs8", "%i8s1", 0xe900, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL}, 730 /* SEG13_2 bit8~bit5. */ 731 {"ex9.it", "%i9u", 0xea00, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL}, 732 /* SEG14 bit7. */ 733 {"lwi37.sp", "=rt38,[+%i7u2]", 0xf000, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL}, 734 {"swi37.sp", "%rt38,[+%i7u2]", 0xf080, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL}, 735 /* SEG15 bit10~bit9. */ 736 {"ifcall9", "%i9u1", 0xf800, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL}, 737 {"movpi45", "=rt4,%pi5", 0xfa00, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 738 /* SEG15_1 bit8. */ 739 {"movd44", "=rt5e,%ra5e", 0xfd00, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 740 741 /* SEG-BFMI333 bit2~bit0. */ 742 {"zeb33", "=rt3,%ra3", 0x9600, 2, ATTR_ALL, 0, NULL, 0, NULL}, 743 {"zeh33", "=rt3,%ra3", 0x9601, 2, ATTR_ALL, 0, NULL, 0, NULL}, 744 {"seb33", "=rt3,%ra3", 0x9602, 2, ATTR_ALL, 0, NULL, 0, NULL}, 745 {"seh33", "=rt3,%ra3", 0x9603, 2, ATTR_ALL, 0, NULL, 0, NULL}, 746 {"xlsb33", "=rt3,%ra3", 0x9604, 2, ATTR_ALL, 0, NULL, 0, NULL}, 747 {"x11b33", "=rt3,%ra3", 0x9605, 2, ATTR_ALL, 0, NULL, 0, NULL}, 748 {"bmski33", "=rt3,%ia3u", 0x9606, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 749 {"fexti33", "=rt3,%ia3u", 0x9607, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 750 /* SEG-PUSHPOP25 bit8~bit7. */ 751 {"push25", "%re2,%i5u3", 0xfc00, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, 752 {"pop25", "%re2,%i5u3", 0xfc80, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, 753 /* SEG-MISC33 bit2~bit0. */ 754 {"neg33", "=rt3,%ra3", 0xfe02, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 755 {"not33", "=rt3,%ra3", 0xfe03, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 756 {"mul33", "=rt3,%ra3", 0xfe04, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 757 {"xor33", "=rt3,%ra3", 0xfe05, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 758 {"and33", "=rt3,%ra3", 0xfe06, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 759 {"or33", "=rt3,%ra3", 0xfe07, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, 760 /* SEG-Alias instructions. */ 761 {"nop16", "", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL}, 762 {"ifret16", "", 0x83ff, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL}, 763 764 /* Saturation ext ISA. */ 765 {"kaddw", "=rt,%ra,%rb", ALU2 (KADD), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 766 {"ksubw", "=rt,%ra,%rb", ALU2 (KSUB), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 767 {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 768 {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 769 {"kdmbb", "=rt,%ra,%rb", ALU2 (KMxy), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 770 {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 771 {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 772 {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (6) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 773 {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 774 {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 775 {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 776 {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 777 {"kslraw", "=rt,%ra,%rb", ALU2 (KSLRA), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 778 {"rdov", "=rt", ALU2 (MFUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 779 {"clrov", "", ALU2 (MTUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, 780 781 /* Audio ext. instructions. */ 782 783 {"amtari", "%aridxi,%imm16", AUDIO (AMTARI), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 784 /* N32_AEXT_AMADD */ 785 {"alr2", "=a_rt,=a_ru,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x1 << 6), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 786 {"amaddl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADD) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 787 {"amaddl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADD) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 788 {"amaddl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 789 {"amaddl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 790 {"amaddsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADD) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 791 {"alr", "=a_rt,[%im5_i],%im5_m", AUDIO (AMADD) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 792 {"amadd", "=a_dx,%ra,%rb", AUDIO (AMADD), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 793 {"amabbs", "=a_dx,%ra,%rb", AUDIO (AMADD) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 794 /* N32_AEXT_AMSUB */ 795 {"amsubl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 796 {"amsubl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 797 {"amsubl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 798 {"amsubl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 799 {"amsubsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 800 {"asr", "%ra,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 801 {"amsub", "=a_dx,%ra,%rb", AUDIO (AMSUB), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 802 {"amabts", "=a_dx,%ra,%rb", AUDIO (AMSUB) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 803 /* N32_AEXT_AMULT */ 804 {"amultl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULT) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 805 {"amultl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULT) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 806 {"amultl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 807 {"amultl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 808 {"amultsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULT) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 809 {"ala", "=dxh,[%im5_i],%im5_m", AUDIO (AMULT) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 810 {"amult", "=a_dx,%ra,%rb", AUDIO (AMULT), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 811 {"amatbs", "=a_dx,%ra,%rb", AUDIO (AMULT) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 812 {"asats48", "=a_dx", AUDIO (AMULT) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 813 {"awext", "%ra,%a_dx,%i5u", AUDIO (AMULT) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 814 /* N32_AEXT_AMFAR */ 815 {"amatts", "=a_dx,%ra,%rb", AUDIO (AMFAR) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 816 {"asa", "=dxh,[%im5_i],%im5_m", AUDIO (AMFAR) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 817 {"amtar", "%ra,%aridx", AUDIO (AMFAR) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 818 {"amtar2", "%ra,%aridx2", AUDIO (AMFAR) | (0x12 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 819 {"amfar", "=ra,%aridx", AUDIO (AMFAR) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 820 {"amfar2", "=ra,%aridx2", AUDIO (AMFAR) | (0x13 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 821 /* N32_AEXT_AMADDS */ 822 {"amaddsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 823 {"amaddsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 824 {"amaddsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 825 {"amaddsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 826 {"amaddssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 827 {"aupi", "%im5_i,%im5_m", AUDIO (AMADDS) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 828 {"amadds", "=a_dx,%ra,%rb", AUDIO (AMADDS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 829 {"ambbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 830 {"amawbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 831 /* N32_AEXT_AMSUBS */ 832 {"amsubsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 833 {"amsubsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 834 {"amsubsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 835 {"amsubsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 836 {"amsubssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 837 {"amsubs", "=a_dx,%ra,%rb", AUDIO (AMSUBS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 838 {"ambts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 839 {"amawts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 840 /* N32_AEXT_AMULTS */ 841 {"amultsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 842 {"amultsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 843 {"amultsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 844 {"amultsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 845 {"amultssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 846 {"amults", "=a_dx,%ra,%rb", AUDIO (AMULTS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 847 {"amtbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 848 {"amwbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 849 /* N32_AEXT_AMNEGS */ 850 {"amnegsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 851 {"amnegsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 852 {"amnegsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 853 {"amnegsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 854 {"amnegssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 855 {"amnegs", "=a_dx,%ra,%rb", AUDIO (AMNEGS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 856 {"amtts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 857 {"amwts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 858 /* N32_AEXT_AADDL */ 859 {"aaddl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 860 {"asubl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 861 /* N32_AEXT_AMAWBS */ 862 {"amawbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 863 {"amawbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 864 {"amawbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 865 {"amawbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 866 {"amawbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 867 /* N32_AEXT_AMAWTS */ 868 {"amawtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 869 {"amawtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 870 {"amawtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 871 {"amawtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 872 {"amawtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 873 /* N32_AEXT_AMWBS */ 874 {"amwbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 875 {"amwbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 876 {"amwbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 877 {"amwbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 878 {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 879 {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 880 /* N32_AEXT_AMWTS */ 881 {"amwtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 882 {"amwtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 883 {"amwtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 884 {"amwtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 885 {"amwtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 886 /* N32_AEXT_AMABBS */ 887 {"amabbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 888 {"amabbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 889 {"amabbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 890 {"amabbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 891 {"amabbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 892 /* N32_AEXT_AMABTS */ 893 {"amabtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 894 {"amabtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 895 {"amabtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 896 {"amabtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 897 {"amabtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 898 /* N32_AEXT_AMATBS */ 899 {"amatbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 900 {"amatbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 901 {"amatbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 902 {"amatbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 903 {"amatbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 904 /* N32_AEXT_AMATTS */ 905 {"amattsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 906 {"amattsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 907 {"amattsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 908 {"amattsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 909 {"amattssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 910 /* N32_AEXT_AMBBS */ 911 {"ambbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 912 {"ambbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 913 {"ambbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 914 {"ambbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 915 {"ambbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 916 /* N32_AEXT_AMBTS */ 917 {"ambtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 918 {"ambtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 919 {"ambtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 920 {"ambtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 921 {"ambtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 922 /* N32_AEXT_AMTBS */ 923 {"amtbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 924 {"amtbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 925 {"amtbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 926 {"amtbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 927 {"amtbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 928 /* N32_AEXT_AMTTS */ 929 {"amttsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 930 {"amttsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 931 {"amttsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 932 {"amttsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 933 {"amttssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, 934 {NULL, NULL, 0, 0, 0, 0, NULL, 0, NULL}, 935 }; 936 937 const keyword_t keyword_gpr[] = 938 { 939 /* Standard names. */ 940 {"r0", 0, ATTR (RDREG)}, {"r1", 1, ATTR (RDREG)}, {"r2", 2, ATTR (RDREG)}, 941 {"r3", 3, ATTR (RDREG)}, {"r4", 4, ATTR (RDREG)}, {"r5", 5, ATTR (RDREG)}, 942 {"r6", 6, ATTR (RDREG)}, {"r7", 7, ATTR (RDREG)}, {"r8", 8, ATTR (RDREG)}, 943 {"r9", 9, ATTR (RDREG)}, {"r10", 10, ATTR (RDREG)}, {"r11", 11, 0}, 944 {"r12", 12, 0}, {"r13", 13, 0}, {"r14", 14, 0}, {"r15", 15, ATTR (RDREG)}, 945 {"r16", 16, 0}, {"r17", 17, 0}, {"r18", 18, 0}, {"r19", 19, 0}, 946 {"r20", 20, 0}, {"r21", 21, 0}, {"r22", 22, 0}, {"r23", 23, 0}, 947 {"r24", 24, 0}, {"r25", 25, 0}, 948 {"p0", 26, 0}, {"p1", 27, 0}, 949 {"fp", 28, ATTR (RDREG)}, {"gp", 29, ATTR (RDREG)}, 950 {"lp", 30, ATTR (RDREG)}, {"sp", 31, ATTR (RDREG)}, 951 {"r26", 26, 0}, {"r27", 27, 0}, 952 {"r28", 28, ATTR (RDREG)}, {"r29", 29, ATTR (RDREG)}, 953 {"r30", 30, ATTR (RDREG)}, {"r31", 31, ATTR (RDREG)}, 954 /* Names for parameter passing. */ 955 {"a0", 0, ATTR (RDREG)}, {"a1", 1, ATTR (RDREG)}, 956 {"a2", 2, ATTR (RDREG)}, {"a3", 3, ATTR (RDREG)}, 957 {"a4", 4, ATTR (RDREG)}, {"a5", 5, ATTR (RDREG)}, 958 /* Names reserved for 5-bit addressing only. */ 959 {"s0", 6, ATTR (RDREG)}, {"s1", 7, ATTR (RDREG)}, 960 {"s2", 8, ATTR (RDREG)}, {"s3", 9, ATTR (RDREG)}, 961 {"s4", 10, ATTR (RDREG)}, {"s5", 11, 0}, {"s6", 12, 0}, {"s7", 13, 0}, 962 {"s8", 14, 0}, {"s9", 28, ATTR (RDREG)}, 963 {"ta", 15, ATTR (RDREG)}, 964 {"t0", 16, 0}, {"t1", 17, 0}, {"t2", 18, 0}, {"t3", 19, 0}, 965 {"t4", 20, 0}, {"t5", 21, 0}, {"t6", 22, 0}, {"t7", 23, 0}, 966 {"t8", 24, 0}, {"t9", 25, 0}, 967 /* Names reserved for 4-bit addressing only. */ 968 {"h0", 0, ATTR (RDREG)}, {"h1", 1, ATTR (RDREG)}, 969 {"h2", 2, ATTR (RDREG)}, {"h3", 3, ATTR (RDREG)}, 970 {"h4", 4, ATTR (RDREG)}, {"h5", 5, ATTR (RDREG)}, 971 {"h6", 6, ATTR (RDREG)}, {"h7", 7, ATTR (RDREG)}, 972 {"h8", 8, ATTR (RDREG)}, {"h9", 9, ATTR (RDREG)}, 973 {"h10", 10, ATTR (RDREG)}, {"h11", 11, 0}, 974 {"h12", 16, 0}, {"h13", 17, 0}, {"h14", 18, 0}, {"h15", 19, 0}, 975 /* Names reserved for 3-bit addressing only. */ 976 {"o0", 0, ATTR (RDREG)}, {"o1", 1, ATTR (RDREG)}, 977 {"o2", 2, ATTR (RDREG)}, {"o3", 3, ATTR (RDREG)}, 978 {"o4", 4, ATTR (RDREG)}, {"o5", 5, ATTR (RDREG)}, 979 {"o6", 6, ATTR (RDREG)}, {"o7", 7, ATTR (RDREG)}, 980 {NULL, 0, 0} 981 }; 982 983 const keyword_t keyword_usr[] = 984 { 985 {"d0.lo", USRIDX (0, 0), 0}, 986 {"d0.hi", USRIDX (0, 1), 0}, 987 {"d1.lo", USRIDX (0, 2), 0}, 988 {"d1.hi", USRIDX (0, 3), 0}, 989 {"itb", USRIDX (0, 28), 0}, 990 {"ifc_lp", USRIDX (0, 29), 0}, 991 {"pc", USRIDX (0, 31), 0}, 992 993 {"dma_cfg", USRIDX (1, 0), 0}, 994 {"dma_gcsw", USRIDX (1, 1), 0}, 995 {"dma_chnsel", USRIDX (1, 2), 0}, 996 {"dma_act", USRIDX (1, 3), 0}, 997 {"dma_setup", USRIDX (1, 4), 0}, 998 {"dma_isaddr", USRIDX (1, 5), 0}, 999 {"dma_esaddr", USRIDX (1, 6), 0}, 1000 {"dma_tcnt", USRIDX (1, 7), 0}, 1001 {"dma_status", USRIDX (1, 8), 0}, 1002 {"dma_2dset", USRIDX (1, 9), 0}, 1003 {"dma_rcnt", USRIDX (1, 23), 0}, 1004 {"dma_hstatus", USRIDX (1, 24), 0}, 1005 {"dma_2dsctl", USRIDX (1, 25), 0}, 1006 1007 {"pfmc0", USRIDX (2, 0), 0}, 1008 {"pfmc1", USRIDX (2, 1), 0}, 1009 {"pfmc2", USRIDX (2, 2), 0}, 1010 {"pfm_ctl", USRIDX (2, 4), 0}, 1011 1012 {NULL, 0, 0} 1013 }; 1014 1015 const keyword_t keyword_dxr[] = 1016 { 1017 {"d0", 0, 0}, {"d1", 1, 0}, {NULL, 0, 0} 1018 }; 1019 1020 const keyword_t keyword_sr[] = 1021 { 1022 {"cpu_ver", SRIDX (0, 0, 0), 0}, {"cr0", SRIDX (0, 0, 0), 0}, 1023 {"icm_cfg", SRIDX (0, 1, 0), 0}, {"cr1", SRIDX (0, 1, 0), 0}, 1024 {"dcm_cfg", SRIDX (0, 2, 0), 0}, {"cr2", SRIDX (0, 2, 0), 0}, 1025 {"mmu_cfg", SRIDX (0, 3, 0), 0}, {"cr3", SRIDX (0, 3, 0), 0}, 1026 {"msc_cfg", SRIDX (0, 4, 0), 0}, {"cr4", SRIDX (0, 4, 0), 0}, 1027 {"core_id", SRIDX (0, 0, 1), 0}, {"cr5", SRIDX (0, 0, 1), 0}, 1028 {"fucop_exist", SRIDX (0, 5, 0), 0}, {"cr6", SRIDX (0, 5, 0), 0}, 1029 1030 {"psw", SRIDX (1, 0, 0), 0}, {"ir0", SRIDX (1, 0, 0), 0}, 1031 {"ipsw", SRIDX (1, 0, 1), 0}, {"ir1", SRIDX (1, 0, 1), 0}, 1032 {"p_ipsw", SRIDX (1, 0, 2), 0}, {"ir2", SRIDX (1, 0, 2), 0}, 1033 {"ivb", SRIDX (1, 1, 1), 0}, {"ir3", SRIDX (1, 1, 1), 0}, 1034 {"eva", SRIDX (1, 2, 1), 0}, {"ir4", SRIDX (1, 2, 1), 0}, 1035 {"p_eva", SRIDX (1, 2, 2), 0}, {"ir5", SRIDX (1, 2, 2), 0}, 1036 {"itype", SRIDX (1, 3, 1), 0}, {"ir6", SRIDX (1, 3, 1), 0}, 1037 {"p_itype", SRIDX (1, 3, 2), 0}, {"ir7", SRIDX (1, 3, 2), 0}, 1038 {"merr", SRIDX (1, 4, 1), 0}, {"ir8", SRIDX (1, 4, 1), 0}, 1039 {"ipc", SRIDX (1, 5, 1), 0}, {"ir9", SRIDX (1, 5, 1), 0}, 1040 {"p_ipc", SRIDX (1, 5, 2), 0}, {"ir10", SRIDX (1, 5, 2), 0}, 1041 {"oipc", SRIDX (1, 5, 3), 0}, {"ir11", SRIDX (1, 5, 3), 0}, 1042 {"p_p0", SRIDX (1, 6, 2), 0}, {"ir12", SRIDX (1, 6, 2), 0}, 1043 {"p_p1", SRIDX (1, 7, 2), 0}, {"ir13", SRIDX (1, 7, 2), 0}, 1044 {"int_mask", SRIDX (1, 8, 0), 0}, {"ir14", SRIDX (1, 8, 0), 0}, 1045 {"int_pend", SRIDX (1, 9, 0), 0}, {"ir15", SRIDX (1, 9, 0), 0}, 1046 {"sp_usr", SRIDX (1, 10, 0), 0}, {"ir16", SRIDX (1, 10, 0), 0}, 1047 {"sp_priv", SRIDX (1, 10, 1), 0}, {"ir17", SRIDX (1, 10, 1), 0}, 1048 {"int_pri", SRIDX (1, 11, 0), 0}, {"ir18", SRIDX (1, 11, 0), 0}, 1049 {"int_ctrl", SRIDX (1, 1, 2), 0}, {"ir19", SRIDX (1, 1, 2), 0}, 1050 {"sp_usr1", SRIDX (1, 10, 2), 0}, {"ir20", SRIDX (1, 10, 2), 0}, 1051 {"sp_priv1", SRIDX (1, 10, 3), 0}, {"ir21", SRIDX (1, 10, 3), 0}, 1052 {"sp_usr2", SRIDX (1, 10, 4), 0}, {"ir22", SRIDX (1, 10, 4), 0}, 1053 {"sp_priv2", SRIDX (1, 10, 5), 0}, {"ir23", SRIDX (1, 10, 5), 0}, 1054 {"sp_usr3", SRIDX (1, 10, 6), 0}, {"ir24", SRIDX (1, 10, 6), 0}, 1055 {"sp_priv3", SRIDX (1, 10, 7), 0}, {"ir25", SRIDX (1, 10, 7), 0}, 1056 {"int_mask2", SRIDX (1, 8, 1), 0}, {"ir26", SRIDX (1, 8, 1), 0}, 1057 {"int_pend2", SRIDX (1, 9, 1), 0}, {"ir27", SRIDX (1, 9, 1), 0}, 1058 {"int_pri2", SRIDX (1, 11, 1), 0}, {"ir28", SRIDX (1, 11, 1), 0}, 1059 {"int_trigger", SRIDX (1, 9, 4), 0}, {"ir29", SRIDX (1, 9, 4), 0}, 1060 {"int_gpr_push_dis", SRIDX(1, 1, 3), 0}, {"ir30", SRIDX (1, 1, 3), 0}, 1061 1062 {"mmu_ctl", SRIDX (2, 0, 0), 0}, {"mr0", SRIDX (2, 0, 0), 0}, 1063 {"l1_pptb", SRIDX (2, 1, 0), 0}, {"mr1", SRIDX (2, 1, 0), 0}, 1064 {"tlb_vpn", SRIDX (2, 2, 0), 0}, {"mr2", SRIDX (2, 2, 0), 0}, 1065 {"tlb_data", SRIDX (2, 3, 0), 0}, {"mr3", SRIDX (2, 3, 0), 0}, 1066 {"tlb_misc", SRIDX (2, 4, 0), 0}, {"mr4", SRIDX (2, 4, 0), 0}, 1067 {"vlpt_idx", SRIDX (2, 5, 0), 0}, {"mr5", SRIDX (2, 5, 0), 0}, 1068 {"ilmb", SRIDX (2, 6, 0), 0}, {"mr6", SRIDX (2, 6, 0), 0}, 1069 {"dlmb", SRIDX (2, 7, 0), 0}, {"mr7", SRIDX (2, 7, 0), 0}, 1070 {"cache_ctl", SRIDX (2, 8, 0), 0}, {"mr8", SRIDX (2, 8, 0), 0}, 1071 {"hsmp_saddr", SRIDX (2, 9, 0), 0}, {"mr9", SRIDX (2, 9, 0), 0}, 1072 {"hsmp_eaddr", SRIDX (2, 9, 1), 0}, {"mr10", SRIDX (2, 9, 1), 0}, 1073 {"bg_region", SRIDX (2, 0, 1), 0}, {"mr11", SRIDX (2, 0, 1), 0}, 1074 1075 {"pfmc0", SRIDX (4, 0, 0), 0}, {"pfr0", SRIDX (4, 0, 0), 0}, 1076 {"pfmc1", SRIDX (4, 0, 1), 0}, {"pfr1", SRIDX (4, 0, 1), 0}, 1077 {"pfmc2", SRIDX (4, 0, 2), 0}, {"pfr2", SRIDX (4, 0, 2), 0}, 1078 {"pfm_ctl", SRIDX (4, 1, 0), 0}, {"pfr3", SRIDX (4, 1, 0), 0}, 1079 1080 {"dma_cfg", SRIDX (5, 0, 0), 0}, {"dmar0", SRIDX (5, 0, 0), 0}, 1081 {"dma_gcsw", SRIDX (5, 1, 0), 0}, {"dmar1", SRIDX (5, 1, 0), 0}, 1082 {"dma_chnsel", SRIDX (5, 2, 0), 0}, {"dmar2", SRIDX (5, 2, 0), 0}, 1083 {"dma_act", SRIDX (5, 3, 0), 0}, {"dmar3", SRIDX (5, 3, 0), 0}, 1084 {"dma_setup", SRIDX (5, 4, 0), 0}, {"dmar4", SRIDX (5, 4, 0), 0}, 1085 {"dma_isaddr", SRIDX (5, 5, 0), 0}, {"dmar5", SRIDX (5, 5, 0), 0}, 1086 {"dma_esaddr", SRIDX (5, 6, 0), 0}, {"dmar6", SRIDX (5, 6, 0), 0}, 1087 {"dma_tcnt", SRIDX (5, 7, 0), 0}, {"dmar7", SRIDX (5, 7, 0), 0}, 1088 {"dma_status", SRIDX (5, 8, 0), 0}, {"dmar8", SRIDX (5, 8, 0), 0}, 1089 {"dma_2dset", SRIDX (5, 9, 0), 0}, {"dmar9", SRIDX (5, 9, 0), 0}, 1090 {"dma_2dsctl", SRIDX (5, 9, 1), 0}, {"dmar10", SRIDX (5, 9, 1), 0}, 1091 {"dma_rcnt", SRIDX (5, 7, 1), 0}, {"dmar11", SRIDX (5, 7, 1), 0}, 1092 {"dma_hstatus", SRIDX (5, 8, 1), 0}, {"dmar12", SRIDX (5, 8, 1), 0}, 1093 1094 {"sdz_ctl", SRIDX (2, 15, 0), 0}, {"idr0", SRIDX (2, 15, 0), 0}, 1095 {"misc_ctl", SRIDX (2, 15, 1), 0}, {"n12misc_ctl", SRIDX (2, 15, 1), 0}, 1096 {"idr1", SRIDX (2, 15, 1), 0}, 1097 1098 {"secur0", SRIDX (6, 0, 0), 0}, {"sfcr", SRIDX (6, 0, 0), 0}, 1099 1100 {"prusr_acc_ctl", SRIDX (4, 4, 0), 0}, 1101 {"fucpr", SRIDX (4, 5, 0), 0}, {"fucop_ctl", SRIDX (4, 5, 0), 0}, 1102 1103 {"bpc0", SRIDX (3, 0, 0), 0}, {"dr0", SRIDX (3, 0, 0), 0}, 1104 {"bpc1", SRIDX (3, 0, 1), 0}, {"dr1", SRIDX (3, 0, 1), 0}, 1105 {"bpc2", SRIDX (3, 0, 2), 0}, {"dr2", SRIDX (3, 0, 2), 0}, 1106 {"bpc3", SRIDX (3, 0, 3), 0}, {"dr3", SRIDX (3, 0, 3), 0}, 1107 {"bpc4", SRIDX (3, 0, 4), 0}, {"dr4", SRIDX (3, 0, 4), 0}, 1108 {"bpc5", SRIDX (3, 0, 5), 0}, {"dr5", SRIDX (3, 0, 5), 0}, 1109 {"bpc6", SRIDX (3, 0, 6), 0}, {"dr6", SRIDX (3, 0, 6), 0}, 1110 {"bpc7", SRIDX (3, 0, 7), 0}, {"dr7", SRIDX (3, 0, 7), 0}, 1111 {"bpa0", SRIDX (3, 1, 0), 0}, {"dr8", SRIDX (3, 1, 0), 0}, 1112 {"bpa1", SRIDX (3, 1, 1), 0}, {"dr9", SRIDX (3, 1, 1), 0}, 1113 {"bpa2", SRIDX (3, 1, 2), 0}, {"dr10", SRIDX (3, 1, 2), 0}, 1114 {"bpa3", SRIDX (3, 1, 3), 0}, {"dr11", SRIDX (3, 1, 3), 0}, 1115 {"bpa4", SRIDX (3, 1, 4), 0}, {"dr12", SRIDX (3, 1, 4), 0}, 1116 {"bpa5", SRIDX (3, 1, 5), 0}, {"dr13", SRIDX (3, 1, 5), 0}, 1117 {"bpa6", SRIDX (3, 1, 6), 0}, {"dr14", SRIDX (3, 1, 6), 0}, 1118 {"bpa7", SRIDX (3, 1, 7), 0}, {"dr15", SRIDX (3, 1, 7), 0}, 1119 {"bpam0", SRIDX (3, 2, 0), 0}, {"dr16", SRIDX (3, 2, 0), 0}, 1120 {"bpam1", SRIDX (3, 2, 1), 0}, {"dr17", SRIDX (3, 2, 1), 0}, 1121 {"bpam2", SRIDX (3, 2, 2), 0}, {"dr18", SRIDX (3, 2, 2), 0}, 1122 {"bpam3", SRIDX (3, 2, 3), 0}, {"dr19", SRIDX (3, 2, 3), 0}, 1123 {"bpam4", SRIDX (3, 2, 4), 0}, {"dr20", SRIDX (3, 2, 4), 0}, 1124 {"bpam5", SRIDX (3, 2, 5), 0}, {"dr21", SRIDX (3, 2, 5), 0}, 1125 {"bpam6", SRIDX (3, 2, 6), 0}, {"dr22", SRIDX (3, 2, 6), 0}, 1126 {"bpam7", SRIDX (3, 2, 7), 0}, {"dr23", SRIDX (3, 2, 7), 0}, 1127 {"bpv0", SRIDX (3, 3, 0), 0}, {"dr24", SRIDX (3, 3, 0), 0}, 1128 {"bpv1", SRIDX (3, 3, 1), 0}, {"dr25", SRIDX (3, 3, 1), 0}, 1129 {"bpv2", SRIDX (3, 3, 2), 0}, {"dr26", SRIDX (3, 3, 2), 0}, 1130 {"bpv3", SRIDX (3, 3, 3), 0}, {"dr27", SRIDX (3, 3, 3), 0}, 1131 {"bpv4", SRIDX (3, 3, 4), 0}, {"dr28", SRIDX (3, 3, 4), 0}, 1132 {"bpv5", SRIDX (3, 3, 5), 0}, {"dr29", SRIDX (3, 3, 5), 0}, 1133 {"bpv6", SRIDX (3, 3, 6), 0}, {"dr30", SRIDX (3, 3, 6), 0}, 1134 {"bpv7", SRIDX (3, 3, 7), 0}, {"dr31", SRIDX (3, 3, 7), 0}, 1135 {"bpcid0", SRIDX (3, 4, 0), 0}, {"dr32", SRIDX (3, 4, 0), 0}, 1136 {"bpcid1", SRIDX (3, 4, 1), 0}, {"dr33", SRIDX (3, 4, 1), 0}, 1137 {"bpcid2", SRIDX (3, 4, 2), 0}, {"dr34", SRIDX (3, 4, 2), 0}, 1138 {"bpcid3", SRIDX (3, 4, 3), 0}, {"dr35", SRIDX (3, 4, 3), 0}, 1139 {"bpcid4", SRIDX (3, 4, 4), 0}, {"dr36", SRIDX (3, 4, 4), 0}, 1140 {"bpcid5", SRIDX (3, 4, 5), 0}, {"dr37", SRIDX (3, 4, 5), 0}, 1141 {"bpcid6", SRIDX (3, 4, 6), 0}, {"dr38", SRIDX (3, 4, 6), 0}, 1142 {"bpcid7", SRIDX (3, 4, 7), 0}, {"dr39", SRIDX (3, 4, 7), 0}, 1143 {"edm_cfg", SRIDX (3, 5, 0), 0}, {"dr40", SRIDX (3, 5, 0), 0}, 1144 {"edmsw", SRIDX (3, 6, 0), 0}, {"dr41", SRIDX (3, 6, 0), 0}, 1145 {"edm_ctl", SRIDX (3, 7, 0), 0}, {"dr42", SRIDX (3, 7, 0), 0}, 1146 {"edm_dtr", SRIDX (3, 8, 0), 0}, {"dr43", SRIDX (3, 8, 0), 0}, 1147 {"bpmtc", SRIDX (3, 9, 0), 0}, {"dr44", SRIDX (3, 9, 0), 0}, 1148 {"dimbr", SRIDX (3, 10, 0), 0}, {"dr45", SRIDX (3, 10, 0), 0}, 1149 {"tecr0", SRIDX (3, 14, 0), 0}, {"dr46", SRIDX (3, 14, 0), 0}, 1150 {"tecr1", SRIDX (3, 14, 1), 0}, {"dr47", SRIDX (3, 14, 1), 0}, 1151 {NULL,0 ,0} 1152 }; 1153 1154 const keyword_t keyword_cp[] = 1155 { 1156 {"cp0", 0, 0}, {"cp1", 1, 0}, {"cp2", 2, 0}, {"cp3", 3, 0}, {NULL, 0, 0} 1157 }; 1158 1159 const keyword_t keyword_cpr[] = 1160 { 1161 {"cpr0", 0, 0}, {"cpr1", 1, 0}, {"cpr2", 2, 0}, {"cpr3", 3, 0}, 1162 {"cpr4", 4, 0}, {"cpr5", 5, 0}, {"cpr6", 6, 0}, {"cpr7", 7, 0}, 1163 {"cpr8", 8, 0}, {"cpr9", 9, 0}, {"cpr10", 10, 0}, {"cpr11", 11, 0}, 1164 {"cpr12", 12, 0}, {"cpr13", 13, 0}, {"cpr14", 14, 0}, {"cpr15", 15, 0}, 1165 {"cpr16", 16, 0}, {"cpr17", 17, 0}, {"cpr18", 18, 0}, {"cpr19", 19, 0}, 1166 {"cpr20", 20, 0}, {"cpr21", 21, 0}, {"cpr22", 22, 0}, {"cpr23", 23, 0}, 1167 {"cpr24", 24, 0}, {"cpr25", 25, 0}, {"cpr26", 26, 0}, {"cpr27", 27, 0}, 1168 {"cpr28", 28, 0}, {"cpr29", 29, 0}, {"cpr30", 30, 0}, {"cpr31", 31, 0}, 1169 {NULL, 0, 0} 1170 }; 1171 1172 const keyword_t keyword_fsr[] = 1173 { 1174 {"fs0", 0, 0}, {"fs1", 1, 0}, {"fs2", 2, 0}, {"fs3", 3, 0}, {"fs4", 4, 0}, 1175 {"fs5", 5, 0}, {"fs6", 6, 0}, {"fs7", 7, 0}, {"fs8", 8, 0}, {"fs9", 9, 0}, 1176 {"fs10", 10, 0}, {"fs11", 11, 0}, {"fs12", 12, 0}, {"fs13", 13, 0}, 1177 {"fs14", 14, 0}, {"fs15", 15, 0}, {"fs16", 16, 0}, {"fs17", 17, 0}, 1178 {"fs18", 18, 0}, {"fs19", 19, 0}, {"fs20", 20, 0}, {"fs21", 21, 0}, 1179 {"fs22", 22, 0}, {"fs23", 23, 0}, {"fs24", 24, 0}, {"fs25", 25, 0}, 1180 {"fs26", 26, 0}, {"fs27", 27, 0}, {"fs28", 28, 0}, {"fs29", 29, 0}, 1181 {"fs30", 30, 0}, {"fs31", 31, 0}, {NULL, 0 ,0} 1182 }; 1183 1184 const keyword_t keyword_fdr[] = 1185 { 1186 {"fd0", 0, 0}, {"fd1", 1, 0}, {"fd2", 2, 0}, {"fd3", 3, 0}, {"fd4", 4, 0}, 1187 {"fd5", 5, 0}, {"fd6", 6, 0}, {"fd7", 7, 0}, {"fd8", 8, 0}, {"fd9", 9, 0}, 1188 {"fd10", 10, 0}, {"fd11", 11, 0}, {"fd12", 12, 0}, {"fd13", 13, 0}, 1189 {"fd14", 14, 0}, {"fd15", 15, 0}, {"fd16", 16, 0}, {"fd17", 17, 0}, 1190 {"fd18", 18, 0}, {"fd19", 19, 0}, {"fd20", 20, 0}, {"fd21", 21, 0}, 1191 {"fd22", 22, 0}, {"fd23", 23, 0}, {"fd24", 24, 0}, {"fd25", 25, 0}, 1192 {"fd26", 26, 0}, {"fd27", 27, 0}, {"fd28", 28, 0}, {"fd29", 29, 0}, 1193 {"fd30", 30, 0}, {"fd31", 31, 0}, {NULL, 0, 0} 1194 }; 1195 1196 const keyword_t keyword_abdim[] = 1197 { 1198 {"bi", 0, 0}, {"bim", 1, 0}, {"bd", 2, 0}, {"bdm", 3, 0}, 1199 {"ai", 4, 0}, {"aim", 5, 0}, {"ad", 6, 0}, {"adm", 7, 0}, 1200 {NULL, 0, 0} 1201 }; 1202 1203 const keyword_t keyword_abm[] = 1204 { 1205 {"b", 0, 0}, {"bm", 1, 0}, {"bx", 2, 0}, {"bmx", 3, 0}, 1206 {"a", 4, 0}, {"am", 5, 0}, {"ax", 6, 0}, {"amx", 7, 0}, 1207 {NULL, 0, 0} 1208 }; 1209 1210 static const keyword_t keyword_dtiton[] = 1211 { 1212 {"iton", 1, 0}, {"ton", 3, 0}, {NULL, 0, 0} 1213 }; 1214 1215 static const keyword_t keyword_dtitoff[] = 1216 { 1217 {"itoff", 1, 0}, {"toff", 3, 0}, {NULL, 0, 0} 1218 }; 1219 1220 const keyword_t keyword_dpref_st[] = 1221 { 1222 {"srd", 0, 0}, {"mrd", 1, 0}, {"swr", 2, 0}, {"mwr", 3, 0}, 1223 {"pte", 4, 0}, {"clwr", 5, 0}, {NULL, 0, 0} 1224 }; 1225 1226 /* CCTL Ra, SubType. */ 1227 static const keyword_t keyword_cctl_st0[] = 1228 { 1229 {"l1d_ix_inval", 0X0, 0}, {"l1d_ix_wb", 0X1, 0}, {"l1d_ix_wbinval", 0X2, 0}, 1230 {"l1d_va_fillck", 0XB, 0}, {"l1d_va_ulck", 0XC, 0}, {"l1i_ix_inval", 0X10, 0}, 1231 {"l1i_va_fillck", 0X1B, 0}, {"l1i_va_ulck", 0X1C, 0}, 1232 {NULL, 0, 0} 1233 }; 1234 1235 /* CCTL Ra, SubType, level. */ 1236 static const keyword_t keyword_cctl_st1[] = 1237 { 1238 {"l1d_va_inval", 0X8, 0}, {"l1d_va_wb", 0X9, 0}, 1239 {"l1d_va_wbinval", 0XA, 0}, {"l1i_va_inval", 0X18, 0}, 1240 {NULL, 0, 0} 1241 }; 1242 1243 /* CCTL Rt, Ra, SubType. */ 1244 static const keyword_t keyword_cctl_st2[] = 1245 { 1246 {"l1d_ix_rtag", 0X3, 0}, {"l1d_ix_rwd", 0X4, 0}, 1247 {"l1i_ix_rtag", 0X13, 0}, {"l1i_ix_rwd", 0X14, 0}, 1248 {NULL, 0, 0} 1249 }; 1250 1251 /* CCTL Rb, Ra, SubType. */ 1252 static const keyword_t keyword_cctl_st3[] = 1253 { 1254 {"l1d_ix_wtag", 0X5, 0}, {"l1d_ix_wwd", 0X6, 0}, 1255 {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0}, 1256 {NULL, 0, 0} 1257 }; 1258 1259 /* CCTL L1D_INVALALL. */ 1260 static const keyword_t keyword_cctl_st4[] = 1261 { 1262 {"l1d_invalall", 0x7, 0}, {NULL, 0, 0} 1263 }; 1264 1265 /* CCTL L1D_WBALL, level. */ 1266 static const keyword_t keyword_cctl_st5[] = 1267 { 1268 {"l1d_wball", 0xf, 0}, {NULL, 0, 0} 1269 }; 1270 1271 const keyword_t keyword_cctl_lv[] = 1272 { 1273 {"1level", 0, 0}, {"alevel", 1, 0}, {"0", 0, 0}, {"1", 1, 0}, 1274 {NULL, 0, 0}, 1275 }; 1276 1277 static const keyword_t keyword_tlbop_st[] = 1278 { 1279 {"targetread", 0, 0}, {"trd", 0, 0}, 1280 {"targetwrite", 1, 0}, {"twr", 1, 0}, 1281 {"rwrite", 2, 0}, {"rwr", 2, 0}, 1282 {"rwritelock", 3, 0}, {"rwlk", 3, 0}, 1283 {"unlock", 4, 0}, {"unlk", 4, 0}, 1284 {"invalidate", 6, 0}, {"inv", 6, 0}, 1285 {NULL, 0, 0}, 1286 }; 1287 1288 const keyword_t keyword_standby_st[] = 1289 { 1290 {"no_wake_grant", 0, 0}, 1291 {"wake_grant", 1, 0}, 1292 {"wait_done", 2, 0}, 1293 {"0", 0, 0}, 1294 {"1", 1, 0}, 1295 {"2", 2, 0}, 1296 {"3", 3, 0}, 1297 {NULL, 0, 0}, 1298 }; 1299 1300 const keyword_t keyword_msync_st[] = 1301 { 1302 {"all", 0, 0}, {"store", 1, 0}, 1303 {NULL, 0, 0} 1304 }; 1305 1306 const keyword_t keyword_im5_i[] = 1307 { 1308 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0}, 1309 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0}, 1310 {NULL, 0, 0} 1311 }; 1312 1313 const keyword_t keyword_im5_m[] = 1314 { 1315 {"m0", 0, 0}, {"m1", 1, 0}, {"m2", 2, 0}, {"m3", 3, 0}, 1316 {"m4", 4, 0}, {"m5", 5, 0}, {"m6", 6, 0}, {"m7", 7, 0}, 1317 {NULL, 0, 0} 1318 }; 1319 1320 const keyword_t keyword_accumulator[] = 1321 { 1322 {"d0.lo", 0, 0}, {"d0.hi", 1, 0}, {"d1.lo", 2, 0}, {"d1.hi", 3, 0}, 1323 {NULL, 0, 0} 1324 }; 1325 1326 const keyword_t keyword_aridx[] = 1327 { 1328 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0}, 1329 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0}, 1330 {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0}, 1331 {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0}, 1332 {"d0.l24", 16, 0}, {"d1.l24", 17, 0}, 1333 {"shft_ctl0", 18, 0}, {"shft_ctl1", 19, 0}, 1334 {"lb", 24, 0}, {"le", 25, 0}, {"lc", 26, 0}, {"adm_vbase", 27, 0}, 1335 {NULL, 0, 0} 1336 }; 1337 1338 const keyword_t keyword_aridx2[] = 1339 { 1340 {"cbb0", 0, 0}, {"cbb1", 1, 0}, {"cbb2", 2, 0}, {"cbb3", 3, 0}, 1341 {"cbe0", 4, 0}, {"cbe1", 5, 0}, {"cbe2", 6, 0}, {"cbe3", 7, 0}, 1342 {"cb_ctl", 31, 0}, 1343 {NULL, 0, 0} 1344 }; 1345 1346 const keyword_t keyword_aridxi[] = 1347 { 1348 {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0}, 1349 {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0}, 1350 {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0}, 1351 {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0}, 1352 {NULL, 0, 0} 1353 }; 1354 1355 const keyword_t *keywords[_HW_LAST] = 1356 { 1357 keyword_gpr, keyword_usr, keyword_dxr, keyword_sr, keyword_fsr, 1358 keyword_fdr, keyword_cp, keyword_cpr, keyword_abdim, keyword_abm, 1359 keyword_dtiton, keyword_dtitoff, keyword_dpref_st, 1360 keyword_cctl_st0, keyword_cctl_st1, keyword_cctl_st2, 1361 keyword_cctl_st3, keyword_cctl_st4, keyword_cctl_st5, 1362 keyword_cctl_lv, keyword_tlbop_st, keyword_standby_st, 1363 keyword_msync_st, 1364 keyword_im5_i, keyword_im5_m, 1365 keyword_accumulator, keyword_aridx, keyword_aridx2, keyword_aridxi 1366 }; 1367 1368 /* Hash table for syntax lex. */ 1370 static htab_t field_htab; 1371 /* Hash table for opcodes. */ 1372 static htab_t opcode_htab; 1373 /* Hash table for hardware resources. */ 1374 static htab_t hw_ktabs[_HW_LAST]; 1375 1376 static hashval_t 1377 htab_hash_hash (const void *p) 1378 { 1379 struct nds32_hash_entry *h = (struct nds32_hash_entry *) p; 1380 1381 return htab_hash_string (h->name); 1382 } 1383 1384 static int 1385 htab_hash_eq (const void *p, const void *q) 1386 { 1387 struct nds32_hash_entry *h = (struct nds32_hash_entry *) p; 1388 const char *name = (const char *) q; 1389 1390 return strcmp (name, h->name) == 0; 1391 } 1392 1393 /* Build a hash table for array BASE. Each element is in size of SIZE, 1395 and it's first element is a pointer to the key of string. 1396 It stops inserting elements until reach an NULL key. */ 1397 1398 static htab_t 1399 build_hash_table (const void *base, size_t size) 1400 { 1401 htab_t htab; 1402 hashval_t hash; 1403 const char *p; 1404 1405 htab = htab_create_alloc (128, htab_hash_hash, htab_hash_eq, 1406 NULL, xcalloc, free); 1407 1408 p = base; 1409 while (1) 1410 { 1411 struct nds32_hash_entry **slot; 1412 struct nds32_hash_entry *h; 1413 1414 h = (struct nds32_hash_entry *) p; 1415 1416 if (h->name == NULL) 1417 break; 1418 1419 hash = htab_hash_string (h->name); 1420 slot = (struct nds32_hash_entry **) 1421 htab_find_slot_with_hash (htab, h->name, hash, INSERT); 1422 1423 assert (slot != NULL && *slot == NULL); 1424 1425 *slot = h; 1426 1427 p = p + size; 1428 } 1429 1430 return htab; 1431 } 1432 1433 /* Build the syntax for a given opcode OPC. It parses the string 1434 pointed by INSTRUCTION and store the result on SYNTAX, so 1435 when we assemble an instruction, we don't have to parse the syntax 1436 again. */ 1437 1438 static void 1439 build_opcode_syntax (struct nds32_opcode *opc) 1440 { 1441 char odstr[MAX_LEX_LEN]; 1442 const char *str; 1443 const char *end; 1444 lex_t *plex; 1445 int len; 1446 hashval_t hash; 1447 field_t *fd; 1448 int opt = 0; 1449 1450 /* Check whether it has been initialized. */ 1451 if (opc->syntax) 1452 return; 1453 1454 opc->syntax = xmalloc (MAX_LEX_NUM * sizeof (lex_t)); 1455 1456 str = opc->instruction; 1457 plex = opc->syntax; 1458 while (*str) 1459 { 1460 int fidx; 1461 1462 switch (*str) 1463 { 1464 case '%': 1465 *plex = SYN_INPUT; 1466 break; 1467 case '=': 1468 *plex = SYN_OUTPUT; 1469 break; 1470 case '&': 1471 *plex = SYN_INPUT | SYN_OUTPUT; 1472 break; 1473 case '{': 1474 *plex++ = SYN_LOPT; 1475 opt++; 1476 str++; 1477 continue; 1478 case '}': 1479 *plex++ = SYN_ROPT; 1480 str++; 1481 continue; 1482 default: 1483 *plex++ = *str++; 1484 continue; 1485 } 1486 str++; 1487 1488 /* Extract operand. */ 1489 end = str; 1490 while (ISALNUM (*end) || *end == '_') 1491 end++; 1492 len = end - str; 1493 memcpy (odstr, str, len); 1494 odstr[len] = '\0'; 1495 1496 hash = htab_hash_string (odstr); 1497 fd = (field_t *) htab_find_with_hash (field_htab, odstr, hash); 1498 fidx = fd - operand_fields; 1499 1500 if (fd == NULL) 1501 { 1502 fprintf (stderr, "Internal error: Unknown operand, %s\n", str); 1503 } 1504 assert (fd && fidx >= 0 && fidx < (int) ARRAY_SIZE (operand_fields)); 1505 *plex |= LEX_SET_FIELD (fidx); 1506 1507 str += len; 1508 plex++; 1509 } 1510 1511 *plex = 0; 1512 opc->variant = opt; 1513 return; 1514 } 1515 1516 /* Initialize the assembler. It must be called before assembling. */ 1517 1518 void 1519 nds32_asm_init (nds32_asm_desc_t *pdesc, int flags) 1520 { 1521 int i; 1522 hashval_t hash; 1523 1524 pdesc->flags = flags; 1525 pdesc->mach = flags & NASM_OPEN_ARCH_MASK; 1526 1527 /* Build keyword tables. */ 1528 field_htab = build_hash_table (operand_fields, 1529 sizeof (operand_fields[0])); 1530 1531 for (i = 0; i < _HW_LAST; i++) 1532 hw_ktabs[i] = build_hash_table (keywords[i], sizeof (keyword_t)); 1533 1534 /* Build opcode table. */ 1535 opcode_htab = htab_create_alloc (128, htab_hash_hash, htab_hash_eq, 1536 NULL, xcalloc, free); 1537 1538 for (i = 0; i < (int) ARRAY_SIZE (nds32_opcodes); i++) 1539 { 1540 struct nds32_opcode **slot; 1541 struct nds32_opcode *opc; 1542 1543 opc = &nds32_opcodes[i]; 1544 if ((opc->opcode != NULL) && (opc->instruction != NULL)) 1545 { 1546 hash = htab_hash_string (opc->opcode); 1547 slot = (struct nds32_opcode **) 1548 htab_find_slot_with_hash (opcode_htab, opc->opcode, hash, INSERT); 1549 1550 #define NDS32_PREINIT_SYNTAX 1551 #if defined (NDS32_PREINIT_SYNTAX) 1552 /* Initial SYNTAX when build opcode table, so bug in syntax can be 1553 found when initialized rather than used. */ 1554 build_opcode_syntax (opc); 1555 #endif 1556 1557 if (*slot == NULL) 1558 { 1559 /* This is the new one. */ 1560 *slot = opc; 1561 } 1562 else 1563 { 1564 /* Already exists. Append to the list. */ 1565 opc = *slot; 1566 while (opc->next) 1567 opc = opc->next; 1568 opc->next = &nds32_opcodes[i]; 1569 } 1570 } 1571 } 1572 } 1573 1574 /* Parse the input and store operand keyword string in ODSTR. 1575 This function is only used for parsing keywords, 1576 HW_INT/HW_UINT are parsed parse_operand callback handler. */ 1577 1578 static char * 1579 parse_to_delimiter (char *str, char odstr[MAX_KEYWORD_LEN]) 1580 { 1581 char *outp = odstr; 1582 1583 while (ISALNUM (*str) || *str == '.' || *str == '_') 1584 *outp++ = TOLOWER (*str++); 1585 1586 *outp = '\0'; 1587 return str; 1588 } 1589 1590 /* Parse the operand of lmw/smw/lmwa/smwa. */ 1591 1592 static int 1593 parse_re (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1594 struct nds32_asm_insn *pinsn, char **pstr, int64_t *value) 1595 { 1596 char *end = *pstr; 1597 char odstr[MAX_KEYWORD_LEN]; 1598 keyword_t *k; 1599 hashval_t hash; 1600 1601 if (*end == '$') 1602 end++; 1603 end = parse_to_delimiter (end, odstr); 1604 1605 hash = htab_hash_string (odstr); 1606 k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash); 1607 1608 if (k == NULL) 1609 return NASM_ERR_OPERAND; 1610 1611 if (__GF (pinsn->insn, 20, 5) > (unsigned int) k->value) 1612 return NASM_ERR_OPERAND; 1613 1614 *value = k->value; 1615 *pstr = end; 1616 return NASM_R_CONST; 1617 } 1618 1619 /* Parse the operand of push25/pop25. */ 1620 1621 static int 1622 parse_re2 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1623 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1624 char **pstr, int64_t *value) 1625 { 1626 char *end = *pstr; 1627 char odstr[MAX_KEYWORD_LEN]; 1628 keyword_t *k; 1629 hashval_t hash; 1630 1631 if (*end == '$') 1632 end++; 1633 end = parse_to_delimiter (end, odstr); 1634 1635 hash = htab_hash_string (odstr); 1636 k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash); 1637 1638 if (k == NULL) 1639 return NASM_ERR_OPERAND; 1640 1641 if (k->value == 6) 1642 *value = 0; 1643 else if (k->value == 8) 1644 *value = 1; 1645 else if (k->value == 10) 1646 *value = 2; 1647 else if (k->value == 14) 1648 *value = 3; 1649 else 1650 return NASM_ERR_OPERAND; 1651 1652 *pstr = end; 1653 return NASM_R_CONST; 1654 } 1655 1656 /* Parse the operand of lwi45.fe. */ 1657 1658 static int 1659 parse_fe5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn, 1660 char **pstr, int64_t *value) 1661 { 1662 int r; 1663 1664 r = pdesc->parse_operand (pdesc, pinsn, pstr, value); 1665 if (r != NASM_R_CONST) 1666 return NASM_ERR_OPERAND; 1667 1668 /* 128 == 32 << 2. Leave the shift to parse_opreand, 1669 so it can check whether it is a multiple of 4. */ 1670 *value = 128 + *value; 1671 return r; 1672 } 1673 1674 /* Parse the operand of movpi45. */ 1675 1676 static int 1677 parse_pi5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn, 1678 char **pstr, int64_t *value) 1679 { 1680 int r; 1681 1682 r = pdesc->parse_operand (pdesc, pinsn, pstr, value); 1683 if (r != NASM_R_CONST) 1684 return NASM_ERR_OPERAND; 1685 1686 *value -= 16; 1687 return r; 1688 } 1689 1690 static int aext_a30b20 = 0; 1691 static int aext_rte = 0; 1692 static int aext_im5_ip = 0; 1693 static int aext_im6_ip = 0; 1694 /* Parse the operand of audio ext. */ 1695 static int 1696 parse_aext_reg (char **pstr, int *value, int hw_res) 1697 { 1698 char *end = *pstr; 1699 char odstr[MAX_KEYWORD_LEN]; 1700 keyword_t *k; 1701 hashval_t hash; 1702 1703 if (*end == '$') 1704 end++; 1705 end = parse_to_delimiter (end, odstr); 1706 1707 hash = htab_hash_string (odstr); 1708 k = htab_find_with_hash (hw_ktabs[hw_res], odstr, hash); 1709 1710 if (k == NULL) 1711 return NASM_ERR_OPERAND; 1712 1713 *value = k->value; 1714 *pstr = end; 1715 return NASM_R_CONST; 1716 } 1717 1718 static int 1719 parse_a30b20 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1720 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1721 char **pstr, int64_t *value) 1722 { 1723 int rt_value, ret; 1724 1725 ret = parse_aext_reg (pstr, &rt_value, HW_GPR); 1726 1727 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)) 1728 return NASM_ERR_OPERAND; 1729 1730 *value = rt_value; 1731 aext_a30b20 = rt_value; 1732 return NASM_R_CONST; 1733 } 1734 1735 static int 1736 parse_rt21 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1737 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1738 char **pstr, int64_t *value) 1739 { 1740 int rt_value, ret, tmp_value, tmp1, tmp2; 1741 1742 ret = parse_aext_reg (pstr, &rt_value, HW_GPR); 1743 1744 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)) 1745 return NASM_ERR_OPERAND; 1746 tmp1 = (aext_a30b20 & 0x08); 1747 tmp2 = (rt_value & 0x08); 1748 if (tmp1 != tmp2) 1749 return NASM_ERR_OPERAND; 1750 1751 /* Rt=CONCAT(c, t21, t0), t21:bit11-10, t0:bit5. */ 1752 tmp_value = (rt_value & 0x06) << 4; 1753 tmp_value |= (rt_value & 0x01); 1754 *value = tmp_value; 1755 return NASM_R_CONST; 1756 } 1757 1758 static int 1759 parse_rte_start (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1760 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1761 char **pstr, int64_t *value) 1762 { 1763 int rt_value, ret, tmp1, tmp2; 1764 1765 ret = parse_aext_reg (pstr, &rt_value, HW_GPR); 1766 1767 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15) 1768 || (rt_value & 0x01)) 1769 return NASM_ERR_OPERAND; 1770 tmp1 = (aext_a30b20 & 0x08); 1771 tmp2 = (rt_value & 0x08); 1772 if (tmp1 != tmp2) 1773 return NASM_ERR_OPERAND; 1774 1775 aext_rte = rt_value; 1776 /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */ 1777 rt_value = (rt_value & 0x06) << 4; 1778 *value = rt_value; 1779 return NASM_R_CONST; 1780 } 1781 1782 static int 1783 parse_rte_end (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1784 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1785 char **pstr, int64_t *value) 1786 { 1787 int rt_value, ret, tmp1, tmp2; 1788 1789 ret = parse_aext_reg (pstr, &rt_value, HW_GPR); 1790 if ((ret == NASM_ERR_OPERAND) || (rt_value > 15) 1791 || ((rt_value & 0x01) == 0) 1792 || (rt_value != (aext_rte + 1))) 1793 return NASM_ERR_OPERAND; 1794 tmp1 = (aext_a30b20 & 0x08); 1795 tmp2 = (rt_value & 0x08); 1796 if (tmp1 != tmp2) 1797 return NASM_ERR_OPERAND; 1798 /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */ 1799 rt_value = (rt_value & 0x06) << 4; 1800 *value = rt_value; 1801 return NASM_R_CONST; 1802 } 1803 1804 static int 1805 parse_rte69_start (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1806 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1807 char **pstr, int64_t *value) 1808 { 1809 int rt_value, ret; 1810 1811 ret = parse_aext_reg (pstr, &rt_value, HW_GPR); 1812 if ((ret == NASM_ERR_OPERAND) 1813 || (rt_value & 0x01)) 1814 return NASM_ERR_OPERAND; 1815 aext_rte = rt_value; 1816 rt_value = (rt_value >> 1); 1817 *value = rt_value; 1818 return NASM_R_CONST; 1819 } 1820 1821 static int 1822 parse_rte69_end (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1823 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1824 char **pstr, int64_t *value) 1825 { 1826 int rt_value, ret; 1827 1828 ret = parse_aext_reg (pstr, &rt_value, HW_GPR); 1829 if ((ret == NASM_ERR_OPERAND) 1830 || ((rt_value & 0x01) == 0) 1831 || (rt_value != (aext_rte + 1))) 1832 return NASM_ERR_OPERAND; 1833 aext_rte = rt_value; 1834 rt_value = (rt_value >> 1); 1835 *value = rt_value; 1836 return NASM_R_CONST; 1837 } 1838 1839 static int 1840 parse_im5_ip (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1841 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1842 char **pstr, int64_t *value) 1843 { 1844 int rt_value, ret, new_value; 1845 1846 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I); 1847 if (ret == NASM_ERR_OPERAND) 1848 return NASM_ERR_OPERAND; 1849 /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */ 1850 new_value = (rt_value & 0x04) << 2; 1851 new_value |= (rt_value & 0x03); 1852 *value = new_value; 1853 aext_im5_ip = new_value; 1854 return NASM_R_CONST; 1855 } 1856 1857 static int 1858 parse_im5_mr (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1859 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1860 char **pstr, int64_t *value) 1861 { 1862 int rt_value, ret, new_value, tmp1, tmp2; 1863 1864 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M); 1865 if (ret == NASM_ERR_OPERAND) 1866 return NASM_ERR_OPERAND; 1867 /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */ 1868 new_value = (rt_value & 0x07) << 2; 1869 tmp1 = (aext_im5_ip & 0x10); 1870 tmp2 = (new_value & 0x10); 1871 if (tmp1 != tmp2) 1872 return NASM_ERR_OPERAND; 1873 *value = new_value; 1874 return NASM_R_CONST; 1875 } 1876 1877 static int 1878 parse_im6_ip (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1879 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1880 char **pstr, int64_t *value) 1881 { 1882 int rt_value, ret; 1883 1884 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I); 1885 if ((ret == NASM_ERR_OPERAND) || (rt_value > 3)) 1886 return NASM_ERR_OPERAND; 1887 /* p = 0.bit[1:0]. */ 1888 aext_im6_ip = rt_value; 1889 *value = aext_im6_ip; 1890 return NASM_R_CONST; 1891 } 1892 1893 static int 1894 parse_im6_iq (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1895 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1896 char **pstr, int64_t *value) 1897 { 1898 int rt_value, ret; 1899 1900 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I); 1901 if ((ret == NASM_ERR_OPERAND) || (rt_value < 4)) 1902 return NASM_ERR_OPERAND; 1903 /* q = 1.bit[1:0]. */ 1904 if ((rt_value & 0x03) != aext_im6_ip) 1905 return NASM_ERR_OPERAND; 1906 *value = aext_im6_ip; 1907 return NASM_R_CONST; 1908 } 1909 1910 static int 1911 parse_im6_mr (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1912 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1913 char **pstr, int64_t *value) 1914 { 1915 int rt_value, ret; 1916 1917 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M); 1918 if ((ret == NASM_ERR_OPERAND) || (rt_value > 3)) 1919 return NASM_ERR_OPERAND; 1920 /* r = 0.bit[3:2]. */ 1921 *value = (rt_value & 0x03); 1922 return NASM_R_CONST; 1923 } 1924 1925 static int 1926 parse_im6_ms (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, 1927 struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, 1928 char **pstr, int64_t *value) 1929 { 1930 int rt_value, ret; 1931 1932 ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M); 1933 if ((ret == NASM_ERR_OPERAND) || (rt_value < 4)) 1934 return NASM_ERR_OPERAND; 1935 /* s = 1.bit[5:4]. */ 1936 *value = (rt_value & 0x03); 1937 return NASM_R_CONST; 1938 } 1939 1940 /* Generic operand parse base on the information provided by the field. */ 1941 1942 static int 1943 parse_operand (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, 1944 char **str, int syn) 1945 { 1946 char odstr[MAX_KEYWORD_LEN]; 1947 char *end; 1948 hashval_t hash; 1949 const field_t *fld = &LEX_GET_FIELD (syn); 1950 keyword_t *k; 1951 int64_t value; 1952 int r; 1953 uint64_t modifier = 0; 1954 1955 end = *str; 1956 1957 if (fld->parse) 1958 { 1959 r = fld->parse (pdesc, pinsn, &end, &value); 1960 if (r == NASM_ERR_OPERAND) 1961 { 1962 pdesc->result = NASM_ERR_OPERAND; 1963 return 0; 1964 } 1965 goto done; 1966 } 1967 1968 if (fld->hw_res < _HW_LAST) 1969 { 1970 /* Parse the operand in assembly code. */ 1971 if (*end == '$') 1972 end++; 1973 end = parse_to_delimiter (end, odstr); 1974 1975 hash = htab_hash_string (odstr); 1976 k = htab_find_with_hash (hw_ktabs[fld->hw_res], odstr, hash); 1977 1978 if (k == NULL) 1979 { 1980 pdesc->result = NASM_ERR_OPERAND; 1981 return 0; 1982 } 1983 1984 if (fld->hw_res == HW_GPR && (pdesc->flags & NASM_OPEN_REDUCED_REG) 1985 && (k->attr & ATTR (RDREG)) == 0) 1986 { 1987 /* Register not allowed in reduced register. */ 1988 pdesc->result = NASM_ERR_REG_REDUCED; 1989 return 0; 1990 } 1991 1992 if (fld->hw_res == HW_GPR) 1993 { 1994 if (syn & SYN_INPUT) 1995 pinsn->defuse |= USE_REG (k->value); 1996 if (syn & SYN_OUTPUT) 1997 pinsn->defuse |= DEF_REG (k->value); 1998 } 1999 2000 value = k->value; 2001 if (fld->hw_res == HW_GPR && (fld->bitsize + fld->shift) == 4) 2002 value = nds32_r54map[value]; 2003 } 2004 else if (fld->hw_res == HW_INT || fld->hw_res == HW_UINT) 2005 { 2006 if (*end == '#') 2007 end++; 2008 2009 /* Handle modifiers. Do we need to make a table for modifiers? 2010 Do we need to check unknown modifier? */ 2011 if (strncasecmp (end, "hi20(", 5) == 0) 2012 { 2013 modifier |= NASM_ATTR_HI20; 2014 end += 5; 2015 } 2016 else if (strncasecmp (end, "lo12(", 5) == 0) 2017 { 2018 modifier |= NASM_ATTR_LO12; 2019 end += 5; 2020 } 2021 else if (strncasecmp (end, "lo20(", 5) == 0) 2022 { 2023 /* e.g., movi. */ 2024 modifier |= NASM_ATTR_LO20; 2025 end += 5; 2026 } 2027 2028 r = pdesc->parse_operand (pdesc, pinsn, &end, &value); 2029 if (modifier) 2030 { 2031 /* Consume the ')' of modifier. */ 2032 end++; 2033 pinsn->attr |= modifier; 2034 } 2035 2036 switch (r) 2037 { 2038 case NASM_R_ILLEGAL: 2039 pdesc->result = NASM_ERR_OPERAND; 2040 return 0; 2041 case NASM_R_SYMBOL: 2042 /* This field needs special fix-up. */ 2043 pinsn->field = fld; 2044 break; 2045 case NASM_R_CONST: 2046 if (modifier & NASM_ATTR_HI20) 2047 value = (value >> 12) & 0xfffff; 2048 else if (modifier & NASM_ATTR_LO12) 2049 value = value & 0xfff; 2050 else if (modifier & NASM_ATTR_LO20) 2051 value = value & 0xfffff; 2052 break; 2053 default: 2054 fprintf (stderr, "Internal error: Don't know how to handle " 2055 "parsing results.\n"); 2056 abort (); 2057 } 2058 } 2059 else 2060 { 2061 fprintf (stderr, "Internal error: Unknown hardware resource.\n"); 2062 abort (); 2063 } 2064 2065 done: 2066 /* Don't silently discarding bits. */ 2067 if (value & __MASK (fld->shift)) 2068 { 2069 pdesc->result = NASM_ERR_OUT_OF_RANGE; 2070 return 0; 2071 } 2072 2073 /* Check the range of signed or unsigned result. */ 2074 if (fld->hw_res != HW_INT && ((int32_t) value >> (fld->bitsize + fld->shift))) 2075 { 2076 pdesc->result = NASM_ERR_OUT_OF_RANGE; 2077 return 0; 2078 } 2079 else if (fld->hw_res == HW_INT) 2080 { 2081 /* Sign-ext the value. */ 2082 if (((value >> 32) == 0) && (value & 0x80000000)) 2083 value |= (int64_t) -1 << 31; 2084 2085 2086 /* Shift the value to positive domain. */ 2087 if ((value + (1 << (fld->bitsize + fld->shift - 1))) 2088 >> (fld->bitsize + fld->shift)) 2089 { 2090 pdesc->result = NASM_ERR_OUT_OF_RANGE; 2091 return 0; 2092 } 2093 } 2094 2095 pinsn->insn |= 2096 (((value >> fld->shift) & __MASK (fld->bitsize)) << fld->bitpos); 2097 *str = end; 2098 return 1; 2099 } 2100 2101 /* Try to parse an instruction string based on opcode syntax. */ 2102 2103 static int 2104 parse_insn (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, 2105 char *str, struct nds32_opcode *opc) 2106 { 2107 int variant = 0; 2108 char *p = NULL; 2109 2110 /* A syntax may has optional operands, so we have to try each possible 2111 combination to see if the input is accepted. In order to do so, 2112 bit-N represent whether optional-operand-N is used in this combination. 2113 That is, if bit-N is set, optional-operand-N is not used. 2114 2115 For example, there are 2 optional operands in this syntax, 2116 2117 "a{,b}{,c}" 2118 2119 we can try it 4 times (i.e., 1 << 2) 2120 2121 0 (b00): "a,b,c" 2122 1 (b01): "a,c" 2123 2 (b10): "a,b" 2124 3 (b11): "a" 2125 */ 2126 2127 /* The outer do-while loop is used to try each possible optional 2128 operand combination, and VARIANT is the bit mask. The inner loop 2129 iterates each lexeme in the syntax. */ 2130 2131 do 2132 { 2133 /* OPT is the number of optional operands we've seen. */ 2134 int opt = 0; 2135 lex_t *plex; 2136 2137 /* PLEX is the syntax iterator and P is the iterator for input 2138 string. */ 2139 plex = opc->syntax; 2140 p = str; 2141 /* Initial the base value. */ 2142 pinsn->insn = opc->value; 2143 2144 while (*plex) 2145 { 2146 if (IS_LEX_CHAR (*plex)) 2147 { 2148 /* If it's a plain char, just compare it. */ 2149 if (LEX_CHAR (*plex) != TOLOWER (*p)) 2150 { 2151 if (LEX_CHAR (*plex) == '+' && TOLOWER (*p) == '-') 2152 { 2153 /* We don't define minus format for some signed 2154 immediate case, so ignoring '+' here to parse 2155 negative value eazily. Besides, the minus format 2156 can not support for instruction with relocation. 2157 Ex: lwi $r0, [$r0 + imm] */ 2158 plex++; 2159 continue; 2160 } 2161 pdesc->result = NASM_ERR_SYNTAX; 2162 goto reject; 2163 } 2164 p++; 2165 } 2166 else if (*plex & SYN_LOPT) 2167 { 2168 /* If it's '{' and it's not used in this iteration, 2169 just skip the whole optional operand. */ 2170 if ((1 << (opt++)) & variant) 2171 { 2172 while ((*plex & SYN_ROPT) == 0) 2173 plex++; 2174 } 2175 } 2176 else if (*plex & SYN_ROPT) 2177 { 2178 /* ignore. */ 2179 } 2180 else 2181 { 2182 /* If it's a operand, parse the input operand from input. */ 2183 if (!parse_operand (pdesc, pinsn, &p, *plex)) 2184 goto reject; 2185 } 2186 plex++; 2187 } 2188 2189 /* Check whether this syntax is accepted. */ 2190 if (*plex == 0 && (*p == '\0' || *p == '!' || *p == '#')) 2191 return 1; 2192 2193 reject: 2194 /* If not accepted, try another combination. */ 2195 variant++; 2196 } 2197 while (variant < (1 << opc->variant)); 2198 2199 return 0; 2200 } 2201 2202 void 2203 nds32_assemble (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, 2204 char *str) 2205 { 2206 struct nds32_opcode *opc; 2207 char *s; 2208 char *mnemoic; 2209 char *dot; 2210 hashval_t hash; 2211 2212 /* Duplicate the string, so we can modify it for convenience. */ 2213 s = strdup (str); 2214 mnemoic = s; 2215 str = s; 2216 2217 /* Find opcode mnemoic. */ 2218 while (*s != ' ' && *s != '\t' && *s != '\0') 2219 s++; 2220 if (*s != '\0') 2221 *s++ = '\0'; 2222 dot = strchr (mnemoic, '.'); 2223 2224 retry_dot: 2225 /* Lookup the opcode syntax. */ 2226 hash = htab_hash_string (mnemoic); 2227 opc = (struct nds32_opcode *) 2228 htab_find_with_hash (opcode_htab, mnemoic, hash); 2229 2230 /* If we cannot find a match syntax, try it again without `.'. 2231 For example, try "lmw.adm" first and then try "lmw" again. */ 2232 if (opc == NULL && dot != NULL) 2233 { 2234 *dot = '\0'; 2235 s[-1] = ' '; 2236 s = dot + 1; 2237 dot = NULL; 2238 goto retry_dot; 2239 } 2240 else if (opc == NULL) 2241 { 2242 pdesc->result = NASM_ERR_UNKNOWN_OP; 2243 goto out; 2244 } 2245 2246 /* There may be multiple syntaxes for a given opcode. 2247 Try each one until a match is found. */ 2248 for (; opc; opc = opc->next) 2249 { 2250 /* Build opcode syntax, if it's not been initialized yet. */ 2251 if (opc->syntax == NULL) 2252 build_opcode_syntax (opc); 2253 2254 /* Reset status before assemble. */ 2255 pinsn->defuse = opc->defuse; 2256 pinsn->insn = 0; 2257 pinsn->field = NULL; 2258 /* Use opcode attributes to initial instruction attributes. */ 2259 pinsn->attr = opc->attr; 2260 if (parse_insn (pdesc, pinsn, s, opc)) 2261 break; 2262 } 2263 2264 pinsn->opcode = opc; 2265 if (opc == NULL) 2266 { 2267 pdesc->result = NASM_ERR_SYNTAX; 2268 goto out; 2269 } 2270 2271 /* A matched opcode is found. Write the result to instruction buffer. */ 2272 pdesc->result = NASM_OK; 2273 2274 out: 2275 free (str); 2276 } 2277
