1 /* tc-m68k.c -- Assemble for the m68k family 2 Copyright (C) 1987-2014 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "obstack.h" 24 #include "subsegs.h" 25 #include "dwarf2dbg.h" 26 #include "dw2gencfi.h" 27 28 #include "opcode/m68k.h" 29 #include "m68k-parse.h" 30 31 #if defined (OBJ_ELF) 32 #include "elf/m68k.h" 33 #endif 34 35 #ifdef M68KCOFF 36 #include "obj-coff.h" 37 #endif 38 39 #ifdef OBJ_ELF 40 static void m68k_elf_cons (int); 41 #endif 42 43 /* This string holds the chars that always start a comment. If the 44 pre-processor is disabled, these aren't very useful. The macro 45 tc_comment_chars points to this. We use this, rather than the 46 usual comment_chars, so that the --bitwise-or option will work. */ 47 #if defined (TE_SVR4) || defined (TE_DELTA) 48 const char *m68k_comment_chars = "|#"; 49 #else 50 const char *m68k_comment_chars = "|"; 51 #endif 52 53 /* This array holds the chars that only start a comment at the beginning of 54 a line. If the line seems to have the form '# 123 filename' 55 .line and .file directives will appear in the pre-processed output */ 56 /* Note that input_file.c hand checks for '#' at the beginning of the 57 first line of the input file. This is because the compiler outputs 58 #NO_APP at the beginning of its output. */ 59 /* Also note that comments like this one will always work. */ 60 const char line_comment_chars[] = "#*"; 61 62 const char line_separator_chars[] = ";"; 63 64 /* Chars that can be used to separate mant from exp in floating point nums. */ 65 const char EXP_CHARS[] = "eE"; 66 67 /* Chars that mean this number is a floating point constant, as 68 in "0f12.456" or "0d1.2345e12". */ 69 70 const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 71 72 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 73 changed in read.c . Ideally it shouldn't have to know about it at all, 74 but nothing is ideal around here. */ 75 76 /* Are we trying to generate PIC code? If so, absolute references 77 ought to be made into linkage table references or pc-relative 78 references. Not implemented. For ELF there are other means 79 to denote pic relocations. */ 80 int flag_want_pic; 81 82 static int flag_short_refs; /* -l option. */ 83 static int flag_long_jumps; /* -S option. */ 84 static int flag_keep_pcrel; /* --pcrel option. */ 85 86 #ifdef REGISTER_PREFIX_OPTIONAL 87 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 88 #else 89 int flag_reg_prefix_optional; 90 #endif 91 92 /* Whether --register-prefix-optional was used on the command line. */ 93 static int reg_prefix_optional_seen; 94 95 /* The floating point coprocessor to use by default. */ 96 static enum m68k_register m68k_float_copnum = COP1; 97 98 /* If this is non-zero, then references to number(%pc) will be taken 99 to refer to number, rather than to %pc + number. */ 100 static int m68k_abspcadd; 101 102 /* If this is non-zero, then the quick forms of the move, add, and sub 103 instructions are used when possible. */ 104 static int m68k_quick = 1; 105 106 /* If this is non-zero, then if the size is not specified for a base 107 or outer displacement, the assembler assumes that the size should 108 be 32 bits. */ 109 static int m68k_rel32 = 1; 110 111 /* This is non-zero if m68k_rel32 was set from the command line. */ 112 static int m68k_rel32_from_cmdline; 113 114 /* The default width to use for an index register when using a base 115 displacement. */ 116 static enum m68k_size m68k_index_width_default = SIZE_LONG; 117 118 /* We want to warn if any text labels are misaligned. In order to get 119 the right line number, we need to record the line number for each 120 label. */ 121 struct label_line 122 { 123 struct label_line *next; 124 symbolS *label; 125 char *file; 126 unsigned int line; 127 int text; 128 }; 129 130 /* The list of labels. */ 131 132 static struct label_line *labels; 133 134 /* The current label. */ 135 136 static struct label_line *current_label; 137 138 /* Pointer to list holding the opcodes sorted by name. */ 139 static struct m68k_opcode const ** m68k_sorted_opcodes; 140 141 /* Its an arbitrary name: This means I don't approve of it. 142 See flames below. */ 143 static struct obstack robyn; 144 145 struct m68k_incant 146 { 147 const char *m_operands; 148 unsigned long m_opcode; 149 short m_opnum; 150 short m_codenum; 151 int m_arch; 152 struct m68k_incant *m_next; 153 }; 154 155 #define getone(x) ((((x)->m_opcode)>>16)&0xffff) 156 #define gettwo(x) (((x)->m_opcode)&0xffff) 157 158 static const enum m68k_register m68000_ctrl[] = { 0 }; 159 static const enum m68k_register m68010_ctrl[] = { 160 SFC, DFC, USP, VBR, 161 0 162 }; 163 static const enum m68k_register m68020_ctrl[] = { 164 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, 165 0 166 }; 167 static const enum m68k_register m68040_ctrl[] = { 168 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, 169 USP, VBR, MSP, ISP, MMUSR, URP, SRP, 170 0 171 }; 172 static const enum m68k_register m68060_ctrl[] = { 173 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, 174 USP, VBR, URP, SRP, PCR, 175 0 176 }; 177 static const enum m68k_register mcf_ctrl[] = { 178 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, 179 RAMBAR0, RAMBAR1, RAMBAR, MBAR, 180 0 181 }; 182 static const enum m68k_register mcf51_ctrl[] = { 183 VBR, CPUCR, 184 0 185 }; 186 static const enum m68k_register mcf5206_ctrl[] = { 187 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, 188 0 189 }; 190 static const enum m68k_register mcf5208_ctrl[] = { 191 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, 192 0 193 }; 194 static const enum m68k_register mcf5210a_ctrl[] = { 195 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, 196 0 197 }; 198 static const enum m68k_register mcf5213_ctrl[] = { 199 VBR, RAMBAR, RAMBAR1, FLASHBAR, 200 0 201 }; 202 static const enum m68k_register mcf5216_ctrl[] = { 203 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 204 0 205 }; 206 static const enum m68k_register mcf5221x_ctrl[] = { 207 VBR, FLASHBAR, RAMBAR, RAMBAR1, 208 0 209 }; 210 static const enum m68k_register mcf52223_ctrl[] = { 211 VBR, FLASHBAR, RAMBAR, RAMBAR1, 212 0 213 }; 214 static const enum m68k_register mcf52235_ctrl[] = { 215 VBR, FLASHBAR, RAMBAR, RAMBAR1, 216 0 217 }; 218 static const enum m68k_register mcf5225_ctrl[] = { 219 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, 220 0 221 }; 222 static const enum m68k_register mcf52259_ctrl[] = { 223 VBR, FLASHBAR, RAMBAR, RAMBAR1, 224 0 225 }; 226 static const enum m68k_register mcf52277_ctrl[] = { 227 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 228 0 229 }; 230 static const enum m68k_register mcf5235_ctrl[] = { 231 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 232 0 233 }; 234 static const enum m68k_register mcf5249_ctrl[] = { 235 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 236 0 237 }; 238 static const enum m68k_register mcf5250_ctrl[] = { 239 VBR, 240 0 241 }; 242 static const enum m68k_register mcf5253_ctrl[] = { 243 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 244 0 245 }; 246 static const enum m68k_register mcf5271_ctrl[] = { 247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 248 0 249 }; 250 static const enum m68k_register mcf5272_ctrl[] = { 251 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, 252 0 253 }; 254 static const enum m68k_register mcf5275_ctrl[] = { 255 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 256 0 257 }; 258 static const enum m68k_register mcf5282_ctrl[] = { 259 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 260 0 261 }; 262 static const enum m68k_register mcf53017_ctrl[] = { 263 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 264 0 265 }; 266 static const enum m68k_register mcf5307_ctrl[] = { 267 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR, 268 0 269 }; 270 static const enum m68k_register mcf5329_ctrl[] = { 271 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 272 0 273 }; 274 static const enum m68k_register mcf5373_ctrl[] = { 275 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 276 0 277 }; 278 static const enum m68k_register mcfv4e_ctrl[] = { 279 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 280 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, 281 MBAR, SECMBAR, 282 MPCR /* Multiprocessor Control register */, 283 EDRAMBAR /* Embedded DRAM Base Address Register */, 284 /* Permutation control registers. */ 285 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, 286 PCR3U0, PCR3L0, PCR3U1, PCR3L1, 287 /* Legacy names */ 288 TC /* ASID */, BUSCR /* MMUBAR */, 289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 290 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, 291 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, 292 0 293 }; 294 static const enum m68k_register mcf5407_ctrl[] = { 295 CACR, ASID, ACR0, ACR1, ACR2, ACR3, 296 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 297 /* Legacy names */ 298 TC /* ASID */, 299 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 300 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 301 0 302 }; 303 static const enum m68k_register mcf54418_ctrl[] = { 304 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR, 305 VBR, PC, RAMBAR1, 306 /* Legacy names */ 307 TC /* ASID */, BUSCR /* MMUBAR */, 308 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 309 RAMBAR /* RAMBAR1 */, 310 0 311 }; 312 static const enum m68k_register mcf54455_ctrl[] = { 313 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 314 VBR, PC, RAMBAR1, 315 /* Legacy names */ 316 TC /* ASID */, BUSCR /* MMUBAR */, 317 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 318 RAMBAR /* RAMBAR1 */, 319 0 320 }; 321 static const enum m68k_register mcf5475_ctrl[] = { 322 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 323 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 324 /* Legacy names */ 325 TC /* ASID */, BUSCR /* MMUBAR */, 326 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 327 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 328 0 329 }; 330 static const enum m68k_register mcf5485_ctrl[] = { 331 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 332 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 333 /* Legacy names */ 334 TC /* ASID */, BUSCR /* MMUBAR */, 335 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 336 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 337 0 338 }; 339 static const enum m68k_register fido_ctrl[] = { 340 SFC, DFC, USP, VBR, CAC, MBO, 341 0 342 }; 343 #define cpu32_ctrl m68010_ctrl 344 345 static const enum m68k_register *control_regs; 346 347 /* Internal form of a 68020 instruction. */ 348 struct m68k_it 349 { 350 const char *error; 351 const char *args; /* List of opcode info. */ 352 int numargs; 353 354 int numo; /* Number of shorts in opcode. */ 355 short opcode[11]; 356 357 struct m68k_op operands[6]; 358 359 int nexp; /* Number of exprs in use. */ 360 struct m68k_exp exprs[4]; 361 362 int nfrag; /* Number of frags we have to produce. */ 363 struct 364 { 365 int fragoff; /* Where in the current opcode the frag ends. */ 366 symbolS *fadd; 367 offsetT foff; 368 int fragty; 369 } 370 fragb[4]; 371 372 int nrel; /* Num of reloc strucs in use. */ 373 struct 374 { 375 int n; 376 expressionS exp; 377 char wid; 378 char pcrel; 379 /* In a pc relative address the difference between the address 380 of the offset and the address that the offset is relative 381 to. This depends on the addressing mode. Basically this 382 is the value to put in the offset field to address the 383 first byte of the offset, without regarding the special 384 significance of some values (in the branch instruction, for 385 example). */ 386 int pcrel_fix; 387 #ifdef OBJ_ELF 388 /* Whether this expression needs special pic relocation, and if 389 so, which. */ 390 enum pic_relocation pic_reloc; 391 #endif 392 } 393 reloc[5]; /* Five is enough??? */ 394 }; 395 396 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) 397 #define float_of_arch(x) ((x) & mfloat) 398 #define mmu_of_arch(x) ((x) & mmmu) 399 #define arch_coldfire_p(x) ((x) & mcfisa_a) 400 #define arch_coldfire_fpu(x) ((x) & cfloat) 401 402 /* Macros for determining if cpu supports a specific addressing mode. */ 403 #define HAVE_LONG_DISP(x) \ 404 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 405 #define HAVE_LONG_CALL(x) \ 406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 407 #define HAVE_LONG_COND(x) \ 408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 409 #define HAVE_LONG_BRANCH(x) \ 410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) 411 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) 412 413 static struct m68k_it the_ins; /* The instruction being assembled. */ 414 415 #define op(ex) ((ex)->exp.X_op) 416 #define adds(ex) ((ex)->exp.X_add_symbol) 417 #define subs(ex) ((ex)->exp.X_op_symbol) 418 #define offs(ex) ((ex)->exp.X_add_number) 419 420 /* Macros for adding things to the m68k_it struct. */ 421 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) 422 423 /* Like addword, but goes BEFORE general operands. */ 424 425 static void 426 insop (int w, const struct m68k_incant *opcode) 427 { 428 int z; 429 for (z = the_ins.numo; z > opcode->m_codenum; --z) 430 the_ins.opcode[z] = the_ins.opcode[z - 1]; 431 for (z = 0; z < the_ins.nrel; z++) 432 the_ins.reloc[z].n += 2; 433 for (z = 0; z < the_ins.nfrag; z++) 434 the_ins.fragb[z].fragoff++; 435 the_ins.opcode[opcode->m_codenum] = w; 436 the_ins.numo++; 437 } 438 439 /* The numo+1 kludge is so we can hit the low order byte of the prev word. 440 Blecch. */ 441 static void 442 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) 443 { 444 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' 445 ? the_ins.numo * 2 - 1 446 : (width == 'b' 447 ? the_ins.numo * 2 + 1 448 : the_ins.numo * 2)); 449 the_ins.reloc[the_ins.nrel].exp = exp->exp; 450 the_ins.reloc[the_ins.nrel].wid = width; 451 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; 452 #ifdef OBJ_ELF 453 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; 454 #endif 455 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; 456 } 457 458 /* Cause an extra frag to be generated here, inserting up to 10 bytes 459 (that value is chosen in the frag_var call in md_assemble). TYPE 460 is the subtype of the frag to be generated; its primary type is 461 rs_machine_dependent. 462 463 The TYPE parameter is also used by md_convert_frag_1 and 464 md_estimate_size_before_relax. The appropriate type of fixup will 465 be emitted by md_convert_frag_1. 466 467 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 468 static void 469 add_frag (symbolS *add, offsetT off, int type) 470 { 471 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; 472 the_ins.fragb[the_ins.nfrag].fadd = add; 473 the_ins.fragb[the_ins.nfrag].foff = off; 474 the_ins.fragb[the_ins.nfrag++].fragty = type; 475 } 476 477 #define isvar(ex) \ 478 (op (ex) != O_constant && op (ex) != O_big) 479 480 static char *crack_operand (char *str, struct m68k_op *opP); 481 static int get_num (struct m68k_exp *exp, int ok); 482 static int reverse_16_bits (int in); 483 static int reverse_8_bits (int in); 484 static void install_gen_operand (int mode, int val); 485 static void install_operand (int mode, int val); 486 static void s_bss (int); 487 static void s_data1 (int); 488 static void s_data2 (int); 489 static void s_even (int); 490 static void s_proc (int); 491 static void s_chip (int); 492 static void s_fopt (int); 493 static void s_opt (int); 494 static void s_reg (int); 495 static void s_restore (int); 496 static void s_save (int); 497 static void s_mri_if (int); 498 static void s_mri_else (int); 499 static void s_mri_endi (int); 500 static void s_mri_break (int); 501 static void s_mri_next (int); 502 static void s_mri_for (int); 503 static void s_mri_endf (int); 504 static void s_mri_repeat (int); 505 static void s_mri_until (int); 506 static void s_mri_while (int); 507 static void s_mri_endw (int); 508 static void s_m68k_cpu (int); 509 static void s_m68k_arch (int); 510 511 struct m68k_cpu 512 { 513 unsigned long arch; /* Architecture features. */ 514 const enum m68k_register *control_regs; /* Control regs on chip */ 515 const char *name; /* Name */ 516 int alias; /* Alias for a cannonical name. If 1, then 517 succeeds canonical name, if -1 then 518 succeeds canonical name, if <-1 ||>1 this is a 519 deprecated name, and the next/previous name 520 should be used. */ 521 }; 522 523 /* We hold flags for features explicitly enabled and explicitly 524 disabled. */ 525 static int current_architecture; 526 static int not_current_architecture; 527 static const struct m68k_cpu *selected_arch; 528 static const struct m68k_cpu *selected_cpu; 529 static int initialized; 530 531 /* Architecture models. */ 532 static const struct m68k_cpu m68k_archs[] = 533 { 534 {m68000, m68000_ctrl, "68000", 0}, 535 {m68010, m68010_ctrl, "68010", 0}, 536 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 537 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 538 {m68040, m68040_ctrl, "68040", 0}, 539 {m68060, m68060_ctrl, "68060", 0}, 540 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 541 {fido_a, fido_ctrl, "fidoa", 0}, 542 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, 543 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, 544 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, 545 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, 546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, 547 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, 548 {0,0,NULL, 0} 549 }; 550 551 /* For -mno-mac we want to turn off all types of mac. */ 552 static const unsigned no_mac = mcfmac | mcfemac; 553 554 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 555 for either. */ 556 static const struct m68k_cpu m68k_extensions[] = 557 { 558 {m68851, NULL, "68851", -1}, 559 {m68881, NULL, "68881", -1}, 560 {m68881, NULL, "68882", -1}, 561 562 {cfloat|m68881, NULL, "float", 0}, 563 564 {mcfhwdiv, NULL, "div", 1}, 565 {mcfusp, NULL, "usp", 1}, 566 {mcfmac, (void *)&no_mac, "mac", 1}, 567 {mcfemac, NULL, "emac", 1}, 568 569 {0,NULL,NULL, 0} 570 }; 571 572 /* Processor list */ 573 static const struct m68k_cpu m68k_cpus[] = 574 { 575 {m68000, m68000_ctrl, "68000", 0}, 576 {m68000, m68000_ctrl, "68ec000", 1}, 577 {m68000, m68000_ctrl, "68hc000", 1}, 578 {m68000, m68000_ctrl, "68hc001", 1}, 579 {m68000, m68000_ctrl, "68008", 1}, 580 {m68000, m68000_ctrl, "68302", 1}, 581 {m68000, m68000_ctrl, "68306", 1}, 582 {m68000, m68000_ctrl, "68307", 1}, 583 {m68000, m68000_ctrl, "68322", 1}, 584 {m68000, m68000_ctrl, "68356", 1}, 585 {m68010, m68010_ctrl, "68010", 0}, 586 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 587 {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, 588 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, 589 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 590 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, 591 {m68040, m68040_ctrl, "68040", 0}, 592 {m68040, m68040_ctrl, "68ec040", 1}, 593 {m68060, m68060_ctrl, "68060", 0}, 594 {m68060, m68060_ctrl, "68ec060", 1}, 595 596 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 597 {cpu32|m68881, cpu32_ctrl, "68330", 1}, 598 {cpu32|m68881, cpu32_ctrl, "68331", 1}, 599 {cpu32|m68881, cpu32_ctrl, "68332", 1}, 600 {cpu32|m68881, cpu32_ctrl, "68333", 1}, 601 {cpu32|m68881, cpu32_ctrl, "68334", 1}, 602 {cpu32|m68881, cpu32_ctrl, "68336", 1}, 603 {cpu32|m68881, cpu32_ctrl, "68340", 1}, 604 {cpu32|m68881, cpu32_ctrl, "68341", 1}, 605 {cpu32|m68881, cpu32_ctrl, "68349", 1}, 606 {cpu32|m68881, cpu32_ctrl, "68360", 1}, 607 608 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0}, 609 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1}, 610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1}, 611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1}, 612 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1}, 613 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1}, 614 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1}, 615 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1}, 616 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1}, 617 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1}, 618 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1}, 619 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1}, 620 621 {mcfisa_a, mcf_ctrl, "5200", 0}, 622 {mcfisa_a, mcf_ctrl, "5202", 1}, 623 {mcfisa_a, mcf_ctrl, "5204", 1}, 624 {mcfisa_a, mcf5206_ctrl, "5206", 1}, 625 626 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, 627 628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, 629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, 630 631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, 632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, 633 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, 635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, 636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, 637 638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, 639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, 641 642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0}, 643 644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, 645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, 646 647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, 648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, 649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, 650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, 651 652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, 653 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, 654 655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1}, 656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0}, 657 658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, 659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, 660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, 661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, 662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, 663 664 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, 665 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, 666 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, 667 668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1}, 669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1}, 670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1}, 671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1}, 672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1}, 673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0}, 674 675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, 676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, 677 678 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, 679 680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, 681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, 682 683 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, 684 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, 685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, 686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, 687 688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1}, 689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1}, 690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1}, 691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1}, 692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1}, 693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1}, 694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0}, 695 696 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, 697 698 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, 699 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, 700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, 701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, 702 703 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, 704 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, 705 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, 706 707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, 708 709 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1}, 710 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1}, 711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1}, 712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1}, 713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0}, 714 715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, 716 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, 717 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, 718 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, 719 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, 720 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, 721 722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, 723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, 724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, 725 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, 726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, 727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, 728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, 729 730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, 731 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, 732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, 733 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, 734 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, 735 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, 736 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, 737 738 {fido_a, fido_ctrl, "fidoa", 0}, 739 {fido_a, fido_ctrl, "fido", 1}, 740 741 {0,NULL,NULL, 0} 742 }; 743 744 static const struct m68k_cpu *m68k_lookup_cpu 745 (const char *, const struct m68k_cpu *, int, int *); 746 static int m68k_set_arch (const char *, int, int); 747 static int m68k_set_cpu (const char *, int, int); 748 static int m68k_set_extension (const char *, int, int); 749 static void m68k_init_arch (void); 750 751 /* This is the assembler relaxation table for m68k. m68k is a rich CISC 752 architecture and we have a lot of relaxation modes. */ 753 754 /* Macros used in the relaxation code. */ 755 #define TAB(x,y) (((x) << 2) + (y)) 756 #define TABTYPE(x) ((x) >> 2) 757 758 /* Relaxation states. */ 759 #define BYTE 0 760 #define SHORT 1 761 #define LONG 2 762 #define SZ_UNDEF 3 763 764 /* Here are all the relaxation modes we support. First we can relax ordinary 765 branches. On 68020 and higher and on CPU32 all branch instructions take 766 three forms, so on these CPUs all branches always remain as such. When we 767 have to expand to the LONG form on a 68000, though, we substitute an 768 absolute jump instead. This is a direct replacement for unconditional 769 branches and a branch over a jump for conditional branches. However, if the 770 user requires PIC and disables this with --pcrel, we can only relax between 771 BYTE and SHORT forms, punting if that isn't enough. This gives us four 772 different relaxation modes for branches: */ 773 774 #define BRANCHBWL 0 /* Branch byte, word, or long. */ 775 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ 776 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ 777 #define BRANCHBW 3 /* Branch byte or word. */ 778 779 /* We also relax coprocessor branches and DBcc's. All CPUs that support 780 coprocessor branches support them in word and long forms, so we have only 781 one relaxation mode for them. DBcc's are word only on all CPUs. We can 782 relax them to the LONG form with a branch-around sequence. This sequence 783 can use a long branch (if available) or an absolute jump (if acceptable). 784 This gives us two relaxation modes. If long branches are not available and 785 absolute jumps are not acceptable, we don't relax DBcc's. */ 786 787 #define FBRANCH 4 /* Coprocessor branch. */ 788 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */ 789 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ 790 791 /* That's all for instruction relaxation. However, we also relax PC-relative 792 operands. Specifically, we have three operand relaxation modes. On the 793 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and 794 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the 795 two. Also PC+displacement+index operands in their simple form (with a non- 796 suppressed index without memory indirection) are supported on all CPUs, but 797 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher 798 and on CPU32 we relax it to SHORT and LONG forms as well using the extended 799 form of the PC+displacement+index operand. Finally, some absolute operands 800 can be relaxed down to 16-bit PC-relative. */ 801 802 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ 803 #define PCINDEX 8 /* PC + displacement + index. */ 804 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ 805 806 /* This relaxation is required for branches where there is no long 807 branch and we are in pcrel mode. We generate a bne/beq pair. */ 808 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs 809 */ 810 811 /* Note that calls to frag_var need to specify the maximum expansion 812 needed; this is currently 12 bytes for bne/beq pair. */ 813 #define FRAG_VAR_SIZE 12 814 815 /* The fields are: 816 How far Forward this mode will reach: 817 How far Backward this mode will reach: 818 How many bytes this mode will add to the size of the frag 819 Which mode to go to if the offset won't fit in this one 820 821 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ 822 relax_typeS md_relax_table[] = 823 { 824 { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, 825 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, 826 { 0, 0, 4, 0 }, 827 { 1, 1, 0, 0 }, 828 829 { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, 830 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, 831 { 0, 0, 4, 0 }, 832 { 1, 1, 0, 0 }, 833 834 { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, 835 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, 836 { 0, 0, 6, 0 }, 837 { 1, 1, 0, 0 }, 838 839 { 127, -128, 0, TAB (BRANCHBW, SHORT) }, 840 { 0, 0, 2, 0 }, 841 { 1, 1, 0, 0 }, 842 { 1, 1, 0, 0 }, 843 844 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ 845 { 32767, -32768, 2, TAB (FBRANCH, LONG) }, 846 { 0, 0, 4, 0 }, 847 { 1, 1, 0, 0 }, 848 849 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 850 { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, 851 { 0, 0, 10, 0 }, 852 { 1, 1, 0, 0 }, 853 854 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 855 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, 856 { 0, 0, 10, 0 }, 857 { 1, 1, 0, 0 }, 858 859 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ 860 { 32767, -32768, 2, TAB (PCREL1632, LONG) }, 861 { 0, 0, 6, 0 }, 862 { 1, 1, 0, 0 }, 863 864 { 125, -130, 0, TAB (PCINDEX, SHORT) }, 865 { 32765, -32770, 2, TAB (PCINDEX, LONG) }, 866 { 0, 0, 4, 0 }, 867 { 1, 1, 0, 0 }, 868 869 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ 870 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, 871 { 0, 0, 4, 0 }, 872 { 1, 1, 0, 0 }, 873 874 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, 875 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, 876 { 0, 0, 10, 0 }, 877 { 1, 1, 0, 0 }, 878 }; 879 880 /* These are the machine dependent pseudo-ops. These are included so 881 the assembler can work on the output from the SUN C compiler, which 882 generates these. */ 883 884 /* This table describes all the machine specific pseudo-ops the assembler 885 has to support. The fields are: 886 pseudo-op name without dot 887 function to call to execute this pseudo-op 888 Integer arg to pass to the function. */ 889 const pseudo_typeS md_pseudo_table[] = 890 { 891 {"data1", s_data1, 0}, 892 {"data2", s_data2, 0}, 893 {"bss", s_bss, 0}, 894 {"even", s_even, 0}, 895 {"skip", s_space, 0}, 896 {"proc", s_proc, 0}, 897 #if defined (TE_SUN3) || defined (OBJ_ELF) 898 {"align", s_align_bytes, 0}, 899 #endif 900 #ifdef OBJ_ELF 901 {"swbeg", s_ignore, 0}, 902 {"long", m68k_elf_cons, 4}, 903 #endif 904 {"extend", float_cons, 'x'}, 905 {"ldouble", float_cons, 'x'}, 906 907 {"arch", s_m68k_arch, 0}, 908 {"cpu", s_m68k_cpu, 0}, 909 910 /* The following pseudo-ops are supported for MRI compatibility. */ 911 {"chip", s_chip, 0}, 912 {"comline", s_space, 1}, 913 {"fopt", s_fopt, 0}, 914 {"mask2", s_ignore, 0}, 915 {"opt", s_opt, 0}, 916 {"reg", s_reg, 0}, 917 {"restore", s_restore, 0}, 918 {"save", s_save, 0}, 919 920 {"if", s_mri_if, 0}, 921 {"if.b", s_mri_if, 'b'}, 922 {"if.w", s_mri_if, 'w'}, 923 {"if.l", s_mri_if, 'l'}, 924 {"else", s_mri_else, 0}, 925 {"else.s", s_mri_else, 's'}, 926 {"else.l", s_mri_else, 'l'}, 927 {"endi", s_mri_endi, 0}, 928 {"break", s_mri_break, 0}, 929 {"break.s", s_mri_break, 's'}, 930 {"break.l", s_mri_break, 'l'}, 931 {"next", s_mri_next, 0}, 932 {"next.s", s_mri_next, 's'}, 933 {"next.l", s_mri_next, 'l'}, 934 {"for", s_mri_for, 0}, 935 {"for.b", s_mri_for, 'b'}, 936 {"for.w", s_mri_for, 'w'}, 937 {"for.l", s_mri_for, 'l'}, 938 {"endf", s_mri_endf, 0}, 939 {"repeat", s_mri_repeat, 0}, 940 {"until", s_mri_until, 0}, 941 {"until.b", s_mri_until, 'b'}, 942 {"until.w", s_mri_until, 'w'}, 943 {"until.l", s_mri_until, 'l'}, 944 {"while", s_mri_while, 0}, 945 {"while.b", s_mri_while, 'b'}, 946 {"while.w", s_mri_while, 'w'}, 947 {"while.l", s_mri_while, 'l'}, 948 {"endw", s_mri_endw, 0}, 949 950 {0, 0, 0} 951 }; 952 953 /* The mote pseudo ops are put into the opcode table, since they 954 don't start with a . they look like opcodes to gas. */ 955 956 const pseudo_typeS mote_pseudo_table[] = 957 { 958 959 {"dcl", cons, 4}, 960 {"dc", cons, 2}, 961 {"dcw", cons, 2}, 962 {"dcb", cons, 1}, 963 964 {"dsl", s_space, 4}, 965 {"ds", s_space, 2}, 966 {"dsw", s_space, 2}, 967 {"dsb", s_space, 1}, 968 969 {"xdef", s_globl, 0}, 970 #ifdef OBJ_ELF 971 {"align", s_align_bytes, 0}, 972 #else 973 {"align", s_align_ptwo, 0}, 974 #endif 975 #ifdef M68KCOFF 976 {"sect", obj_coff_section, 0}, 977 {"section", obj_coff_section, 0}, 978 #endif 979 {0, 0, 0} 980 }; 981 982 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host 983 gives identical results to a 32-bit host. */ 984 #define TRUNC(X) ((valueT) (X) & 0xffffffff) 985 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) 986 987 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) 988 #define isubyte(x) ((valueT) TRUNC (x) < 0x100) 989 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) 990 #define isuword(x) ((valueT) TRUNC (x) < 0x10000) 991 992 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) 993 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) 994 #define islong(x) (1) 995 996 static char notend_table[256]; 997 static char alt_notend_table[256]; 998 #define notend(s) \ 999 (! (notend_table[(unsigned char) *s] \ 1000 || (*s == ':' \ 1001 && alt_notend_table[(unsigned char) s[1]]))) 1002 1003 #ifdef OBJ_ELF 1004 1005 /* Return zero if the reference to SYMBOL from within the same segment may 1006 be relaxed. */ 1007 1008 /* On an ELF system, we can't relax an externally visible symbol, 1009 because it may be overridden by a shared library. However, if 1010 TARGET_OS is "elf", then we presume that we are assembling for an 1011 embedded system, in which case we don't have to worry about shared 1012 libraries, and we can relax any external sym. */ 1013 1014 #define relaxable_symbol(symbol) \ 1015 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ 1016 || S_IS_WEAK (symbol))) 1017 1018 /* Compute the relocation code for a fixup of SIZE bytes, using pc 1019 relative relocation if PCREL is non-zero. PIC says whether a special 1020 pic relocation was requested. */ 1021 1022 static bfd_reloc_code_real_type 1023 get_reloc_code (int size, int pcrel, enum pic_relocation pic) 1024 { 1025 switch (pic) 1026 { 1027 case pic_got_pcrel: 1028 switch (size) 1029 { 1030 case 1: 1031 return BFD_RELOC_8_GOT_PCREL; 1032 case 2: 1033 return BFD_RELOC_16_GOT_PCREL; 1034 case 4: 1035 return BFD_RELOC_32_GOT_PCREL; 1036 } 1037 break; 1038 1039 case pic_got_off: 1040 switch (size) 1041 { 1042 case 1: 1043 return BFD_RELOC_8_GOTOFF; 1044 case 2: 1045 return BFD_RELOC_16_GOTOFF; 1046 case 4: 1047 return BFD_RELOC_32_GOTOFF; 1048 } 1049 break; 1050 1051 case pic_plt_pcrel: 1052 switch (size) 1053 { 1054 case 1: 1055 return BFD_RELOC_8_PLT_PCREL; 1056 case 2: 1057 return BFD_RELOC_16_PLT_PCREL; 1058 case 4: 1059 return BFD_RELOC_32_PLT_PCREL; 1060 } 1061 break; 1062 1063 case pic_plt_off: 1064 switch (size) 1065 { 1066 case 1: 1067 return BFD_RELOC_8_PLTOFF; 1068 case 2: 1069 return BFD_RELOC_16_PLTOFF; 1070 case 4: 1071 return BFD_RELOC_32_PLTOFF; 1072 } 1073 break; 1074 1075 case pic_tls_gd: 1076 switch (size) 1077 { 1078 case 1: 1079 return BFD_RELOC_68K_TLS_GD8; 1080 case 2: 1081 return BFD_RELOC_68K_TLS_GD16; 1082 case 4: 1083 return BFD_RELOC_68K_TLS_GD32; 1084 } 1085 break; 1086 1087 case pic_tls_ldm: 1088 switch (size) 1089 { 1090 case 1: 1091 return BFD_RELOC_68K_TLS_LDM8; 1092 case 2: 1093 return BFD_RELOC_68K_TLS_LDM16; 1094 case 4: 1095 return BFD_RELOC_68K_TLS_LDM32; 1096 } 1097 break; 1098 1099 case pic_tls_ldo: 1100 switch (size) 1101 { 1102 case 1: 1103 return BFD_RELOC_68K_TLS_LDO8; 1104 case 2: 1105 return BFD_RELOC_68K_TLS_LDO16; 1106 case 4: 1107 return BFD_RELOC_68K_TLS_LDO32; 1108 } 1109 break; 1110 1111 case pic_tls_ie: 1112 switch (size) 1113 { 1114 case 1: 1115 return BFD_RELOC_68K_TLS_IE8; 1116 case 2: 1117 return BFD_RELOC_68K_TLS_IE16; 1118 case 4: 1119 return BFD_RELOC_68K_TLS_IE32; 1120 } 1121 break; 1122 1123 case pic_tls_le: 1124 switch (size) 1125 { 1126 case 1: 1127 return BFD_RELOC_68K_TLS_LE8; 1128 case 2: 1129 return BFD_RELOC_68K_TLS_LE16; 1130 case 4: 1131 return BFD_RELOC_68K_TLS_LE32; 1132 } 1133 break; 1134 1135 case pic_none: 1136 if (pcrel) 1137 { 1138 switch (size) 1139 { 1140 case 1: 1141 return BFD_RELOC_8_PCREL; 1142 case 2: 1143 return BFD_RELOC_16_PCREL; 1144 case 4: 1145 return BFD_RELOC_32_PCREL; 1146 } 1147 } 1148 else 1149 { 1150 switch (size) 1151 { 1152 case 1: 1153 return BFD_RELOC_8; 1154 case 2: 1155 return BFD_RELOC_16; 1156 case 4: 1157 return BFD_RELOC_32; 1158 } 1159 } 1160 } 1161 1162 if (pcrel) 1163 { 1164 if (pic == pic_none) 1165 as_bad (_("Can not do %d byte pc-relative relocation"), size); 1166 else 1167 as_bad (_("Can not do %d byte pc-relative pic relocation"), size); 1168 } 1169 else 1170 { 1171 if (pic == pic_none) 1172 as_bad (_("Can not do %d byte relocation"), size); 1173 else 1174 as_bad (_("Can not do %d byte pic relocation"), size); 1175 } 1176 1177 return BFD_RELOC_NONE; 1178 } 1179 1180 /* Here we decide which fixups can be adjusted to make them relative 1181 to the beginning of the section instead of the symbol. Basically 1182 we need to make sure that the dynamic relocations are done 1183 correctly, so in some cases we force the original symbol to be 1184 used. */ 1185 int 1186 tc_m68k_fix_adjustable (fixS *fixP) 1187 { 1188 /* Adjust_reloc_syms doesn't know about the GOT. */ 1189 switch (fixP->fx_r_type) 1190 { 1191 case BFD_RELOC_8_GOT_PCREL: 1192 case BFD_RELOC_16_GOT_PCREL: 1193 case BFD_RELOC_32_GOT_PCREL: 1194 case BFD_RELOC_8_GOTOFF: 1195 case BFD_RELOC_16_GOTOFF: 1196 case BFD_RELOC_32_GOTOFF: 1197 case BFD_RELOC_8_PLT_PCREL: 1198 case BFD_RELOC_16_PLT_PCREL: 1199 case BFD_RELOC_32_PLT_PCREL: 1200 case BFD_RELOC_8_PLTOFF: 1201 case BFD_RELOC_16_PLTOFF: 1202 case BFD_RELOC_32_PLTOFF: 1203 case BFD_RELOC_68K_TLS_GD32: 1204 case BFD_RELOC_68K_TLS_GD16: 1205 case BFD_RELOC_68K_TLS_GD8: 1206 case BFD_RELOC_68K_TLS_LDM32: 1207 case BFD_RELOC_68K_TLS_LDM16: 1208 case BFD_RELOC_68K_TLS_LDM8: 1209 case BFD_RELOC_68K_TLS_LDO32: 1210 case BFD_RELOC_68K_TLS_LDO16: 1211 case BFD_RELOC_68K_TLS_LDO8: 1212 case BFD_RELOC_68K_TLS_IE32: 1213 case BFD_RELOC_68K_TLS_IE16: 1214 case BFD_RELOC_68K_TLS_IE8: 1215 case BFD_RELOC_68K_TLS_LE32: 1216 case BFD_RELOC_68K_TLS_LE16: 1217 case BFD_RELOC_68K_TLS_LE8: 1218 return 0; 1219 1220 case BFD_RELOC_VTABLE_INHERIT: 1221 case BFD_RELOC_VTABLE_ENTRY: 1222 return 0; 1223 1224 default: 1225 return 1; 1226 } 1227 } 1228 1229 #else /* !OBJ_ELF */ 1230 1231 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC 1232 1233 /* PR gas/3041 Weak symbols are not relaxable 1234 because they must be treated as extern. */ 1235 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol))) 1236 1237 #endif /* OBJ_ELF */ 1238 1239 arelent * 1240 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 1241 { 1242 arelent *reloc; 1243 bfd_reloc_code_real_type code; 1244 1245 /* If the tcbit is set, then this was a fixup of a negative value 1246 that was never resolved. We do not have a reloc to handle this, 1247 so just return. We assume that other code will have detected this 1248 situation and produced a helpful error message, so we just tell the 1249 user that the reloc cannot be produced. */ 1250 if (fixp->fx_tcbit) 1251 { 1252 if (fixp->fx_addsy) 1253 as_bad_where (fixp->fx_file, fixp->fx_line, 1254 _("Unable to produce reloc against symbol '%s'"), 1255 S_GET_NAME (fixp->fx_addsy)); 1256 return NULL; 1257 } 1258 1259 if (fixp->fx_r_type != BFD_RELOC_NONE) 1260 { 1261 code = fixp->fx_r_type; 1262 1263 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible 1264 that fixup_segment converted a non-PC relative reloc into a 1265 PC relative reloc. In such a case, we need to convert the 1266 reloc code. */ 1267 if (fixp->fx_pcrel) 1268 { 1269 switch (code) 1270 { 1271 case BFD_RELOC_8: 1272 code = BFD_RELOC_8_PCREL; 1273 break; 1274 case BFD_RELOC_16: 1275 code = BFD_RELOC_16_PCREL; 1276 break; 1277 case BFD_RELOC_32: 1278 code = BFD_RELOC_32_PCREL; 1279 break; 1280 case BFD_RELOC_8_PCREL: 1281 case BFD_RELOC_16_PCREL: 1282 case BFD_RELOC_32_PCREL: 1283 case BFD_RELOC_8_GOT_PCREL: 1284 case BFD_RELOC_16_GOT_PCREL: 1285 case BFD_RELOC_32_GOT_PCREL: 1286 case BFD_RELOC_8_GOTOFF: 1287 case BFD_RELOC_16_GOTOFF: 1288 case BFD_RELOC_32_GOTOFF: 1289 case BFD_RELOC_8_PLT_PCREL: 1290 case BFD_RELOC_16_PLT_PCREL: 1291 case BFD_RELOC_32_PLT_PCREL: 1292 case BFD_RELOC_8_PLTOFF: 1293 case BFD_RELOC_16_PLTOFF: 1294 case BFD_RELOC_32_PLTOFF: 1295 case BFD_RELOC_68K_TLS_GD32: 1296 case BFD_RELOC_68K_TLS_GD16: 1297 case BFD_RELOC_68K_TLS_GD8: 1298 case BFD_RELOC_68K_TLS_LDM32: 1299 case BFD_RELOC_68K_TLS_LDM16: 1300 case BFD_RELOC_68K_TLS_LDM8: 1301 case BFD_RELOC_68K_TLS_LDO32: 1302 case BFD_RELOC_68K_TLS_LDO16: 1303 case BFD_RELOC_68K_TLS_LDO8: 1304 case BFD_RELOC_68K_TLS_IE32: 1305 case BFD_RELOC_68K_TLS_IE16: 1306 case BFD_RELOC_68K_TLS_IE8: 1307 case BFD_RELOC_68K_TLS_LE32: 1308 case BFD_RELOC_68K_TLS_LE16: 1309 case BFD_RELOC_68K_TLS_LE8: 1310 break; 1311 default: 1312 as_bad_where (fixp->fx_file, fixp->fx_line, 1313 _("Cannot make %s relocation PC relative"), 1314 bfd_get_reloc_code_name (code)); 1315 } 1316 } 1317 } 1318 else 1319 { 1320 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) 1321 switch (F (fixp->fx_size, fixp->fx_pcrel)) 1322 { 1323 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break 1324 MAP (1, 0, BFD_RELOC_8); 1325 MAP (2, 0, BFD_RELOC_16); 1326 MAP (4, 0, BFD_RELOC_32); 1327 MAP (1, 1, BFD_RELOC_8_PCREL); 1328 MAP (2, 1, BFD_RELOC_16_PCREL); 1329 MAP (4, 1, BFD_RELOC_32_PCREL); 1330 default: 1331 abort (); 1332 } 1333 } 1334 #undef F 1335 #undef MAP 1336 1337 reloc = (arelent *) xmalloc (sizeof (arelent)); 1338 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 1339 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1340 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1341 #ifndef OBJ_ELF 1342 if (OUTPUT_FLAVOR == bfd_target_aout_flavour 1343 && fixp->fx_addsy 1344 && S_IS_WEAK (fixp->fx_addsy) 1345 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy))) 1346 { 1347 /* PR gas/3041 References to weak symbols must be treated as extern 1348 in order to be overridable by the linker, even if they are defined 1349 in the same object file. So the original addend must be written 1350 "as is" into the output section without further processing. 1351 The addend value must be hacked here in order to force 1352 bfd_install_relocation() to write the original value into the 1353 output section. 1354 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol 1355 value has already been added to the addend in fixup_segment(). We 1356 have to remove it. 1357 2) bfd_install_relocation() will incorrectly treat this symbol as 1358 resolved, so it will write the symbol value plus its addend and 1359 section VMA. As a workaround we can tweak the addend value here in 1360 order to get the original value in the section after the call to 1361 bfd_install_relocation(). */ 1362 reloc->addend = fixp->fx_addnumber 1363 /* Fix because of MD_APPLY_SYM_VALUE() */ 1364 - S_GET_VALUE (fixp->fx_addsy) 1365 /* Fix for bfd_install_relocation() */ 1366 - (S_GET_VALUE (fixp->fx_addsy) 1367 + S_GET_SEGMENT (fixp->fx_addsy)->vma); 1368 } 1369 else if (fixp->fx_pcrel) 1370 reloc->addend = fixp->fx_addnumber; 1371 else 1372 reloc->addend = 0; 1373 #else 1374 if (!fixp->fx_pcrel) 1375 reloc->addend = fixp->fx_addnumber; 1376 else 1377 reloc->addend = (section->vma 1378 + fixp->fx_pcrel_adjust 1379 + fixp->fx_addnumber 1380 + md_pcrel_from (fixp)); 1381 #endif 1382 1383 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 1384 gas_assert (reloc->howto != 0); 1385 1386 return reloc; 1387 } 1388 1389 /* Handle of the OPCODE hash table. NULL means any use before 1390 m68k_ip_begin() will crash. */ 1391 static struct hash_control *op_hash; 1392 1393 /* Assemble an m68k instruction. */ 1395 1396 static void 1397 m68k_ip (char *instring) 1398 { 1399 char *p; 1400 struct m68k_op *opP; 1401 const struct m68k_incant *opcode; 1402 const char *s; 1403 int tmpreg = 0, baseo = 0, outro = 0, nextword; 1404 char *pdot, *pdotmove; 1405 enum m68k_size siz1, siz2; 1406 char c; 1407 int losing; 1408 int opsfound; 1409 struct m68k_op operands_backup[6]; 1410 LITTLENUM_TYPE words[6]; 1411 LITTLENUM_TYPE *wordp; 1412 unsigned long ok_arch = 0; 1413 1414 if (*instring == ' ') 1415 instring++; /* Skip leading whitespace. */ 1416 1417 /* Scan up to end of operation-code, which MUST end in end-of-string 1418 or exactly 1 space. */ 1419 pdot = 0; 1420 for (p = instring; *p != '\0'; p++) 1421 { 1422 if (*p == ' ') 1423 break; 1424 if (*p == '.') 1425 pdot = p; 1426 } 1427 1428 if (p == instring) 1429 { 1430 the_ins.error = _("No operator"); 1431 return; 1432 } 1433 1434 /* p now points to the end of the opcode name, probably whitespace. 1435 Make sure the name is null terminated by clobbering the 1436 whitespace, look it up in the hash table, then fix it back. 1437 Remove a dot, first, since the opcode tables have none. */ 1438 if (pdot != NULL) 1439 { 1440 for (pdotmove = pdot; pdotmove < p; pdotmove++) 1441 *pdotmove = pdotmove[1]; 1442 p--; 1443 } 1444 1445 c = *p; 1446 *p = '\0'; 1447 opcode = (const struct m68k_incant *) hash_find (op_hash, instring); 1448 *p = c; 1449 1450 if (pdot != NULL) 1451 { 1452 for (pdotmove = p; pdotmove > pdot; pdotmove--) 1453 *pdotmove = pdotmove[-1]; 1454 *pdot = '.'; 1455 ++p; 1456 } 1457 1458 if (opcode == NULL) 1459 { 1460 the_ins.error = _("Unknown operator"); 1461 return; 1462 } 1463 1464 /* Found a legitimate opcode, start matching operands. */ 1465 while (*p == ' ') 1466 ++p; 1467 1468 if (opcode->m_operands == 0) 1469 { 1470 char *old = input_line_pointer; 1471 *old = '\n'; 1472 input_line_pointer = p; 1473 /* Ahh - it's a motorola style psuedo op. */ 1474 mote_pseudo_table[opcode->m_opnum].poc_handler 1475 (mote_pseudo_table[opcode->m_opnum].poc_val); 1476 input_line_pointer = old; 1477 *old = 0; 1478 1479 return; 1480 } 1481 1482 if (flag_mri && opcode->m_opnum == 0) 1483 { 1484 /* In MRI mode, random garbage is allowed after an instruction 1485 which accepts no operands. */ 1486 the_ins.args = opcode->m_operands; 1487 the_ins.numargs = opcode->m_opnum; 1488 the_ins.numo = opcode->m_codenum; 1489 the_ins.opcode[0] = getone (opcode); 1490 the_ins.opcode[1] = gettwo (opcode); 1491 return; 1492 } 1493 1494 for (opP = &the_ins.operands[0]; *p; opP++) 1495 { 1496 p = crack_operand (p, opP); 1497 1498 if (opP->error) 1499 { 1500 the_ins.error = opP->error; 1501 return; 1502 } 1503 } 1504 1505 opsfound = opP - &the_ins.operands[0]; 1506 1507 /* This ugly hack is to support the floating pt opcodes in their 1508 standard form. Essentially, we fake a first enty of type COP#1 */ 1509 if (opcode->m_operands[0] == 'I') 1510 { 1511 int n; 1512 1513 for (n = opsfound; n > 0; --n) 1514 the_ins.operands[n] = the_ins.operands[n - 1]; 1515 1516 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); 1517 the_ins.operands[0].mode = CONTROL; 1518 the_ins.operands[0].reg = m68k_float_copnum; 1519 opsfound++; 1520 } 1521 1522 /* We've got the operands. Find an opcode that'll accept them. */ 1523 for (losing = 0;;) 1524 { 1525 /* If we didn't get the right number of ops, or we have no 1526 common model with this pattern then reject this pattern. */ 1527 1528 ok_arch |= opcode->m_arch; 1529 if (opsfound != opcode->m_opnum 1530 || ((opcode->m_arch & current_architecture) == 0)) 1531 ++losing; 1532 else 1533 { 1534 int i; 1535 1536 /* Make a copy of the operands of this insn so that 1537 we can modify them safely, should we want to. */ 1538 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); 1539 for (i = 0; i < opsfound; i++) 1540 operands_backup[i] = the_ins.operands[i]; 1541 1542 for (s = opcode->m_operands, opP = &operands_backup[0]; 1543 *s && !losing; 1544 s += 2, opP++) 1545 { 1546 /* Warning: this switch is huge! */ 1547 /* I've tried to organize the cases into this order: 1548 non-alpha first, then alpha by letter. Lower-case 1549 goes directly before uppercase counterpart. */ 1550 /* Code with multiple case ...: gets sorted by the lowest 1551 case ... it belongs to. I hope this makes sense. */ 1552 switch (*s) 1553 { 1554 case '!': 1555 switch (opP->mode) 1556 { 1557 case IMMED: 1558 case DREG: 1559 case AREG: 1560 case FPREG: 1561 case CONTROL: 1562 case AINC: 1563 case ADEC: 1564 case REGLST: 1565 losing++; 1566 break; 1567 default: 1568 break; 1569 } 1570 break; 1571 1572 case '<': 1573 switch (opP->mode) 1574 { 1575 case DREG: 1576 case AREG: 1577 case FPREG: 1578 case CONTROL: 1579 case IMMED: 1580 case ADEC: 1581 case REGLST: 1582 losing++; 1583 break; 1584 default: 1585 break; 1586 } 1587 break; 1588 1589 case '>': 1590 switch (opP->mode) 1591 { 1592 case DREG: 1593 case AREG: 1594 case FPREG: 1595 case CONTROL: 1596 case IMMED: 1597 case AINC: 1598 case REGLST: 1599 losing++; 1600 break; 1601 case ABSL: 1602 break; 1603 default: 1604 if (opP->reg == PC 1605 || opP->reg == ZPC) 1606 losing++; 1607 break; 1608 } 1609 break; 1610 1611 case 'm': 1612 switch (opP->mode) 1613 { 1614 case DREG: 1615 case AREG: 1616 case AINDR: 1617 case AINC: 1618 case ADEC: 1619 break; 1620 default: 1621 losing++; 1622 } 1623 break; 1624 1625 case 'n': 1626 switch (opP->mode) 1627 { 1628 case DISP: 1629 break; 1630 default: 1631 losing++; 1632 } 1633 break; 1634 1635 case 'o': 1636 switch (opP->mode) 1637 { 1638 case BASE: 1639 case ABSL: 1640 case IMMED: 1641 break; 1642 default: 1643 losing++; 1644 } 1645 break; 1646 1647 case 'p': 1648 switch (opP->mode) 1649 { 1650 case DREG: 1651 case AREG: 1652 case AINDR: 1653 case AINC: 1654 case ADEC: 1655 break; 1656 case DISP: 1657 if (opP->reg == PC || opP->reg == ZPC) 1658 losing++; 1659 break; 1660 default: 1661 losing++; 1662 } 1663 break; 1664 1665 case 'q': 1666 switch (opP->mode) 1667 { 1668 case DREG: 1669 case AINDR: 1670 case AINC: 1671 case ADEC: 1672 break; 1673 case DISP: 1674 if (opP->reg == PC || opP->reg == ZPC) 1675 losing++; 1676 break; 1677 default: 1678 losing++; 1679 break; 1680 } 1681 break; 1682 1683 case 'v': 1684 switch (opP->mode) 1685 { 1686 case DREG: 1687 case AINDR: 1688 case AINC: 1689 case ADEC: 1690 case ABSL: 1691 break; 1692 case DISP: 1693 if (opP->reg == PC || opP->reg == ZPC) 1694 losing++; 1695 break; 1696 default: 1697 losing++; 1698 break; 1699 } 1700 break; 1701 1702 case '#': 1703 if (opP->mode != IMMED) 1704 losing++; 1705 else if (s[1] == 'b' 1706 && ! isvar (&opP->disp) 1707 && (opP->disp.exp.X_op != O_constant 1708 || ! isbyte (opP->disp.exp.X_add_number))) 1709 losing++; 1710 else if (s[1] == 'B' 1711 && ! isvar (&opP->disp) 1712 && (opP->disp.exp.X_op != O_constant 1713 || ! issbyte (opP->disp.exp.X_add_number))) 1714 losing++; 1715 else if (s[1] == 'w' 1716 && ! isvar (&opP->disp) 1717 && (opP->disp.exp.X_op != O_constant 1718 || ! isword (opP->disp.exp.X_add_number))) 1719 losing++; 1720 else if (s[1] == 'W' 1721 && ! isvar (&opP->disp) 1722 && (opP->disp.exp.X_op != O_constant 1723 || ! issword (opP->disp.exp.X_add_number))) 1724 losing++; 1725 break; 1726 1727 case '^': 1728 case 'T': 1729 if (opP->mode != IMMED) 1730 losing++; 1731 break; 1732 1733 case '$': 1734 if (opP->mode == AREG 1735 || opP->mode == CONTROL 1736 || opP->mode == FPREG 1737 || opP->mode == IMMED 1738 || opP->mode == REGLST 1739 || (opP->mode != ABSL 1740 && (opP->reg == PC 1741 || opP->reg == ZPC))) 1742 losing++; 1743 break; 1744 1745 case '%': 1746 if (opP->mode == CONTROL 1747 || opP->mode == FPREG 1748 || opP->mode == REGLST 1749 || opP->mode == IMMED 1750 || (opP->mode != ABSL 1751 && (opP->reg == PC 1752 || opP->reg == ZPC))) 1753 losing++; 1754 break; 1755 1756 case '&': 1757 switch (opP->mode) 1758 { 1759 case DREG: 1760 case AREG: 1761 case FPREG: 1762 case CONTROL: 1763 case IMMED: 1764 case AINC: 1765 case ADEC: 1766 case REGLST: 1767 losing++; 1768 break; 1769 case ABSL: 1770 break; 1771 default: 1772 if (opP->reg == PC 1773 || opP->reg == ZPC) 1774 losing++; 1775 break; 1776 } 1777 break; 1778 1779 case '*': 1780 if (opP->mode == CONTROL 1781 || opP->mode == FPREG 1782 || opP->mode == REGLST) 1783 losing++; 1784 break; 1785 1786 case '+': 1787 if (opP->mode != AINC) 1788 losing++; 1789 break; 1790 1791 case '-': 1792 if (opP->mode != ADEC) 1793 losing++; 1794 break; 1795 1796 case '/': 1797 switch (opP->mode) 1798 { 1799 case AREG: 1800 case CONTROL: 1801 case FPREG: 1802 case AINC: 1803 case ADEC: 1804 case IMMED: 1805 case REGLST: 1806 losing++; 1807 break; 1808 default: 1809 break; 1810 } 1811 break; 1812 1813 case ';': 1814 switch (opP->mode) 1815 { 1816 case AREG: 1817 case CONTROL: 1818 case FPREG: 1819 case REGLST: 1820 losing++; 1821 break; 1822 default: 1823 break; 1824 } 1825 break; 1826 1827 case '?': 1828 switch (opP->mode) 1829 { 1830 case AREG: 1831 case CONTROL: 1832 case FPREG: 1833 case AINC: 1834 case ADEC: 1835 case IMMED: 1836 case REGLST: 1837 losing++; 1838 break; 1839 case ABSL: 1840 break; 1841 default: 1842 if (opP->reg == PC || opP->reg == ZPC) 1843 losing++; 1844 break; 1845 } 1846 break; 1847 1848 case '@': 1849 switch (opP->mode) 1850 { 1851 case AREG: 1852 case CONTROL: 1853 case FPREG: 1854 case IMMED: 1855 case REGLST: 1856 losing++; 1857 break; 1858 default: 1859 break; 1860 } 1861 break; 1862 1863 case '~': /* For now! (JF FOO is this right?) */ 1864 switch (opP->mode) 1865 { 1866 case DREG: 1867 case AREG: 1868 case CONTROL: 1869 case FPREG: 1870 case IMMED: 1871 case REGLST: 1872 losing++; 1873 break; 1874 case ABSL: 1875 break; 1876 default: 1877 if (opP->reg == PC 1878 || opP->reg == ZPC) 1879 losing++; 1880 break; 1881 } 1882 break; 1883 1884 case '3': 1885 if (opP->mode != CONTROL 1886 || (opP->reg != TT0 && opP->reg != TT1)) 1887 losing++; 1888 break; 1889 1890 case 'A': 1891 if (opP->mode != AREG) 1892 losing++; 1893 break; 1894 1895 case 'a': 1896 if (opP->mode != AINDR) 1897 ++losing; 1898 break; 1899 1900 case '4': 1901 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC 1902 && (opP->mode != DISP 1903 || opP->reg < ADDR0 1904 || opP->reg > ADDR7)) 1905 ++losing; 1906 break; 1907 1908 case 'B': /* FOO */ 1909 if (opP->mode != ABSL 1910 || (flag_long_jumps 1911 && strncmp (instring, "jbsr", 4) == 0)) 1912 losing++; 1913 break; 1914 1915 case 'b': 1916 switch (opP->mode) 1917 { 1918 case IMMED: 1919 case ABSL: 1920 case AREG: 1921 case FPREG: 1922 case CONTROL: 1923 case POST: 1924 case PRE: 1925 case REGLST: 1926 losing++; 1927 break; 1928 default: 1929 break; 1930 } 1931 break; 1932 1933 case 'C': 1934 if (opP->mode != CONTROL || opP->reg != CCR) 1935 losing++; 1936 break; 1937 1938 case 'd': 1939 if (opP->mode != DISP 1940 || opP->reg < ADDR0 1941 || opP->reg > ADDR7) 1942 losing++; 1943 break; 1944 1945 case 'D': 1946 if (opP->mode != DREG) 1947 losing++; 1948 break; 1949 1950 case 'E': 1951 if (opP->reg != ACC) 1952 losing++; 1953 break; 1954 1955 case 'e': 1956 if (opP->reg != ACC && opP->reg != ACC1 1957 && opP->reg != ACC2 && opP->reg != ACC3) 1958 losing++; 1959 break; 1960 1961 case 'F': 1962 if (opP->mode != FPREG) 1963 losing++; 1964 break; 1965 1966 case 'G': 1967 if (opP->reg != MACSR) 1968 losing++; 1969 break; 1970 1971 case 'g': 1972 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) 1973 losing++; 1974 break; 1975 1976 case 'H': 1977 if (opP->reg != MASK) 1978 losing++; 1979 break; 1980 1981 case 'I': 1982 if (opP->mode != CONTROL 1983 || opP->reg < COP0 1984 || opP->reg > COP7) 1985 losing++; 1986 break; 1987 1988 case 'i': 1989 if (opP->mode != LSH && opP->mode != RSH) 1990 losing++; 1991 break; 1992 1993 case 'J': 1994 if (opP->mode != CONTROL 1995 || opP->reg < USP 1996 || opP->reg > last_movec_reg 1997 || !control_regs) 1998 losing++; 1999 else 2000 { 2001 const enum m68k_register *rp; 2002 2003 for (rp = control_regs; *rp; rp++) 2004 { 2005 if (*rp == opP->reg) 2006 break; 2007 /* In most CPUs RAMBAR refers to control reg 2008 c05 (RAMBAR1), but a few CPUs have it 2009 refer to c04 (RAMBAR0). */ 2010 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) 2011 { 2012 opP->reg = RAMBAR_ALT; 2013 break; 2014 } 2015 } 2016 if (*rp == 0) 2017 losing++; 2018 } 2019 break; 2020 2021 case 'k': 2022 if (opP->mode != IMMED) 2023 losing++; 2024 break; 2025 2026 case 'l': 2027 case 'L': 2028 if (opP->mode == DREG 2029 || opP->mode == AREG 2030 || opP->mode == FPREG) 2031 { 2032 if (s[1] == '8') 2033 losing++; 2034 else 2035 { 2036 switch (opP->mode) 2037 { 2038 case DREG: 2039 opP->mask = 1 << (opP->reg - DATA0); 2040 break; 2041 case AREG: 2042 opP->mask = 1 << (opP->reg - ADDR0 + 8); 2043 break; 2044 case FPREG: 2045 opP->mask = 1 << (opP->reg - FP0 + 16); 2046 break; 2047 default: 2048 abort (); 2049 } 2050 opP->mode = REGLST; 2051 } 2052 } 2053 else if (opP->mode == CONTROL) 2054 { 2055 if (s[1] != '8') 2056 losing++; 2057 else 2058 { 2059 switch (opP->reg) 2060 { 2061 case FPI: 2062 opP->mask = 1 << 24; 2063 break; 2064 case FPS: 2065 opP->mask = 1 << 25; 2066 break; 2067 case FPC: 2068 opP->mask = 1 << 26; 2069 break; 2070 default: 2071 losing++; 2072 break; 2073 } 2074 opP->mode = REGLST; 2075 } 2076 } 2077 else if (opP->mode != REGLST) 2078 losing++; 2079 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) 2080 losing++; 2081 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) 2082 losing++; 2083 break; 2084 2085 case 'M': 2086 if (opP->mode != IMMED) 2087 losing++; 2088 else if (opP->disp.exp.X_op != O_constant 2089 || ! issbyte (opP->disp.exp.X_add_number)) 2090 losing++; 2091 else if (! m68k_quick 2092 && instring[3] != 'q' 2093 && instring[4] != 'q') 2094 losing++; 2095 break; 2096 2097 case 'O': 2098 if (opP->mode != DREG 2099 && opP->mode != IMMED 2100 && opP->mode != ABSL) 2101 losing++; 2102 break; 2103 2104 case 'Q': 2105 if (opP->mode != IMMED) 2106 losing++; 2107 else if (opP->disp.exp.X_op != O_constant 2108 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2109 losing++; 2110 else if (! m68k_quick 2111 && (strncmp (instring, "add", 3) == 0 2112 || strncmp (instring, "sub", 3) == 0) 2113 && instring[3] != 'q') 2114 losing++; 2115 break; 2116 2117 case 'R': 2118 if (opP->mode != DREG && opP->mode != AREG) 2119 losing++; 2120 break; 2121 2122 case 'r': 2123 if (opP->mode != AINDR 2124 && (opP->mode != BASE 2125 || (opP->reg != 0 2126 && opP->reg != ZADDR0) 2127 || opP->disp.exp.X_op != O_absent 2128 || ((opP->index.reg < DATA0 2129 || opP->index.reg > DATA7) 2130 && (opP->index.reg < ADDR0 2131 || opP->index.reg > ADDR7)) 2132 || opP->index.size != SIZE_UNSPEC 2133 || opP->index.scale != 1)) 2134 losing++; 2135 break; 2136 2137 case 's': 2138 if (opP->mode != CONTROL 2139 || ! (opP->reg == FPI 2140 || opP->reg == FPS 2141 || opP->reg == FPC)) 2142 losing++; 2143 break; 2144 2145 case 'S': 2146 if (opP->mode != CONTROL || opP->reg != SR) 2147 losing++; 2148 break; 2149 2150 case 't': 2151 if (opP->mode != IMMED) 2152 losing++; 2153 else if (opP->disp.exp.X_op != O_constant 2154 || TRUNC (opP->disp.exp.X_add_number) > 7) 2155 losing++; 2156 break; 2157 2158 case 'U': 2159 if (opP->mode != CONTROL || opP->reg != USP) 2160 losing++; 2161 break; 2162 2163 case 'x': 2164 if (opP->mode != IMMED) 2165 losing++; 2166 else if (opP->disp.exp.X_op != O_constant 2167 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff 2168 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) 2169 losing++; 2170 break; 2171 2172 case 'j': 2173 if (opP->mode != IMMED) 2174 losing++; 2175 else if (opP->disp.exp.X_op != O_constant 2176 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2177 losing++; 2178 break; 2179 2180 case 'K': 2181 if (opP->mode != IMMED) 2182 losing++; 2183 else if (opP->disp.exp.X_op != O_constant 2184 || TRUNC (opP->disp.exp.X_add_number) > 511) 2185 losing++; 2186 break; 2187 2188 /* JF these are out of order. We could put them 2189 in order if we were willing to put up with 2190 bunches of #ifdef m68851s in the code. 2191 2192 Don't forget that you need these operands 2193 to use 68030 MMU instructions. */ 2194 #ifndef NO_68851 2195 /* Memory addressing mode used by pflushr. */ 2196 case '|': 2197 if (opP->mode == CONTROL 2198 || opP->mode == FPREG 2199 || opP->mode == DREG 2200 || opP->mode == AREG 2201 || opP->mode == REGLST) 2202 losing++; 2203 /* We should accept immediate operands, but they 2204 supposedly have to be quad word, and we don't 2205 handle that. I would like to see what a Motorola 2206 assembler does before doing something here. */ 2207 if (opP->mode == IMMED) 2208 losing++; 2209 break; 2210 2211 case 'f': 2212 if (opP->mode != CONTROL 2213 || (opP->reg != SFC && opP->reg != DFC)) 2214 losing++; 2215 break; 2216 2217 case '0': 2218 if (opP->mode != CONTROL || opP->reg != TC) 2219 losing++; 2220 break; 2221 2222 case '1': 2223 if (opP->mode != CONTROL || opP->reg != AC) 2224 losing++; 2225 break; 2226 2227 case '2': 2228 if (opP->mode != CONTROL 2229 || (opP->reg != CAL 2230 && opP->reg != VAL 2231 && opP->reg != SCC)) 2232 losing++; 2233 break; 2234 2235 case 'V': 2236 if (opP->mode != CONTROL 2237 || opP->reg != VAL) 2238 losing++; 2239 break; 2240 2241 case 'W': 2242 if (opP->mode != CONTROL 2243 || (opP->reg != DRP 2244 && opP->reg != SRP 2245 && opP->reg != CRP)) 2246 losing++; 2247 break; 2248 2249 case 'w': 2250 switch (opP->mode) 2251 { 2252 case IMMED: 2253 case ABSL: 2254 case AREG: 2255 case DREG: 2256 case FPREG: 2257 case CONTROL: 2258 case POST: 2259 case PRE: 2260 case REGLST: 2261 losing++; 2262 break; 2263 default: 2264 break; 2265 } 2266 break; 2267 2268 case 'X': 2269 if (opP->mode != CONTROL 2270 || (!(opP->reg >= BAD && opP->reg <= BAD + 7) 2271 && !(opP->reg >= BAC && opP->reg <= BAC + 7))) 2272 losing++; 2273 break; 2274 2275 case 'Y': 2276 if (opP->mode != CONTROL || opP->reg != PSR) 2277 losing++; 2278 break; 2279 2280 case 'Z': 2281 if (opP->mode != CONTROL || opP->reg != PCSR) 2282 losing++; 2283 break; 2284 #endif 2285 case 'c': 2286 if (opP->mode != CONTROL 2287 || (opP->reg != NC 2288 && opP->reg != IC 2289 && opP->reg != DC 2290 && opP->reg != BC)) 2291 losing++; 2292 break; 2293 2294 case '_': 2295 if (opP->mode != ABSL) 2296 ++losing; 2297 break; 2298 2299 case 'u': 2300 if (opP->reg < DATA0L || opP->reg > ADDR7U) 2301 losing++; 2302 /* FIXME: kludge instead of fixing parser: 2303 upper/lower registers are *not* CONTROL 2304 registers, but ordinary ones. */ 2305 if ((opP->reg >= DATA0L && opP->reg <= DATA7L) 2306 || (opP->reg >= DATA0U && opP->reg <= DATA7U)) 2307 opP->mode = DREG; 2308 else 2309 opP->mode = AREG; 2310 break; 2311 2312 case 'y': 2313 if (!(opP->mode == AINDR 2314 || (opP->mode == DISP 2315 && !(opP->reg == PC || opP->reg == ZPC)))) 2316 losing++; 2317 break; 2318 2319 case 'z': 2320 if (!(opP->mode == AINDR || opP->mode == DISP)) 2321 losing++; 2322 break; 2323 2324 default: 2325 abort (); 2326 } 2327 2328 if (losing) 2329 break; 2330 } 2331 2332 /* Since we have found the correct instruction, copy 2333 in the modifications that we may have made. */ 2334 if (!losing) 2335 for (i = 0; i < opsfound; i++) 2336 the_ins.operands[i] = operands_backup[i]; 2337 } 2338 2339 if (!losing) 2340 break; 2341 2342 opcode = opcode->m_next; 2343 2344 if (!opcode) 2345 { 2346 if (ok_arch 2347 && !(ok_arch & current_architecture)) 2348 { 2349 const struct m68k_cpu *cpu; 2350 int any = 0; 2351 size_t space = 400; 2352 char *buf = xmalloc (space + 1); 2353 size_t len; 2354 int paren = 1; 2355 2356 the_ins.error = buf; 2357 /* Make sure there's a NUL at the end of the buffer -- strncpy 2358 won't write one when it runs out of buffer. */ 2359 buf[space] = 0; 2360 #define APPEND(STRING) \ 2361 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) 2362 2363 APPEND (_("invalid instruction for this architecture; needs ")); 2364 switch (ok_arch) 2365 { 2366 case mcfisa_a: 2367 APPEND ("ColdFire ISA_A"); 2368 break; 2369 case mcfhwdiv: 2370 APPEND ("ColdFire "); 2371 APPEND (_("hardware divide")); 2372 break; 2373 case mcfisa_aa: 2374 APPEND ("ColdFire ISA_A+"); 2375 break; 2376 case mcfisa_b: 2377 APPEND ("ColdFire ISA_B"); 2378 break; 2379 case mcfisa_c: 2380 APPEND ("ColdFire ISA_C"); 2381 break; 2382 case cfloat: 2383 APPEND ("ColdFire fpu"); 2384 break; 2385 case mfloat: 2386 APPEND ("M68K fpu"); 2387 break; 2388 case mmmu: 2389 APPEND ("M68K mmu"); 2390 break; 2391 case m68020up: 2392 APPEND ("68020 "); 2393 APPEND (_("or higher")); 2394 break; 2395 case m68000up: 2396 APPEND ("68000 "); 2397 APPEND (_("or higher")); 2398 break; 2399 case m68010up: 2400 APPEND ("68010 "); 2401 APPEND (_("or higher")); 2402 break; 2403 default: 2404 paren = 0; 2405 } 2406 if (paren) 2407 APPEND (" ("); 2408 2409 for (cpu = m68k_cpus; cpu->name; cpu++) 2410 if (!cpu->alias && (cpu->arch & ok_arch)) 2411 { 2412 const struct m68k_cpu *alias; 2413 int seen_master = 0; 2414 2415 if (any) 2416 APPEND (", "); 2417 any = 0; 2418 APPEND (cpu->name); 2419 for (alias = cpu; alias != m68k_cpus; alias--) 2420 if (alias[-1].alias >= 0) 2421 break; 2422 for (; !seen_master || alias->alias > 0; alias++) 2423 { 2424 if (!alias->alias) 2425 seen_master = 1; 2426 else 2427 { 2428 if (any) 2429 APPEND (", "); 2430 else 2431 APPEND (" ["); 2432 APPEND (alias->name); 2433 any = 1; 2434 } 2435 } 2436 if (any) 2437 APPEND ("]"); 2438 any = 1; 2439 } 2440 if (paren) 2441 APPEND (")"); 2442 #undef APPEND 2443 if (!space) 2444 { 2445 /* We ran out of space, so replace the end of the list 2446 with ellipsis. */ 2447 buf -= 4; 2448 while (*buf != ' ') 2449 buf--; 2450 strcpy (buf, " ..."); 2451 } 2452 } 2453 else 2454 the_ins.error = _("operands mismatch"); 2455 return; 2456 } 2457 2458 losing = 0; 2459 } 2460 2461 /* Now assemble it. */ 2462 the_ins.args = opcode->m_operands; 2463 the_ins.numargs = opcode->m_opnum; 2464 the_ins.numo = opcode->m_codenum; 2465 the_ins.opcode[0] = getone (opcode); 2466 the_ins.opcode[1] = gettwo (opcode); 2467 2468 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) 2469 { 2470 int have_disp = 0; 2471 int use_pl = 0; 2472 2473 /* This switch is a doozy. 2474 Watch the first step; its a big one! */ 2475 switch (s[0]) 2476 { 2477 2478 case '*': 2479 case '~': 2480 case '%': 2481 case ';': 2482 case '@': 2483 case '!': 2484 case '&': 2485 case '$': 2486 case '?': 2487 case '/': 2488 case '<': 2489 case '>': 2490 case 'b': 2491 case 'm': 2492 case 'n': 2493 case 'o': 2494 case 'p': 2495 case 'q': 2496 case 'v': 2497 case 'w': 2498 case 'y': 2499 case 'z': 2500 case '4': 2501 #ifndef NO_68851 2502 case '|': 2503 #endif 2504 switch (opP->mode) 2505 { 2506 case IMMED: 2507 tmpreg = 0x3c; /* 7.4 */ 2508 if (strchr ("bwl", s[1])) 2509 nextword = get_num (&opP->disp, 90); 2510 else 2511 nextword = get_num (&opP->disp, 0); 2512 if (isvar (&opP->disp)) 2513 add_fix (s[1], &opP->disp, 0, 0); 2514 switch (s[1]) 2515 { 2516 case 'b': 2517 if (!isbyte (nextword)) 2518 opP->error = _("operand out of range"); 2519 addword (nextword); 2520 baseo = 0; 2521 break; 2522 case 'w': 2523 if (!isword (nextword)) 2524 opP->error = _("operand out of range"); 2525 addword (nextword); 2526 baseo = 0; 2527 break; 2528 case 'W': 2529 if (!issword (nextword)) 2530 opP->error = _("operand out of range"); 2531 addword (nextword); 2532 baseo = 0; 2533 break; 2534 case 'l': 2535 addword (nextword >> 16); 2536 addword (nextword); 2537 baseo = 0; 2538 break; 2539 2540 case 'f': 2541 baseo = 2; 2542 outro = 8; 2543 break; 2544 case 'F': 2545 baseo = 4; 2546 outro = 11; 2547 break; 2548 case 'x': 2549 baseo = 6; 2550 outro = 15; 2551 break; 2552 case 'p': 2553 baseo = 6; 2554 outro = -1; 2555 break; 2556 default: 2557 abort (); 2558 } 2559 if (!baseo) 2560 break; 2561 2562 /* We gotta put out some float. */ 2563 if (op (&opP->disp) != O_big) 2564 { 2565 valueT val; 2566 int gencnt; 2567 2568 /* Can other cases happen here? */ 2569 if (op (&opP->disp) != O_constant) 2570 abort (); 2571 2572 val = (valueT) offs (&opP->disp); 2573 gencnt = 0; 2574 do 2575 { 2576 generic_bignum[gencnt] = (LITTLENUM_TYPE) val; 2577 val >>= LITTLENUM_NUMBER_OF_BITS; 2578 ++gencnt; 2579 } 2580 while (val != 0); 2581 offs (&opP->disp) = gencnt; 2582 } 2583 if (offs (&opP->disp) > 0) 2584 { 2585 if (offs (&opP->disp) > baseo) 2586 { 2587 as_warn (_("Bignum too big for %c format; truncated"), 2588 s[1]); 2589 offs (&opP->disp) = baseo; 2590 } 2591 baseo -= offs (&opP->disp); 2592 while (baseo--) 2593 addword (0); 2594 for (wordp = generic_bignum + offs (&opP->disp) - 1; 2595 offs (&opP->disp)--; 2596 --wordp) 2597 addword (*wordp); 2598 break; 2599 } 2600 gen_to_words (words, baseo, (long) outro); 2601 for (wordp = words; baseo--; wordp++) 2602 addword (*wordp); 2603 break; 2604 case DREG: 2605 tmpreg = opP->reg - DATA; /* 0.dreg */ 2606 break; 2607 case AREG: 2608 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ 2609 break; 2610 case AINDR: 2611 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2612 break; 2613 case ADEC: 2614 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ 2615 break; 2616 case AINC: 2617 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ 2618 break; 2619 case DISP: 2620 2621 nextword = get_num (&opP->disp, 90); 2622 2623 /* Convert mode 5 addressing with a zero offset into 2624 mode 2 addressing to reduce the instruction size by a 2625 word. */ 2626 if (! isvar (&opP->disp) 2627 && (nextword == 0) 2628 && (opP->disp.size == SIZE_UNSPEC) 2629 && (opP->reg >= ADDR0) 2630 && (opP->reg <= ADDR7)) 2631 { 2632 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2633 break; 2634 } 2635 2636 if (opP->reg == PC 2637 && ! isvar (&opP->disp) 2638 && m68k_abspcadd) 2639 { 2640 opP->disp.exp.X_op = O_symbol; 2641 opP->disp.exp.X_add_symbol = 2642 section_symbol (absolute_section); 2643 } 2644 2645 /* Force into index mode. Hope this works. */ 2646 2647 /* We do the first bit for 32-bit displacements, and the 2648 second bit for 16 bit ones. It is possible that we 2649 should make the default be WORD instead of LONG, but 2650 I think that'd break GCC, so we put up with a little 2651 inefficiency for the sake of working output. */ 2652 2653 if (!issword (nextword) 2654 || (isvar (&opP->disp) 2655 && ((opP->disp.size == SIZE_UNSPEC 2656 && flag_short_refs == 0 2657 && cpu_of_arch (current_architecture) >= m68020 2658 && ! arch_coldfire_p (current_architecture)) 2659 || opP->disp.size == SIZE_LONG))) 2660 { 2661 if (cpu_of_arch (current_architecture) < m68020 2662 || arch_coldfire_p (current_architecture)) 2663 opP->error = 2664 _("displacement too large for this architecture; needs 68020 or higher"); 2665 if (opP->reg == PC) 2666 tmpreg = 0x3B; /* 7.3 */ 2667 else 2668 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2669 if (isvar (&opP->disp)) 2670 { 2671 if (opP->reg == PC) 2672 { 2673 if (opP->disp.size == SIZE_LONG 2674 #ifdef OBJ_ELF 2675 /* If the displacement needs pic 2676 relocation it cannot be relaxed. */ 2677 || opP->disp.pic_reloc != pic_none 2678 #endif 2679 ) 2680 { 2681 addword (0x0170); 2682 add_fix ('l', &opP->disp, 1, 2); 2683 } 2684 else 2685 { 2686 add_frag (adds (&opP->disp), 2687 SEXT (offs (&opP->disp)), 2688 TAB (PCREL1632, SZ_UNDEF)); 2689 break; 2690 } 2691 } 2692 else 2693 { 2694 addword (0x0170); 2695 add_fix ('l', &opP->disp, 0, 0); 2696 } 2697 } 2698 else 2699 addword (0x0170); 2700 addword (nextword >> 16); 2701 } 2702 else 2703 { 2704 if (opP->reg == PC) 2705 tmpreg = 0x3A; /* 7.2 */ 2706 else 2707 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ 2708 2709 if (isvar (&opP->disp)) 2710 { 2711 if (opP->reg == PC) 2712 { 2713 add_fix ('w', &opP->disp, 1, 0); 2714 } 2715 else 2716 add_fix ('w', &opP->disp, 0, 0); 2717 } 2718 } 2719 addword (nextword); 2720 break; 2721 2722 case POST: 2723 case PRE: 2724 case BASE: 2725 nextword = 0; 2726 baseo = get_num (&opP->disp, 90); 2727 if (opP->mode == POST || opP->mode == PRE) 2728 outro = get_num (&opP->odisp, 90); 2729 /* Figure out the `addressing mode'. 2730 Also turn on the BASE_DISABLE bit, if needed. */ 2731 if (opP->reg == PC || opP->reg == ZPC) 2732 { 2733 tmpreg = 0x3b; /* 7.3 */ 2734 if (opP->reg == ZPC) 2735 nextword |= 0x80; 2736 } 2737 else if (opP->reg == 0) 2738 { 2739 nextword |= 0x80; 2740 tmpreg = 0x30; /* 6.garbage */ 2741 } 2742 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) 2743 { 2744 nextword |= 0x80; 2745 tmpreg = 0x30 + opP->reg - ZADDR0; 2746 } 2747 else 2748 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2749 2750 siz1 = opP->disp.size; 2751 if (opP->mode == POST || opP->mode == PRE) 2752 siz2 = opP->odisp.size; 2753 else 2754 siz2 = SIZE_UNSPEC; 2755 2756 /* Index register stuff. */ 2757 if (opP->index.reg != 0 2758 && opP->index.reg >= DATA 2759 && opP->index.reg <= ADDR7) 2760 { 2761 nextword |= (opP->index.reg - DATA) << 12; 2762 2763 if (opP->index.size == SIZE_LONG 2764 || (opP->index.size == SIZE_UNSPEC 2765 && m68k_index_width_default == SIZE_LONG)) 2766 nextword |= 0x800; 2767 2768 if ((opP->index.scale != 1 2769 && cpu_of_arch (current_architecture) < m68020) 2770 || (opP->index.scale == 8 2771 && (arch_coldfire_p (current_architecture) 2772 && !arch_coldfire_fpu (current_architecture)))) 2773 { 2774 opP->error = 2775 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); 2776 } 2777 2778 if (arch_coldfire_p (current_architecture) 2779 && opP->index.size == SIZE_WORD) 2780 opP->error = _("invalid index size for coldfire"); 2781 2782 switch (opP->index.scale) 2783 { 2784 case 1: 2785 break; 2786 case 2: 2787 nextword |= 0x200; 2788 break; 2789 case 4: 2790 nextword |= 0x400; 2791 break; 2792 case 8: 2793 nextword |= 0x600; 2794 break; 2795 default: 2796 abort (); 2797 } 2798 /* IF its simple, 2799 GET US OUT OF HERE! */ 2800 2801 /* Must be INDEX, with an index register. Address 2802 register cannot be ZERO-PC, and either :b was 2803 forced, or we know it will fit. For a 68000 or 2804 68010, force this mode anyways, because the 2805 larger modes aren't supported. */ 2806 if (opP->mode == BASE 2807 && ((opP->reg >= ADDR0 2808 && opP->reg <= ADDR7) 2809 || opP->reg == PC)) 2810 { 2811 if (siz1 == SIZE_BYTE 2812 || cpu_of_arch (current_architecture) < m68020 2813 || arch_coldfire_p (current_architecture) 2814 || (siz1 == SIZE_UNSPEC 2815 && ! isvar (&opP->disp) 2816 && issbyte (baseo))) 2817 { 2818 nextword += baseo & 0xff; 2819 addword (nextword); 2820 if (isvar (&opP->disp)) 2821 { 2822 /* Do a byte relocation. If it doesn't 2823 fit (possible on m68000) let the 2824 fixup processing complain later. */ 2825 if (opP->reg == PC) 2826 add_fix ('B', &opP->disp, 1, 1); 2827 else 2828 add_fix ('B', &opP->disp, 0, 0); 2829 } 2830 else if (siz1 != SIZE_BYTE) 2831 { 2832 if (siz1 != SIZE_UNSPEC) 2833 as_warn (_("Forcing byte displacement")); 2834 if (! issbyte (baseo)) 2835 opP->error = _("byte displacement out of range"); 2836 } 2837 2838 break; 2839 } 2840 else if (siz1 == SIZE_UNSPEC 2841 && opP->reg == PC 2842 && isvar (&opP->disp) 2843 && subs (&opP->disp) == NULL 2844 #ifdef OBJ_ELF 2845 /* If the displacement needs pic 2846 relocation it cannot be relaxed. */ 2847 && opP->disp.pic_reloc == pic_none 2848 #endif 2849 ) 2850 { 2851 /* The code in md_convert_frag_1 needs to be 2852 able to adjust nextword. Call frag_grow 2853 to ensure that we have enough space in 2854 the frag obstack to make all the bytes 2855 contiguous. */ 2856 frag_grow (14); 2857 nextword += baseo & 0xff; 2858 addword (nextword); 2859 add_frag (adds (&opP->disp), 2860 SEXT (offs (&opP->disp)), 2861 TAB (PCINDEX, SZ_UNDEF)); 2862 2863 break; 2864 } 2865 } 2866 } 2867 else 2868 { 2869 nextword |= 0x40; /* No index reg. */ 2870 if (opP->index.reg >= ZDATA0 2871 && opP->index.reg <= ZDATA7) 2872 nextword |= (opP->index.reg - ZDATA0) << 12; 2873 else if (opP->index.reg >= ZADDR0 2874 || opP->index.reg <= ZADDR7) 2875 nextword |= (opP->index.reg - ZADDR0 + 8) << 12; 2876 } 2877 2878 /* It isn't simple. */ 2879 2880 if (cpu_of_arch (current_architecture) < m68020 2881 || arch_coldfire_p (current_architecture)) 2882 opP->error = 2883 _("invalid operand mode for this architecture; needs 68020 or higher"); 2884 2885 nextword |= 0x100; 2886 /* If the guy specified a width, we assume that it is 2887 wide enough. Maybe it isn't. If so, we lose. */ 2888 switch (siz1) 2889 { 2890 case SIZE_UNSPEC: 2891 if (isvar (&opP->disp) 2892 ? m68k_rel32 2893 : ! issword (baseo)) 2894 { 2895 siz1 = SIZE_LONG; 2896 nextword |= 0x30; 2897 } 2898 else if (! isvar (&opP->disp) && baseo == 0) 2899 nextword |= 0x10; 2900 else 2901 { 2902 nextword |= 0x20; 2903 siz1 = SIZE_WORD; 2904 } 2905 break; 2906 case SIZE_BYTE: 2907 as_warn (_(":b not permitted; defaulting to :w")); 2908 /* Fall through. */ 2909 case SIZE_WORD: 2910 nextword |= 0x20; 2911 break; 2912 case SIZE_LONG: 2913 nextword |= 0x30; 2914 break; 2915 } 2916 2917 /* Figure out inner displacement stuff. */ 2918 if (opP->mode == POST || opP->mode == PRE) 2919 { 2920 if (cpu_of_arch (current_architecture) & cpu32) 2921 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); 2922 switch (siz2) 2923 { 2924 case SIZE_UNSPEC: 2925 if (isvar (&opP->odisp) 2926 ? m68k_rel32 2927 : ! issword (outro)) 2928 { 2929 siz2 = SIZE_LONG; 2930 nextword |= 0x3; 2931 } 2932 else if (! isvar (&opP->odisp) && outro == 0) 2933 nextword |= 0x1; 2934 else 2935 { 2936 nextword |= 0x2; 2937 siz2 = SIZE_WORD; 2938 } 2939 break; 2940 case 1: 2941 as_warn (_(":b not permitted; defaulting to :w")); 2942 /* Fall through. */ 2943 case 2: 2944 nextword |= 0x2; 2945 break; 2946 case 3: 2947 nextword |= 0x3; 2948 break; 2949 } 2950 if (opP->mode == POST 2951 && (nextword & 0x40) == 0) 2952 nextword |= 0x04; 2953 } 2954 addword (nextword); 2955 2956 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) 2957 { 2958 if (opP->reg == PC || opP->reg == ZPC) 2959 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); 2960 else 2961 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); 2962 } 2963 if (siz1 == SIZE_LONG) 2964 addword (baseo >> 16); 2965 if (siz1 != SIZE_UNSPEC) 2966 addword (baseo); 2967 2968 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) 2969 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); 2970 if (siz2 == SIZE_LONG) 2971 addword (outro >> 16); 2972 if (siz2 != SIZE_UNSPEC) 2973 addword (outro); 2974 2975 break; 2976 2977 case ABSL: 2978 nextword = get_num (&opP->disp, 90); 2979 switch (opP->disp.size) 2980 { 2981 default: 2982 abort (); 2983 case SIZE_UNSPEC: 2984 if (!isvar (&opP->disp) && issword (offs (&opP->disp))) 2985 { 2986 tmpreg = 0x38; /* 7.0 */ 2987 addword (nextword); 2988 break; 2989 } 2990 if (isvar (&opP->disp) 2991 && !subs (&opP->disp) 2992 && adds (&opP->disp) 2993 #ifdef OBJ_ELF 2994 /* If the displacement needs pic relocation it 2995 cannot be relaxed. */ 2996 && opP->disp.pic_reloc == pic_none 2997 #endif 2998 && !flag_long_jumps 2999 && !strchr ("~%&$?", s[0])) 3000 { 3001 tmpreg = 0x3A; /* 7.2 */ 3002 add_frag (adds (&opP->disp), 3003 SEXT (offs (&opP->disp)), 3004 TAB (ABSTOPCREL, SZ_UNDEF)); 3005 break; 3006 } 3007 /* Fall through into long. */ 3008 case SIZE_LONG: 3009 if (isvar (&opP->disp)) 3010 add_fix ('l', &opP->disp, 0, 0); 3011 3012 tmpreg = 0x39;/* 7.1 mode */ 3013 addword (nextword >> 16); 3014 addword (nextword); 3015 break; 3016 3017 case SIZE_BYTE: 3018 as_bad (_("unsupported byte value; use a different suffix")); 3019 /* Fall through. */ 3020 3021 case SIZE_WORD: 3022 if (isvar (&opP->disp)) 3023 add_fix ('w', &opP->disp, 0, 0); 3024 3025 tmpreg = 0x38;/* 7.0 mode */ 3026 addword (nextword); 3027 break; 3028 } 3029 break; 3030 case CONTROL: 3031 case FPREG: 3032 default: 3033 as_bad (_("unknown/incorrect operand")); 3034 /* abort (); */ 3035 } 3036 3037 /* If s[0] is '4', then this is for the mac instructions 3038 that can have a trailing_ampersand set. If so, set 0x100 3039 bit on tmpreg so install_gen_operand can check for it and 3040 set the appropriate bit (word2, bit 5). */ 3041 if (s[0] == '4') 3042 { 3043 if (opP->trailing_ampersand) 3044 tmpreg |= 0x100; 3045 } 3046 install_gen_operand (s[1], tmpreg); 3047 break; 3048 3049 case '#': 3050 case '^': 3051 switch (s[1]) 3052 { /* JF: I hate floating point! */ 3053 case 'j': 3054 tmpreg = 70; 3055 break; 3056 case '8': 3057 tmpreg = 20; 3058 break; 3059 case 'C': 3060 tmpreg = 50; 3061 break; 3062 case '3': 3063 default: 3064 tmpreg = 90; 3065 break; 3066 } 3067 tmpreg = get_num (&opP->disp, tmpreg); 3068 if (isvar (&opP->disp)) 3069 add_fix (s[1], &opP->disp, 0, 0); 3070 switch (s[1]) 3071 { 3072 case 'b': /* Danger: These do no check for 3073 certain types of overflow. 3074 user beware! */ 3075 if (!isbyte (tmpreg)) 3076 opP->error = _("out of range"); 3077 insop (tmpreg, opcode); 3078 if (isvar (&opP->disp)) 3079 the_ins.reloc[the_ins.nrel - 1].n = 3080 (opcode->m_codenum) * 2 + 1; 3081 break; 3082 case 'B': 3083 if (!issbyte (tmpreg)) 3084 opP->error = _("out of range"); 3085 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; 3086 if (isvar (&opP->disp)) 3087 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; 3088 break; 3089 case 'w': 3090 if (!isword (tmpreg)) 3091 opP->error = _("out of range"); 3092 insop (tmpreg, opcode); 3093 if (isvar (&opP->disp)) 3094 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3095 break; 3096 case 'W': 3097 if (!issword (tmpreg)) 3098 opP->error = _("out of range"); 3099 insop (tmpreg, opcode); 3100 if (isvar (&opP->disp)) 3101 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3102 break; 3103 case 'l': 3104 /* Because of the way insop works, we put these two out 3105 backwards. */ 3106 insop (tmpreg, opcode); 3107 insop (tmpreg >> 16, opcode); 3108 if (isvar (&opP->disp)) 3109 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3110 break; 3111 case '3': 3112 tmpreg &= 0xFF; 3113 case '8': 3114 case 'C': 3115 case 'j': 3116 install_operand (s[1], tmpreg); 3117 break; 3118 default: 3119 abort (); 3120 } 3121 break; 3122 3123 case '+': 3124 case '-': 3125 case 'A': 3126 case 'a': 3127 install_operand (s[1], opP->reg - ADDR); 3128 break; 3129 3130 case 'B': 3131 tmpreg = get_num (&opP->disp, 90); 3132 3133 switch (s[1]) 3134 { 3135 case 'B': 3136 add_fix ('B', &opP->disp, 1, -1); 3137 break; 3138 case 'W': 3139 add_fix ('w', &opP->disp, 1, 0); 3140 addword (0); 3141 break; 3142 case 'L': 3143 long_branch: 3144 the_ins.opcode[0] |= 0xff; 3145 add_fix ('l', &opP->disp, 1, 0); 3146 addword (0); 3147 addword (0); 3148 break; 3149 case 'g': /* Conditional branch */ 3150 have_disp = HAVE_LONG_CALL (current_architecture); 3151 goto var_branch; 3152 3153 case 'b': /* Unconditional branch */ 3154 have_disp = HAVE_LONG_BRANCH (current_architecture); 3155 use_pl = LONG_BRANCH_VIA_COND (current_architecture); 3156 goto var_branch; 3157 3158 case 's': /* Unconditional subroutine */ 3159 have_disp = HAVE_LONG_CALL (current_architecture); 3160 3161 var_branch: 3162 if (subs (&opP->disp) /* We can't relax it. */ 3163 #ifdef OBJ_ELF 3164 /* If the displacement needs pic relocation it cannot be 3165 relaxed. */ 3166 || opP->disp.pic_reloc != pic_none 3167 #endif 3168 || 0) 3169 { 3170 if (!have_disp) 3171 as_warn (_("Can't use long branches on this architecture")); 3172 goto long_branch; 3173 } 3174 3175 /* This could either be a symbol, or an absolute 3176 address. If it's an absolute address, turn it into 3177 an absolute jump right here and keep it out of the 3178 relaxer. */ 3179 if (adds (&opP->disp) == 0) 3180 { 3181 if (the_ins.opcode[0] == 0x6000) /* jbra */ 3182 the_ins.opcode[0] = 0x4EF9; 3183 else if (the_ins.opcode[0] == 0x6100) /* jbsr */ 3184 the_ins.opcode[0] = 0x4EB9; 3185 else /* jCC */ 3186 { 3187 the_ins.opcode[0] ^= 0x0100; 3188 the_ins.opcode[0] |= 0x0006; 3189 addword (0x4EF9); 3190 } 3191 add_fix ('l', &opP->disp, 0, 0); 3192 addword (0); 3193 addword (0); 3194 break; 3195 } 3196 3197 /* Now we know it's going into the relaxer. Now figure 3198 out which mode. We try in this order of preference: 3199 long branch, absolute jump, byte/word branches only. */ 3200 if (have_disp) 3201 add_frag (adds (&opP->disp), 3202 SEXT (offs (&opP->disp)), 3203 TAB (BRANCHBWL, SZ_UNDEF)); 3204 else if (! flag_keep_pcrel) 3205 { 3206 if ((the_ins.opcode[0] == 0x6000) 3207 || (the_ins.opcode[0] == 0x6100)) 3208 add_frag (adds (&opP->disp), 3209 SEXT (offs (&opP->disp)), 3210 TAB (BRABSJUNC, SZ_UNDEF)); 3211 else 3212 add_frag (adds (&opP->disp), 3213 SEXT (offs (&opP->disp)), 3214 TAB (BRABSJCOND, SZ_UNDEF)); 3215 } 3216 else 3217 add_frag (adds (&opP->disp), 3218 SEXT (offs (&opP->disp)), 3219 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) 3220 : TAB (BRANCHBW, SZ_UNDEF))); 3221 break; 3222 case 'w': 3223 if (isvar (&opP->disp)) 3224 { 3225 /* Check for DBcc instructions. We can relax them, 3226 but only if we have long branches and/or absolute 3227 jumps. */ 3228 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) 3229 && (HAVE_LONG_BRANCH (current_architecture) 3230 || ! flag_keep_pcrel)) 3231 { 3232 if (HAVE_LONG_BRANCH (current_architecture)) 3233 add_frag (adds (&opP->disp), 3234 SEXT (offs (&opP->disp)), 3235 TAB (DBCCLBR, SZ_UNDEF)); 3236 else 3237 add_frag (adds (&opP->disp), 3238 SEXT (offs (&opP->disp)), 3239 TAB (DBCCABSJ, SZ_UNDEF)); 3240 break; 3241 } 3242 add_fix ('w', &opP->disp, 1, 0); 3243 } 3244 addword (0); 3245 break; 3246 case 'C': /* Fixed size LONG coproc branches. */ 3247 add_fix ('l', &opP->disp, 1, 0); 3248 addword (0); 3249 addword (0); 3250 break; 3251 case 'c': /* Var size Coprocesssor branches. */ 3252 if (subs (&opP->disp) || (adds (&opP->disp) == 0)) 3253 { 3254 the_ins.opcode[the_ins.numo - 1] |= 0x40; 3255 add_fix ('l', &opP->disp, 1, 0); 3256 addword (0); 3257 addword (0); 3258 } 3259 else 3260 add_frag (adds (&opP->disp), 3261 SEXT (offs (&opP->disp)), 3262 TAB (FBRANCH, SZ_UNDEF)); 3263 break; 3264 default: 3265 abort (); 3266 } 3267 break; 3268 3269 case 'C': /* Ignore it. */ 3270 break; 3271 3272 case 'd': /* JF this is a kludge. */ 3273 install_operand ('s', opP->reg - ADDR); 3274 tmpreg = get_num (&opP->disp, 90); 3275 if (!issword (tmpreg)) 3276 { 3277 as_warn (_("Expression out of range, using 0")); 3278 tmpreg = 0; 3279 } 3280 addword (tmpreg); 3281 break; 3282 3283 case 'D': 3284 install_operand (s[1], opP->reg - DATA); 3285 break; 3286 3287 case 'e': /* EMAC ACCx, reg/reg. */ 3288 install_operand (s[1], opP->reg - ACC); 3289 break; 3290 3291 case 'E': /* Ignore it. */ 3292 break; 3293 3294 case 'F': 3295 install_operand (s[1], opP->reg - FP0); 3296 break; 3297 3298 case 'g': /* EMAC ACCEXTx. */ 3299 install_operand (s[1], opP->reg - ACCEXT01); 3300 break; 3301 3302 case 'G': /* Ignore it. */ 3303 case 'H': 3304 break; 3305 3306 case 'I': 3307 tmpreg = opP->reg - COP0; 3308 install_operand (s[1], tmpreg); 3309 break; 3310 3311 case 'i': /* MAC/EMAC scale factor. */ 3312 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); 3313 break; 3314 3315 case 'J': /* JF foo. */ 3316 switch (opP->reg) 3317 { 3318 case SFC: 3319 tmpreg = 0x000; 3320 break; 3321 case DFC: 3322 tmpreg = 0x001; 3323 break; 3324 case CACR: 3325 tmpreg = 0x002; 3326 break; 3327 case TC: 3328 case ASID: 3329 tmpreg = 0x003; 3330 break; 3331 case ACR0: 3332 case ITT0: 3333 tmpreg = 0x004; 3334 break; 3335 case ACR1: 3336 case ITT1: 3337 tmpreg = 0x005; 3338 break; 3339 case ACR2: 3340 case DTT0: 3341 tmpreg = 0x006; 3342 break; 3343 case ACR3: 3344 case DTT1: 3345 tmpreg = 0x007; 3346 break; 3347 case BUSCR: 3348 case MMUBAR: 3349 tmpreg = 0x008; 3350 break; 3351 case RGPIOBAR: 3352 tmpreg = 0x009; 3353 break; 3354 case ACR4: 3355 case ACR5: 3356 case ACR6: 3357 case ACR7: 3358 tmpreg = 0x00c + (opP->reg - ACR4); 3359 break; 3360 3361 case USP: 3362 tmpreg = 0x800; 3363 break; 3364 case VBR: 3365 tmpreg = 0x801; 3366 break; 3367 case CAAR: 3368 case CPUCR: 3369 tmpreg = 0x802; 3370 break; 3371 case MSP: 3372 tmpreg = 0x803; 3373 break; 3374 case ISP: 3375 tmpreg = 0x804; 3376 break; 3377 case MMUSR: 3378 tmpreg = 0x805; 3379 break; 3380 case URP: 3381 tmpreg = 0x806; 3382 break; 3383 case SRP: 3384 tmpreg = 0x807; 3385 break; 3386 case PCR: 3387 tmpreg = 0x808; 3388 break; 3389 case ROMBAR: 3390 case ROMBAR0: 3391 tmpreg = 0xC00; 3392 break; 3393 case ROMBAR1: 3394 tmpreg = 0xC01; 3395 break; 3396 case FLASHBAR: 3397 case RAMBAR0: 3398 case RAMBAR_ALT: 3399 tmpreg = 0xC04; 3400 break; 3401 case RAMBAR: 3402 case RAMBAR1: 3403 tmpreg = 0xC05; 3404 break; 3405 case MPCR: 3406 tmpreg = 0xC0C; 3407 break; 3408 case EDRAMBAR: 3409 tmpreg = 0xC0D; 3410 break; 3411 case MBAR0: 3412 case MBAR2: 3413 case SECMBAR: 3414 tmpreg = 0xC0E; 3415 break; 3416 case MBAR1: 3417 case MBAR: 3418 tmpreg = 0xC0F; 3419 break; 3420 case PCR1U0: 3421 tmpreg = 0xD02; 3422 break; 3423 case PCR1L0: 3424 tmpreg = 0xD03; 3425 break; 3426 case PCR2U0: 3427 tmpreg = 0xD04; 3428 break; 3429 case PCR2L0: 3430 tmpreg = 0xD05; 3431 break; 3432 case PCR3U0: 3433 tmpreg = 0xD06; 3434 break; 3435 case PCR3L0: 3436 tmpreg = 0xD07; 3437 break; 3438 case PCR1L1: 3439 tmpreg = 0xD0A; 3440 break; 3441 case PCR1U1: 3442 tmpreg = 0xD0B; 3443 break; 3444 case PCR2L1: 3445 tmpreg = 0xD0C; 3446 break; 3447 case PCR2U1: 3448 tmpreg = 0xD0D; 3449 break; 3450 case PCR3L1: 3451 tmpreg = 0xD0E; 3452 break; 3453 case PCR3U1: 3454 tmpreg = 0xD0F; 3455 break; 3456 case CAC: 3457 tmpreg = 0xFFE; 3458 break; 3459 case MBO: 3460 tmpreg = 0xFFF; 3461 break; 3462 default: 3463 abort (); 3464 } 3465 install_operand (s[1], tmpreg); 3466 break; 3467 3468 case 'k': 3469 tmpreg = get_num (&opP->disp, 55); 3470 install_operand (s[1], tmpreg & 0x7f); 3471 break; 3472 3473 case 'l': 3474 tmpreg = opP->mask; 3475 if (s[1] == 'w') 3476 { 3477 if (tmpreg & 0x7FF0000) 3478 as_bad (_("Floating point register in register list")); 3479 insop (reverse_16_bits (tmpreg), opcode); 3480 } 3481 else 3482 { 3483 if (tmpreg & 0x700FFFF) 3484 as_bad (_("Wrong register in floating-point reglist")); 3485 install_operand (s[1], reverse_8_bits (tmpreg >> 16)); 3486 } 3487 break; 3488 3489 case 'L': 3490 tmpreg = opP->mask; 3491 if (s[1] == 'w') 3492 { 3493 if (tmpreg & 0x7FF0000) 3494 as_bad (_("Floating point register in register list")); 3495 insop (tmpreg, opcode); 3496 } 3497 else if (s[1] == '8') 3498 { 3499 if (tmpreg & 0x0FFFFFF) 3500 as_bad (_("incorrect register in reglist")); 3501 install_operand (s[1], tmpreg >> 24); 3502 } 3503 else 3504 { 3505 if (tmpreg & 0x700FFFF) 3506 as_bad (_("wrong register in floating-point reglist")); 3507 else 3508 install_operand (s[1], tmpreg >> 16); 3509 } 3510 break; 3511 3512 case 'M': 3513 install_operand (s[1], get_num (&opP->disp, 60)); 3514 break; 3515 3516 case 'O': 3517 tmpreg = ((opP->mode == DREG) 3518 ? 0x20 + (int) (opP->reg - DATA) 3519 : (get_num (&opP->disp, 40) & 0x1F)); 3520 install_operand (s[1], tmpreg); 3521 break; 3522 3523 case 'Q': 3524 tmpreg = get_num (&opP->disp, 10); 3525 if (tmpreg == 8) 3526 tmpreg = 0; 3527 install_operand (s[1], tmpreg); 3528 break; 3529 3530 case 'R': 3531 /* This depends on the fact that ADDR registers are eight 3532 more than their corresponding DATA regs, so the result 3533 will have the ADDR_REG bit set. */ 3534 install_operand (s[1], opP->reg - DATA); 3535 break; 3536 3537 case 'r': 3538 if (opP->mode == AINDR) 3539 install_operand (s[1], opP->reg - DATA); 3540 else 3541 install_operand (s[1], opP->index.reg - DATA); 3542 break; 3543 3544 case 's': 3545 if (opP->reg == FPI) 3546 tmpreg = 0x1; 3547 else if (opP->reg == FPS) 3548 tmpreg = 0x2; 3549 else if (opP->reg == FPC) 3550 tmpreg = 0x4; 3551 else 3552 abort (); 3553 install_operand (s[1], tmpreg); 3554 break; 3555 3556 case 'S': /* Ignore it. */ 3557 break; 3558 3559 case 'T': 3560 install_operand (s[1], get_num (&opP->disp, 30)); 3561 break; 3562 3563 case 'U': /* Ignore it. */ 3564 break; 3565 3566 case 'c': 3567 switch (opP->reg) 3568 { 3569 case NC: 3570 tmpreg = 0; 3571 break; 3572 case DC: 3573 tmpreg = 1; 3574 break; 3575 case IC: 3576 tmpreg = 2; 3577 break; 3578 case BC: 3579 tmpreg = 3; 3580 break; 3581 default: 3582 as_fatal (_("failed sanity check")); 3583 } /* switch on cache token. */ 3584 install_operand (s[1], tmpreg); 3585 break; 3586 #ifndef NO_68851 3587 /* JF: These are out of order, I fear. */ 3588 case 'f': 3589 switch (opP->reg) 3590 { 3591 case SFC: 3592 tmpreg = 0; 3593 break; 3594 case DFC: 3595 tmpreg = 1; 3596 break; 3597 default: 3598 abort (); 3599 } 3600 install_operand (s[1], tmpreg); 3601 break; 3602 3603 case '0': 3604 case '1': 3605 case '2': 3606 switch (opP->reg) 3607 { 3608 case TC: 3609 tmpreg = 0; 3610 break; 3611 case CAL: 3612 tmpreg = 4; 3613 break; 3614 case VAL: 3615 tmpreg = 5; 3616 break; 3617 case SCC: 3618 tmpreg = 6; 3619 break; 3620 case AC: 3621 tmpreg = 7; 3622 break; 3623 default: 3624 abort (); 3625 } 3626 install_operand (s[1], tmpreg); 3627 break; 3628 3629 case 'V': 3630 if (opP->reg == VAL) 3631 break; 3632 abort (); 3633 3634 case 'W': 3635 switch (opP->reg) 3636 { 3637 case DRP: 3638 tmpreg = 1; 3639 break; 3640 case SRP: 3641 tmpreg = 2; 3642 break; 3643 case CRP: 3644 tmpreg = 3; 3645 break; 3646 default: 3647 abort (); 3648 } 3649 install_operand (s[1], tmpreg); 3650 break; 3651 3652 case 'X': 3653 switch (opP->reg) 3654 { 3655 case BAD: 3656 case BAD + 1: 3657 case BAD + 2: 3658 case BAD + 3: 3659 case BAD + 4: 3660 case BAD + 5: 3661 case BAD + 6: 3662 case BAD + 7: 3663 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); 3664 break; 3665 3666 case BAC: 3667 case BAC + 1: 3668 case BAC + 2: 3669 case BAC + 3: 3670 case BAC + 4: 3671 case BAC + 5: 3672 case BAC + 6: 3673 case BAC + 7: 3674 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); 3675 break; 3676 3677 default: 3678 abort (); 3679 } 3680 install_operand (s[1], tmpreg); 3681 break; 3682 case 'Y': 3683 know (opP->reg == PSR); 3684 break; 3685 case 'Z': 3686 know (opP->reg == PCSR); 3687 break; 3688 #endif /* m68851 */ 3689 case '3': 3690 switch (opP->reg) 3691 { 3692 case TT0: 3693 tmpreg = 2; 3694 break; 3695 case TT1: 3696 tmpreg = 3; 3697 break; 3698 default: 3699 abort (); 3700 } 3701 install_operand (s[1], tmpreg); 3702 break; 3703 case 't': 3704 tmpreg = get_num (&opP->disp, 20); 3705 install_operand (s[1], tmpreg); 3706 break; 3707 case '_': /* used only for move16 absolute 32-bit address. */ 3708 if (isvar (&opP->disp)) 3709 add_fix ('l', &opP->disp, 0, 0); 3710 tmpreg = get_num (&opP->disp, 90); 3711 addword (tmpreg >> 16); 3712 addword (tmpreg & 0xFFFF); 3713 break; 3714 case 'u': 3715 install_operand (s[1], opP->reg - DATA0L); 3716 opP->reg -= (DATA0L); 3717 opP->reg &= 0x0F; /* remove upper/lower bit. */ 3718 break; 3719 case 'x': 3720 tmpreg = get_num (&opP->disp, 80); 3721 if (tmpreg == -1) 3722 tmpreg = 0; 3723 install_operand (s[1], tmpreg); 3724 break; 3725 case 'j': 3726 tmpreg = get_num (&opP->disp, 10); 3727 install_operand (s[1], tmpreg - 1); 3728 break; 3729 case 'K': 3730 tmpreg = get_num (&opP->disp, 65); 3731 install_operand (s[1], tmpreg); 3732 break; 3733 default: 3734 abort (); 3735 } 3736 } 3737 3738 /* By the time whe get here (FINALLY) the_ins contains the complete 3739 instruction, ready to be emitted. . . */ 3740 } 3741 3742 static int 3743 reverse_16_bits (int in) 3744 { 3745 int out = 0; 3746 int n; 3747 3748 static int mask[16] = 3749 { 3750 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3751 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 3752 }; 3753 for (n = 0; n < 16; n++) 3754 { 3755 if (in & mask[n]) 3756 out |= mask[15 - n]; 3757 } 3758 return out; 3759 } /* reverse_16_bits() */ 3760 3761 static int 3762 reverse_8_bits (int in) 3763 { 3764 int out = 0; 3765 int n; 3766 3767 static int mask[8] = 3768 { 3769 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3770 }; 3771 3772 for (n = 0; n < 8; n++) 3773 { 3774 if (in & mask[n]) 3775 out |= mask[7 - n]; 3776 } 3777 return out; 3778 } /* reverse_8_bits() */ 3779 3780 /* Cause an extra frag to be generated here, inserting up to 3781 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be 3782 generated; its primary type is rs_machine_dependent. 3783 3784 The TYPE parameter is also used by md_convert_frag_1 and 3785 md_estimate_size_before_relax. The appropriate type of fixup will 3786 be emitted by md_convert_frag_1. 3787 3788 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 3789 static void 3790 install_operand (int mode, int val) 3791 { 3792 switch (mode) 3793 { 3794 case 's': 3795 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ 3796 break; 3797 case 'd': 3798 the_ins.opcode[0] |= val << 9; 3799 break; 3800 case 'E': 3801 the_ins.opcode[1] |= val << 9; 3802 break; 3803 case '1': 3804 the_ins.opcode[1] |= val << 12; 3805 break; 3806 case '2': 3807 the_ins.opcode[1] |= val << 6; 3808 break; 3809 case '3': 3810 the_ins.opcode[1] |= val; 3811 break; 3812 case '4': 3813 the_ins.opcode[2] |= val << 12; 3814 break; 3815 case '5': 3816 the_ins.opcode[2] |= val << 6; 3817 break; 3818 case '6': 3819 /* DANGER! This is a hack to force cas2l and cas2w cmds to be 3820 three words long! */ 3821 the_ins.numo++; 3822 the_ins.opcode[2] |= val; 3823 break; 3824 case '7': 3825 the_ins.opcode[1] |= val << 7; 3826 break; 3827 case '8': 3828 the_ins.opcode[1] |= val << 10; 3829 break; 3830 #ifndef NO_68851 3831 case '9': 3832 the_ins.opcode[1] |= val << 5; 3833 break; 3834 #endif 3835 3836 case 't': 3837 the_ins.opcode[1] |= (val << 10) | (val << 7); 3838 break; 3839 case 'D': 3840 the_ins.opcode[1] |= (val << 12) | val; 3841 break; 3842 case 'g': 3843 the_ins.opcode[0] |= val = 0xff; 3844 break; 3845 case 'i': 3846 the_ins.opcode[0] |= val << 9; 3847 break; 3848 case 'C': 3849 the_ins.opcode[1] |= val; 3850 break; 3851 case 'j': 3852 the_ins.opcode[1] |= val; 3853 the_ins.numo++; /* What a hack. */ 3854 break; 3855 case 'k': 3856 the_ins.opcode[1] |= val << 4; 3857 break; 3858 case 'b': 3859 case 'w': 3860 case 'W': 3861 case 'l': 3862 break; 3863 case 'e': 3864 the_ins.opcode[0] |= (val << 6); 3865 break; 3866 case 'L': 3867 the_ins.opcode[1] = (val >> 16); 3868 the_ins.opcode[2] = val & 0xffff; 3869 break; 3870 case 'm': 3871 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3872 the_ins.opcode[0] |= ((val & 0x7) << 9); 3873 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3874 break; 3875 case 'n': /* MAC/EMAC Rx on !load. */ 3876 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3877 the_ins.opcode[0] |= ((val & 0x7) << 9); 3878 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3879 break; 3880 case 'o': /* MAC/EMAC Rx on load. */ 3881 the_ins.opcode[1] |= val << 12; 3882 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3883 break; 3884 case 'M': /* MAC/EMAC Ry on !load. */ 3885 the_ins.opcode[0] |= (val & 0xF); 3886 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3887 break; 3888 case 'N': /* MAC/EMAC Ry on load. */ 3889 the_ins.opcode[1] |= (val & 0xF); 3890 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3891 break; 3892 case 'h': 3893 the_ins.opcode[1] |= ((val != 1) << 10); 3894 break; 3895 case 'F': 3896 the_ins.opcode[0] |= ((val & 0x3) << 9); 3897 break; 3898 case 'f': 3899 the_ins.opcode[0] |= ((val & 0x3) << 0); 3900 break; 3901 case 'G': /* EMAC accumulator in a EMAC load instruction. */ 3902 the_ins.opcode[0] |= ((~val & 0x1) << 7); 3903 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3904 break; 3905 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ 3906 the_ins.opcode[0] |= ((val & 0x1) << 7); 3907 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3908 break; 3909 case 'I': 3910 the_ins.opcode[1] |= ((val & 0x3) << 9); 3911 break; 3912 case ']': 3913 the_ins.opcode[0] |= (val & 0x1) <<10; 3914 break; 3915 case 'c': 3916 default: 3917 as_fatal (_("failed sanity check.")); 3918 } 3919 } 3920 3921 static void 3922 install_gen_operand (int mode, int val) 3923 { 3924 switch (mode) 3925 { 3926 case '/': /* Special for mask loads for mac/msac insns with 3927 possible mask; trailing_ampersend set in bit 8. */ 3928 the_ins.opcode[0] |= (val & 0x3f); 3929 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); 3930 break; 3931 case 's': 3932 the_ins.opcode[0] |= val; 3933 break; 3934 case 'd': 3935 /* This is a kludge!!! */ 3936 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; 3937 break; 3938 case 'b': 3939 case 'w': 3940 case 'l': 3941 case 'f': 3942 case 'F': 3943 case 'x': 3944 case 'p': 3945 the_ins.opcode[0] |= val; 3946 break; 3947 /* more stuff goes here. */ 3948 default: 3949 as_fatal (_("failed sanity check.")); 3950 } 3951 } 3952 3953 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and 3954 then deal with the bitfield hack. */ 3955 3956 static char * 3957 crack_operand (char *str, struct m68k_op *opP) 3958 { 3959 int parens; 3960 int c; 3961 char *beg_str; 3962 int inquote = 0; 3963 3964 if (!str) 3965 { 3966 return str; 3967 } 3968 beg_str = str; 3969 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) 3970 { 3971 if (! inquote) 3972 { 3973 if (*str == '(') 3974 parens++; 3975 else if (*str == ')') 3976 { 3977 if (!parens) 3978 { /* ERROR. */ 3979 opP->error = _("Extra )"); 3980 return str; 3981 } 3982 --parens; 3983 } 3984 } 3985 if (flag_mri && *str == '\'') 3986 inquote = ! inquote; 3987 } 3988 if (!*str && parens) 3989 { /* ERROR. */ 3990 opP->error = _("Missing )"); 3991 return str; 3992 } 3993 c = *str; 3994 *str = '\0'; 3995 if (m68k_ip_op (beg_str, opP) != 0) 3996 { 3997 *str = c; 3998 return str; 3999 } 4000 *str = c; 4001 if (c == '}') 4002 c = *++str; /* JF bitfield hack. */ 4003 if (c) 4004 { 4005 c = *++str; 4006 if (!c) 4007 as_bad (_("Missing operand")); 4008 } 4009 4010 /* Detect MRI REG symbols and convert them to REGLSTs. */ 4011 if (opP->mode == CONTROL && (int)opP->reg < 0) 4012 { 4013 opP->mode = REGLST; 4014 opP->mask = ~(int)opP->reg; 4015 opP->reg = 0; 4016 } 4017 4018 return str; 4019 } 4020 4021 /* This is the guts of the machine-dependent assembler. STR points to a 4022 machine dependent instruction. This function is supposed to emit 4023 the frags/bytes it assembles to. 4024 */ 4025 4026 static void 4027 insert_reg (const char *regname, int regnum) 4028 { 4029 char buf[100]; 4030 int i; 4031 4032 #ifdef REGISTER_PREFIX 4033 if (!flag_reg_prefix_optional) 4034 { 4035 buf[0] = REGISTER_PREFIX; 4036 strcpy (buf + 1, regname); 4037 regname = buf; 4038 } 4039 #endif 4040 4041 symbol_table_insert (symbol_new (regname, reg_section, regnum, 4042 &zero_address_frag)); 4043 4044 for (i = 0; regname[i]; i++) 4045 buf[i] = TOUPPER (regname[i]); 4046 buf[i] = '\0'; 4047 4048 symbol_table_insert (symbol_new (buf, reg_section, regnum, 4049 &zero_address_frag)); 4050 } 4051 4052 struct init_entry 4053 { 4054 const char *name; 4055 int number; 4056 }; 4057 4058 static const struct init_entry init_table[] = 4059 { 4060 { "d0", DATA0 }, 4061 { "d1", DATA1 }, 4062 { "d2", DATA2 }, 4063 { "d3", DATA3 }, 4064 { "d4", DATA4 }, 4065 { "d5", DATA5 }, 4066 { "d6", DATA6 }, 4067 { "d7", DATA7 }, 4068 { "a0", ADDR0 }, 4069 { "a1", ADDR1 }, 4070 { "a2", ADDR2 }, 4071 { "a3", ADDR3 }, 4072 { "a4", ADDR4 }, 4073 { "a5", ADDR5 }, 4074 { "a6", ADDR6 }, 4075 { "fp", ADDR6 }, 4076 { "a7", ADDR7 }, 4077 { "sp", ADDR7 }, 4078 { "ssp", ADDR7 }, 4079 { "fp0", FP0 }, 4080 { "fp1", FP1 }, 4081 { "fp2", FP2 }, 4082 { "fp3", FP3 }, 4083 { "fp4", FP4 }, 4084 { "fp5", FP5 }, 4085 { "fp6", FP6 }, 4086 { "fp7", FP7 }, 4087 { "fpi", FPI }, 4088 { "fpiar", FPI }, 4089 { "fpc", FPI }, 4090 { "fps", FPS }, 4091 { "fpsr", FPS }, 4092 { "fpc", FPC }, 4093 { "fpcr", FPC }, 4094 { "control", FPC }, 4095 { "status", FPS }, 4096 { "iaddr", FPI }, 4097 4098 { "cop0", COP0 }, 4099 { "cop1", COP1 }, 4100 { "cop2", COP2 }, 4101 { "cop3", COP3 }, 4102 { "cop4", COP4 }, 4103 { "cop5", COP5 }, 4104 { "cop6", COP6 }, 4105 { "cop7", COP7 }, 4106 { "pc", PC }, 4107 { "zpc", ZPC }, 4108 { "sr", SR }, 4109 4110 { "ccr", CCR }, 4111 { "cc", CCR }, 4112 4113 { "acc", ACC }, 4114 { "acc0", ACC }, 4115 { "acc1", ACC1 }, 4116 { "acc2", ACC2 }, 4117 { "acc3", ACC3 }, 4118 { "accext01", ACCEXT01 }, 4119 { "accext23", ACCEXT23 }, 4120 { "macsr", MACSR }, 4121 { "mask", MASK }, 4122 4123 /* Control registers. */ 4124 { "sfc", SFC }, /* Source Function Code. */ 4125 { "sfcr", SFC }, 4126 { "dfc", DFC }, /* Destination Function Code. */ 4127 { "dfcr", DFC }, 4128 { "cacr", CACR }, /* Cache Control Register. */ 4129 { "caar", CAAR }, /* Cache Address Register. */ 4130 { "cpucr", CPUCR }, /* CPU Control Register. */ 4131 4132 { "usp", USP }, /* User Stack Pointer. */ 4133 { "vbr", VBR }, /* Vector Base Register. */ 4134 { "msp", MSP }, /* Master Stack Pointer. */ 4135 { "isp", ISP }, /* Interrupt Stack Pointer. */ 4136 4137 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ 4138 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ 4139 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ 4140 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ 4141 4142 /* 68ec040 versions of same */ 4143 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ 4144 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ 4145 { "dacr0", DTT0 }, /* Data Access Control Register 0. */ 4146 { "dacr1", DTT1 }, /* Data Access Control Register 0. */ 4147 4148 /* Coldfire versions of same. The ColdFire programmer's reference 4149 manual indicated that the order is 2,3,0,1, but Ken Rose 4150 <rose (at) netcom.com> says that 0,1,2,3 is the correct order. */ 4151 { "acr0", ACR0 }, /* Access Control Unit 0. */ 4152 { "acr1", ACR1 }, /* Access Control Unit 1. */ 4153 { "acr2", ACR2 }, /* Access Control Unit 2. */ 4154 { "acr3", ACR3 }, /* Access Control Unit 3. */ 4155 { "acr4", ACR4 }, /* Access Control Unit 4. */ 4156 { "acr5", ACR5 }, /* Access Control Unit 5. */ 4157 { "acr6", ACR6 }, /* Access Control Unit 6. */ 4158 { "acr7", ACR7 }, /* Access Control Unit 7. */ 4159 4160 { "tc", TC }, /* MMU Translation Control Register. */ 4161 { "tcr", TC }, 4162 { "asid", ASID }, 4163 4164 { "mmusr", MMUSR }, /* MMU Status Register. */ 4165 { "srp", SRP }, /* User Root Pointer. */ 4166 { "urp", URP }, /* Supervisor Root Pointer. */ 4167 4168 { "buscr", BUSCR }, 4169 { "mmubar", MMUBAR }, 4170 { "pcr", PCR }, 4171 4172 { "rombar", ROMBAR }, /* ROM Base Address Register. */ 4173 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ 4174 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ 4175 { "mbar", MBAR }, /* Module Base Address Register. */ 4176 4177 { "mbar0", MBAR0 }, /* mcfv4e registers. */ 4178 { "mbar1", MBAR1 }, /* mcfv4e registers. */ 4179 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ 4180 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ 4181 { "mpcr", MPCR }, /* mcfv4e registers. */ 4182 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ 4183 { "secmbar", SECMBAR }, /* mcfv4e registers. */ 4184 { "asid", TC }, /* mcfv4e registers. */ 4185 { "mmubar", BUSCR }, /* mcfv4e registers. */ 4186 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ 4187 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ 4188 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ 4189 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ 4190 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ 4191 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ 4192 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ 4193 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ 4194 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ 4195 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ 4196 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ 4197 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ 4198 4199 { "flashbar", FLASHBAR }, /* mcf528x registers. */ 4200 { "rambar", RAMBAR }, /* mcf528x registers. */ 4201 4202 { "mbar2", MBAR2 }, /* mcf5249 registers. */ 4203 4204 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */ 4205 4206 { "cac", CAC }, /* fido registers. */ 4207 { "mbb", MBO }, /* fido registers (obsolete). */ 4208 { "mbo", MBO }, /* fido registers. */ 4209 /* End of control registers. */ 4210 4211 { "ac", AC }, 4212 { "bc", BC }, 4213 { "cal", CAL }, 4214 { "crp", CRP }, 4215 { "drp", DRP }, 4216 { "pcsr", PCSR }, 4217 { "psr", PSR }, 4218 { "scc", SCC }, 4219 { "val", VAL }, 4220 { "bad0", BAD0 }, 4221 { "bad1", BAD1 }, 4222 { "bad2", BAD2 }, 4223 { "bad3", BAD3 }, 4224 { "bad4", BAD4 }, 4225 { "bad5", BAD5 }, 4226 { "bad6", BAD6 }, 4227 { "bad7", BAD7 }, 4228 { "bac0", BAC0 }, 4229 { "bac1", BAC1 }, 4230 { "bac2", BAC2 }, 4231 { "bac3", BAC3 }, 4232 { "bac4", BAC4 }, 4233 { "bac5", BAC5 }, 4234 { "bac6", BAC6 }, 4235 { "bac7", BAC7 }, 4236 4237 { "ic", IC }, 4238 { "dc", DC }, 4239 { "nc", NC }, 4240 4241 { "tt0", TT0 }, 4242 { "tt1", TT1 }, 4243 /* 68ec030 versions of same. */ 4244 { "ac0", TT0 }, 4245 { "ac1", TT1 }, 4246 /* 68ec030 access control unit, identical to 030 MMU status reg. */ 4247 { "acusr", PSR }, 4248 4249 /* Suppressed data and address registers. */ 4250 { "zd0", ZDATA0 }, 4251 { "zd1", ZDATA1 }, 4252 { "zd2", ZDATA2 }, 4253 { "zd3", ZDATA3 }, 4254 { "zd4", ZDATA4 }, 4255 { "zd5", ZDATA5 }, 4256 { "zd6", ZDATA6 }, 4257 { "zd7", ZDATA7 }, 4258 { "za0", ZADDR0 }, 4259 { "za1", ZADDR1 }, 4260 { "za2", ZADDR2 }, 4261 { "za3", ZADDR3 }, 4262 { "za4", ZADDR4 }, 4263 { "za5", ZADDR5 }, 4264 { "za6", ZADDR6 }, 4265 { "za7", ZADDR7 }, 4266 4267 /* Upper and lower data and address registers, used by macw and msacw. */ 4268 { "d0l", DATA0L }, 4269 { "d1l", DATA1L }, 4270 { "d2l", DATA2L }, 4271 { "d3l", DATA3L }, 4272 { "d4l", DATA4L }, 4273 { "d5l", DATA5L }, 4274 { "d6l", DATA6L }, 4275 { "d7l", DATA7L }, 4276 4277 { "a0l", ADDR0L }, 4278 { "a1l", ADDR1L }, 4279 { "a2l", ADDR2L }, 4280 { "a3l", ADDR3L }, 4281 { "a4l", ADDR4L }, 4282 { "a5l", ADDR5L }, 4283 { "a6l", ADDR6L }, 4284 { "a7l", ADDR7L }, 4285 4286 { "d0u", DATA0U }, 4287 { "d1u", DATA1U }, 4288 { "d2u", DATA2U }, 4289 { "d3u", DATA3U }, 4290 { "d4u", DATA4U }, 4291 { "d5u", DATA5U }, 4292 { "d6u", DATA6U }, 4293 { "d7u", DATA7U }, 4294 4295 { "a0u", ADDR0U }, 4296 { "a1u", ADDR1U }, 4297 { "a2u", ADDR2U }, 4298 { "a3u", ADDR3U }, 4299 { "a4u", ADDR4U }, 4300 { "a5u", ADDR5U }, 4301 { "a6u", ADDR6U }, 4302 { "a7u", ADDR7U }, 4303 4304 { 0, 0 } 4305 }; 4306 4307 static void 4308 init_regtable (void) 4309 { 4310 int i; 4311 for (i = 0; init_table[i].name; i++) 4312 insert_reg (init_table[i].name, init_table[i].number); 4313 } 4314 4315 void 4316 md_assemble (char *str) 4317 { 4318 const char *er; 4319 short *fromP; 4320 char *toP = NULL; 4321 int m, n = 0; 4322 char *to_beg_P; 4323 int shorts_this_frag; 4324 fixS *fixP; 4325 4326 if (!selected_cpu && !selected_arch) 4327 { 4328 /* We've not selected an architecture yet. Set the default 4329 now. We do this lazily so that an initial .cpu or .arch directive 4330 can specify. */ 4331 if (!m68k_set_cpu (TARGET_CPU, 1, 1)) 4332 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); 4333 } 4334 if (!initialized) 4335 m68k_init_arch (); 4336 4337 /* In MRI mode, the instruction and operands are separated by a 4338 space. Anything following the operands is a comment. The label 4339 has already been removed. */ 4340 if (flag_mri) 4341 { 4342 char *s; 4343 int fields = 0; 4344 int infield = 0; 4345 int inquote = 0; 4346 4347 for (s = str; *s != '\0'; s++) 4348 { 4349 if ((*s == ' ' || *s == '\t') && ! inquote) 4350 { 4351 if (infield) 4352 { 4353 ++fields; 4354 if (fields >= 2) 4355 { 4356 *s = '\0'; 4357 break; 4358 } 4359 infield = 0; 4360 } 4361 } 4362 else 4363 { 4364 if (! infield) 4365 infield = 1; 4366 if (*s == '\'') 4367 inquote = ! inquote; 4368 } 4369 } 4370 } 4371 4372 memset (&the_ins, '\0', sizeof (the_ins)); 4373 m68k_ip (str); 4374 er = the_ins.error; 4375 if (!er) 4376 { 4377 for (n = 0; n < the_ins.numargs; n++) 4378 if (the_ins.operands[n].error) 4379 { 4380 er = the_ins.operands[n].error; 4381 break; 4382 } 4383 } 4384 if (er) 4385 { 4386 as_bad (_("%s -- statement `%s' ignored"), er, str); 4387 return; 4388 } 4389 4390 /* If there is a current label, record that it marks an instruction. */ 4391 if (current_label != NULL) 4392 { 4393 current_label->text = 1; 4394 current_label = NULL; 4395 } 4396 4397 #ifdef OBJ_ELF 4398 /* Tie dwarf2 debug info to the address at the start of the insn. */ 4399 dwarf2_emit_insn (0); 4400 #endif 4401 4402 if (the_ins.nfrag == 0) 4403 { 4404 /* No frag hacking involved; just put it out. */ 4405 toP = frag_more (2 * the_ins.numo); 4406 fromP = &the_ins.opcode[0]; 4407 for (m = the_ins.numo; m; --m) 4408 { 4409 md_number_to_chars (toP, (long) (*fromP), 2); 4410 toP += 2; 4411 fromP++; 4412 } 4413 /* Put out symbol-dependent info. */ 4414 for (m = 0; m < the_ins.nrel; m++) 4415 { 4416 switch (the_ins.reloc[m].wid) 4417 { 4418 case 'B': 4419 n = 1; 4420 break; 4421 case 'b': 4422 n = 1; 4423 break; 4424 case '3': 4425 n = 1; 4426 break; 4427 case 'w': 4428 case 'W': 4429 n = 2; 4430 break; 4431 case 'l': 4432 n = 4; 4433 break; 4434 default: 4435 as_fatal (_("Don't know how to figure width of %c in md_assemble()"), 4436 the_ins.reloc[m].wid); 4437 } 4438 4439 fixP = fix_new_exp (frag_now, 4440 ((toP - frag_now->fr_literal) 4441 - the_ins.numo * 2 + the_ins.reloc[m].n), 4442 n, 4443 &the_ins.reloc[m].exp, 4444 the_ins.reloc[m].pcrel, 4445 get_reloc_code (n, the_ins.reloc[m].pcrel, 4446 the_ins.reloc[m].pic_reloc)); 4447 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4448 if (the_ins.reloc[m].wid == 'B') 4449 fixP->fx_signed = 1; 4450 } 4451 return; 4452 } 4453 4454 /* There's some frag hacking. */ 4455 { 4456 /* Calculate the max frag size. */ 4457 int wid; 4458 4459 wid = 2 * the_ins.fragb[0].fragoff; 4460 for (n = 1; n < the_ins.nfrag; n++) 4461 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4462 /* frag_var part. */ 4463 wid += FRAG_VAR_SIZE; 4464 /* Make sure the whole insn fits in one chunk, in particular that 4465 the var part is attached, as we access one byte before the 4466 variable frag for byte branches. */ 4467 frag_grow (wid); 4468 } 4469 4470 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) 4471 { 4472 int wid; 4473 4474 if (n == 0) 4475 wid = 2 * the_ins.fragb[n].fragoff; 4476 else 4477 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4478 toP = frag_more (wid); 4479 to_beg_P = toP; 4480 shorts_this_frag = 0; 4481 for (m = wid / 2; m; --m) 4482 { 4483 md_number_to_chars (toP, (long) (*fromP), 2); 4484 toP += 2; 4485 fromP++; 4486 shorts_this_frag++; 4487 } 4488 for (m = 0; m < the_ins.nrel; m++) 4489 { 4490 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) 4491 { 4492 the_ins.reloc[m].n -= 2 * shorts_this_frag; 4493 break; 4494 } 4495 wid = the_ins.reloc[m].wid; 4496 if (wid == 0) 4497 continue; 4498 the_ins.reloc[m].wid = 0; 4499 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4500 4501 fixP = fix_new_exp (frag_now, 4502 ((toP - frag_now->fr_literal) 4503 - the_ins.numo * 2 + the_ins.reloc[m].n), 4504 wid, 4505 &the_ins.reloc[m].exp, 4506 the_ins.reloc[m].pcrel, 4507 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4508 the_ins.reloc[m].pic_reloc)); 4509 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4510 } 4511 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, 4512 (relax_substateT) (the_ins.fragb[n].fragty), 4513 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); 4514 } 4515 gas_assert (the_ins.nfrag >= 1); 4516 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff; 4517 shorts_this_frag = 0; 4518 if (n) 4519 { 4520 toP = frag_more (n * 2); 4521 while (n--) 4522 { 4523 md_number_to_chars (toP, (long) (*fromP), 2); 4524 toP += 2; 4525 fromP++; 4526 shorts_this_frag++; 4527 } 4528 } 4529 for (m = 0; m < the_ins.nrel; m++) 4530 { 4531 int wid; 4532 4533 wid = the_ins.reloc[m].wid; 4534 if (wid == 0) 4535 continue; 4536 the_ins.reloc[m].wid = 0; 4537 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4538 4539 fixP = fix_new_exp (frag_now, 4540 ((the_ins.reloc[m].n + toP - frag_now->fr_literal) 4541 - shorts_this_frag * 2), 4542 wid, 4543 &the_ins.reloc[m].exp, 4544 the_ins.reloc[m].pcrel, 4545 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4546 the_ins.reloc[m].pic_reloc)); 4547 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4548 } 4549 } 4550 4551 /* Comparison function used by qsort to rank the opcode entries by name. */ 4552 4553 static int 4554 m68k_compare_opcode (const void * v1, const void * v2) 4555 { 4556 struct m68k_opcode * op1, * op2; 4557 int ret; 4558 4559 if (v1 == v2) 4560 return 0; 4561 4562 op1 = *(struct m68k_opcode **) v1; 4563 op2 = *(struct m68k_opcode **) v2; 4564 4565 /* Compare the two names. If different, return the comparison. 4566 If the same, return the order they are in the opcode table. */ 4567 ret = strcmp (op1->name, op2->name); 4568 if (ret) 4569 return ret; 4570 if (op1 < op2) 4571 return -1; 4572 return 1; 4573 } 4574 4575 void 4576 md_begin (void) 4577 { 4578 const struct m68k_opcode *ins; 4579 struct m68k_incant *hack, *slak; 4580 const char *retval = 0; /* Empty string, or error msg text. */ 4581 int i; 4582 4583 /* Set up hash tables with 68000 instructions. 4584 similar to what the vax assembler does. */ 4585 /* RMS claims the thing to do is take the m68k-opcode.h table, and make 4586 a copy of it at runtime, adding in the information we want but isn't 4587 there. I think it'd be better to have an awk script hack the table 4588 at compile time. Or even just xstr the table and use it as-is. But 4589 my lord ghod hath spoken, so we do it this way. Excuse the ugly var 4590 names. */ 4591 4592 if (flag_mri) 4593 { 4594 flag_reg_prefix_optional = 1; 4595 m68k_abspcadd = 1; 4596 if (! m68k_rel32_from_cmdline) 4597 m68k_rel32 = 0; 4598 } 4599 4600 /* First sort the opcode table into alphabetical order to seperate 4601 the order that the assembler wants to see the opcodes from the 4602 order that the disassembler wants to see them. */ 4603 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes)); 4604 if (!m68k_sorted_opcodes) 4605 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"), 4606 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes))); 4607 4608 for (i = m68k_numopcodes; i--;) 4609 m68k_sorted_opcodes[i] = m68k_opcodes + i; 4610 4611 qsort (m68k_sorted_opcodes, m68k_numopcodes, 4612 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); 4613 4614 op_hash = hash_new (); 4615 4616 obstack_begin (&robyn, 4000); 4617 for (i = 0; i < m68k_numopcodes; i++) 4618 { 4619 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant)); 4620 do 4621 { 4622 ins = m68k_sorted_opcodes[i]; 4623 4624 /* We must enter all insns into the table, because .arch and 4625 .cpu directives can change things. */ 4626 slak->m_operands = ins->args; 4627 slak->m_arch = ins->arch; 4628 slak->m_opcode = ins->opcode; 4629 4630 /* In most cases we can determine the number of opcode words 4631 by checking the second word of the mask. Unfortunately 4632 some instructions have 2 opcode words, but no fixed bits 4633 in the second word. A leading dot in the operands 4634 string also indicates 2 opcodes. */ 4635 if (*slak->m_operands == '.') 4636 { 4637 slak->m_operands++; 4638 slak->m_codenum = 2; 4639 } 4640 else if (ins->match & 0xffffL) 4641 slak->m_codenum = 2; 4642 else 4643 slak->m_codenum = 1; 4644 slak->m_opnum = strlen (slak->m_operands) / 2; 4645 4646 if (i + 1 != m68k_numopcodes 4647 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) 4648 { 4649 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant)); 4650 i++; 4651 } 4652 else 4653 slak->m_next = 0; 4654 slak = slak->m_next; 4655 } 4656 while (slak); 4657 4658 retval = hash_insert (op_hash, ins->name, (char *) hack); 4659 if (retval) 4660 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); 4661 } 4662 4663 for (i = 0; i < m68k_numaliases; i++) 4664 { 4665 const char *name = m68k_opcode_aliases[i].primary; 4666 const char *alias = m68k_opcode_aliases[i].alias; 4667 void *val = hash_find (op_hash, name); 4668 4669 if (!val) 4670 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4671 retval = hash_insert (op_hash, alias, val); 4672 if (retval) 4673 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); 4674 } 4675 4676 /* In MRI mode, all unsized branches are variable sized. Normally, 4677 they are word sized. */ 4678 if (flag_mri) 4679 { 4680 static struct m68k_opcode_alias mri_aliases[] = 4681 { 4682 { "bhi", "jhi", }, 4683 { "bls", "jls", }, 4684 { "bcc", "jcc", }, 4685 { "bcs", "jcs", }, 4686 { "bne", "jne", }, 4687 { "beq", "jeq", }, 4688 { "bvc", "jvc", }, 4689 { "bvs", "jvs", }, 4690 { "bpl", "jpl", }, 4691 { "bmi", "jmi", }, 4692 { "bge", "jge", }, 4693 { "blt", "jlt", }, 4694 { "bgt", "jgt", }, 4695 { "ble", "jle", }, 4696 { "bra", "jra", }, 4697 { "bsr", "jbsr", }, 4698 }; 4699 4700 for (i = 0; 4701 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); 4702 i++) 4703 { 4704 const char *name = mri_aliases[i].primary; 4705 const char *alias = mri_aliases[i].alias; 4706 void *val = hash_find (op_hash, name); 4707 4708 if (!val) 4709 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4710 retval = hash_jam (op_hash, alias, val); 4711 if (retval) 4712 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); 4713 } 4714 } 4715 4716 for (i = 0; i < (int) sizeof (notend_table); i++) 4717 { 4718 notend_table[i] = 0; 4719 alt_notend_table[i] = 0; 4720 } 4721 4722 notend_table[','] = 1; 4723 notend_table['{'] = 1; 4724 notend_table['}'] = 1; 4725 alt_notend_table['a'] = 1; 4726 alt_notend_table['A'] = 1; 4727 alt_notend_table['d'] = 1; 4728 alt_notend_table['D'] = 1; 4729 alt_notend_table['#'] = 1; 4730 alt_notend_table['&'] = 1; 4731 alt_notend_table['f'] = 1; 4732 alt_notend_table['F'] = 1; 4733 #ifdef REGISTER_PREFIX 4734 alt_notend_table[REGISTER_PREFIX] = 1; 4735 #endif 4736 4737 /* We need to put '(' in alt_notend_table to handle 4738 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ 4739 alt_notend_table['('] = 1; 4740 4741 /* We need to put '@' in alt_notend_table to handle 4742 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ 4743 alt_notend_table['@'] = 1; 4744 4745 /* We need to put digits in alt_notend_table to handle 4746 bfextu %d0{24:1},%d0 */ 4747 alt_notend_table['0'] = 1; 4748 alt_notend_table['1'] = 1; 4749 alt_notend_table['2'] = 1; 4750 alt_notend_table['3'] = 1; 4751 alt_notend_table['4'] = 1; 4752 alt_notend_table['5'] = 1; 4753 alt_notend_table['6'] = 1; 4754 alt_notend_table['7'] = 1; 4755 alt_notend_table['8'] = 1; 4756 alt_notend_table['9'] = 1; 4757 4758 #ifndef MIT_SYNTAX_ONLY 4759 /* Insert pseudo ops, these have to go into the opcode table since 4760 gas expects pseudo ops to start with a dot. */ 4761 { 4762 int n = 0; 4763 4764 while (mote_pseudo_table[n].poc_name) 4765 { 4766 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant)); 4767 hash_insert (op_hash, 4768 mote_pseudo_table[n].poc_name, (char *) hack); 4769 hack->m_operands = 0; 4770 hack->m_opnum = n; 4771 n++; 4772 } 4773 } 4774 #endif 4775 4776 init_regtable (); 4777 4778 #ifdef OBJ_ELF 4779 record_alignment (text_section, 2); 4780 record_alignment (data_section, 2); 4781 record_alignment (bss_section, 2); 4782 #endif 4783 } 4784 4785 4786 /* This is called when a label is defined. */ 4788 4789 void 4790 m68k_frob_label (symbolS *sym) 4791 { 4792 struct label_line *n; 4793 4794 n = (struct label_line *) xmalloc (sizeof *n); 4795 n->next = labels; 4796 n->label = sym; 4797 as_where (&n->file, &n->line); 4798 n->text = 0; 4799 labels = n; 4800 current_label = n; 4801 4802 #ifdef OBJ_ELF 4803 dwarf2_emit_label (sym); 4804 #endif 4805 } 4806 4807 /* This is called when a value that is not an instruction is emitted. */ 4808 4809 void 4810 m68k_flush_pending_output (void) 4811 { 4812 current_label = NULL; 4813 } 4814 4815 /* This is called at the end of the assembly, when the final value of 4816 the label is known. We warn if this is a text symbol aligned at an 4817 odd location. */ 4818 4819 void 4820 m68k_frob_symbol (symbolS *sym) 4821 { 4822 if (S_GET_SEGMENT (sym) == reg_section 4823 && (int) S_GET_VALUE (sym) < 0) 4824 { 4825 S_SET_SEGMENT (sym, absolute_section); 4826 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); 4827 } 4828 else if ((S_GET_VALUE (sym) & 1) != 0) 4829 { 4830 struct label_line *l; 4831 4832 for (l = labels; l != NULL; l = l->next) 4833 { 4834 if (l->label == sym) 4835 { 4836 if (l->text) 4837 as_warn_where (l->file, l->line, 4838 _("text label `%s' aligned to odd boundary"), 4839 S_GET_NAME (sym)); 4840 break; 4841 } 4842 } 4843 } 4844 } 4845 4846 /* This is called if we go in or out of MRI mode because of the .mri 4848 pseudo-op. */ 4849 4850 void 4851 m68k_mri_mode_change (int on) 4852 { 4853 if (on) 4854 { 4855 if (! flag_reg_prefix_optional) 4856 { 4857 flag_reg_prefix_optional = 1; 4858 #ifdef REGISTER_PREFIX 4859 init_regtable (); 4860 #endif 4861 } 4862 m68k_abspcadd = 1; 4863 if (! m68k_rel32_from_cmdline) 4864 m68k_rel32 = 0; 4865 } 4866 else 4867 { 4868 if (! reg_prefix_optional_seen) 4869 { 4870 #ifdef REGISTER_PREFIX_OPTIONAL 4871 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 4872 #else 4873 flag_reg_prefix_optional = 0; 4874 #endif 4875 #ifdef REGISTER_PREFIX 4876 init_regtable (); 4877 #endif 4878 } 4879 m68k_abspcadd = 0; 4880 if (! m68k_rel32_from_cmdline) 4881 m68k_rel32 = 1; 4882 } 4883 } 4884 4885 char * 4886 md_atof (int type, char *litP, int *sizeP) 4887 { 4888 return ieee_md_atof (type, litP, sizeP, TRUE); 4889 } 4890 4891 void 4892 md_number_to_chars (char *buf, valueT val, int n) 4893 { 4894 number_to_chars_bigendian (buf, val, n); 4895 } 4896 4897 void 4898 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 4899 { 4900 offsetT val = *valP; 4901 addressT upper_limit; 4902 offsetT lower_limit; 4903 4904 /* This is unnecessary but it convinces the native rs6000 compiler 4905 to generate the code we want. */ 4906 char *buf = fixP->fx_frag->fr_literal; 4907 buf += fixP->fx_where; 4908 /* End ibm compiler workaround. */ 4909 4910 val = SEXT (val); 4911 4912 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 4913 fixP->fx_done = 1; 4914 4915 #ifdef OBJ_ELF 4916 if (fixP->fx_addsy) 4917 { 4918 memset (buf, 0, fixP->fx_size); 4919 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4920 4921 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4922 && !S_IS_DEFINED (fixP->fx_addsy) 4923 && !S_IS_WEAK (fixP->fx_addsy)) 4924 S_SET_WEAK (fixP->fx_addsy); 4925 4926 switch (fixP->fx_r_type) 4927 { 4928 case BFD_RELOC_68K_TLS_GD32: 4929 case BFD_RELOC_68K_TLS_GD16: 4930 case BFD_RELOC_68K_TLS_GD8: 4931 case BFD_RELOC_68K_TLS_LDM32: 4932 case BFD_RELOC_68K_TLS_LDM16: 4933 case BFD_RELOC_68K_TLS_LDM8: 4934 case BFD_RELOC_68K_TLS_LDO32: 4935 case BFD_RELOC_68K_TLS_LDO16: 4936 case BFD_RELOC_68K_TLS_LDO8: 4937 case BFD_RELOC_68K_TLS_IE32: 4938 case BFD_RELOC_68K_TLS_IE16: 4939 case BFD_RELOC_68K_TLS_IE8: 4940 case BFD_RELOC_68K_TLS_LE32: 4941 case BFD_RELOC_68K_TLS_LE16: 4942 case BFD_RELOC_68K_TLS_LE8: 4943 S_SET_THREAD_LOCAL (fixP->fx_addsy); 4944 break; 4945 4946 default: 4947 break; 4948 } 4949 4950 return; 4951 } 4952 #elif defined(OBJ_AOUT) 4953 /* PR gas/3041 Do not fix frags referencing a weak symbol. */ 4954 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)) 4955 { 4956 memset (buf, 0, fixP->fx_size); 4957 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4958 return; 4959 } 4960 #endif 4961 4962 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4963 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4964 return; 4965 4966 switch (fixP->fx_size) 4967 { 4968 /* The cast to offsetT below are necessary to make code 4969 correct for machines where ints are smaller than offsetT. */ 4970 case 1: 4971 *buf++ = val; 4972 upper_limit = 0x7f; 4973 lower_limit = - (offsetT) 0x80; 4974 break; 4975 case 2: 4976 *buf++ = (val >> 8); 4977 *buf++ = val; 4978 upper_limit = 0x7fff; 4979 lower_limit = - (offsetT) 0x8000; 4980 break; 4981 case 4: 4982 *buf++ = (val >> 24); 4983 *buf++ = (val >> 16); 4984 *buf++ = (val >> 8); 4985 *buf++ = val; 4986 upper_limit = 0x7fffffff; 4987 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ 4988 break; 4989 default: 4990 BAD_CASE (fixP->fx_size); 4991 } 4992 4993 /* Fix up a negative reloc. */ 4994 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) 4995 { 4996 fixP->fx_addsy = fixP->fx_subsy; 4997 fixP->fx_subsy = NULL; 4998 fixP->fx_tcbit = 1; 4999 } 5000 5001 /* For non-pc-relative values, it's conceivable we might get something 5002 like "0xff" for a byte field. So extend the upper part of the range 5003 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", 5004 so that we can do any range checking at all. */ 5005 if (! fixP->fx_pcrel && ! fixP->fx_signed) 5006 upper_limit = upper_limit * 2 + 1; 5007 5008 if ((addressT) val > upper_limit 5009 && (val > 0 || val < lower_limit)) 5010 as_bad_where (fixP->fx_file, fixP->fx_line, 5011 _("value %ld out of range"), (long)val); 5012 5013 /* A one byte PC-relative reloc means a short branch. We can't use 5014 a short branch with a value of 0 or -1, because those indicate 5015 different opcodes (branches with longer offsets). fixup_segment 5016 in write.c may have clobbered fx_pcrel, so we need to examine the 5017 reloc type. */ 5018 if ((fixP->fx_pcrel 5019 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 5020 && fixP->fx_size == 1 5021 && (fixP->fx_addsy == NULL 5022 || S_IS_DEFINED (fixP->fx_addsy)) 5023 && (val == 0 || val == -1)) 5024 as_bad_where (fixP->fx_file, fixP->fx_line, 5025 _("invalid byte branch offset")); 5026 } 5027 5028 /* *fragP has been relaxed to its final size, and now needs to have 5029 the bytes inside it modified to conform to the new size There is UGLY 5030 MAGIC here. .. 5031 */ 5032 static void 5033 md_convert_frag_1 (fragS *fragP) 5034 { 5035 long disp; 5036 fixS *fixP = NULL; 5037 5038 /* Address in object code of the displacement. */ 5039 int object_address = fragP->fr_fix + fragP->fr_address; 5040 5041 /* Address in gas core of the place to store the displacement. */ 5042 /* This convinces the native rs6000 compiler to generate the code we 5043 want. */ 5044 char *buffer_address = fragP->fr_literal; 5045 buffer_address += fragP->fr_fix; 5046 /* End ibm compiler workaround. */ 5047 5048 /* The displacement of the address, from current location. */ 5049 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; 5050 disp = (disp + fragP->fr_offset) - object_address; 5051 5052 switch (fragP->fr_subtype) 5053 { 5054 case TAB (BRANCHBWL, BYTE): 5055 case TAB (BRABSJUNC, BYTE): 5056 case TAB (BRABSJCOND, BYTE): 5057 case TAB (BRANCHBW, BYTE): 5058 case TAB (BRANCHBWPL, BYTE): 5059 know (issbyte (disp)); 5060 if (disp == 0) 5061 as_bad_where (fragP->fr_file, fragP->fr_line, 5062 _("short branch with zero offset: use :w")); 5063 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5064 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5065 fixP->fx_pcrel_adjust = -1; 5066 break; 5067 case TAB (BRANCHBWL, SHORT): 5068 case TAB (BRABSJUNC, SHORT): 5069 case TAB (BRABSJCOND, SHORT): 5070 case TAB (BRANCHBW, SHORT): 5071 case TAB (BRANCHBWPL, SHORT): 5072 fragP->fr_opcode[1] = 0x00; 5073 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5074 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5075 fragP->fr_fix += 2; 5076 break; 5077 case TAB (BRANCHBWL, LONG): 5078 fragP->fr_opcode[1] = (char) 0xFF; 5079 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5080 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5081 fragP->fr_fix += 4; 5082 break; 5083 case TAB (BRANCHBWPL, LONG): 5084 /* Here we are converting an unconditional branch into a pair of 5085 conditional branches, in order to get the range. */ 5086 fragP->fr_opcode[0] = 0x66; /* bne */ 5087 fragP->fr_opcode[1] = 0xFF; 5088 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5089 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5090 fixP->fx_file = fragP->fr_file; 5091 fixP->fx_line = fragP->fr_line; 5092 fragP->fr_fix += 4; /* Skip first offset */ 5093 buffer_address += 4; 5094 *buffer_address++ = 0x67; /* beq */ 5095 *buffer_address++ = 0xff; 5096 fragP->fr_fix += 2; /* Skip second branch opcode */ 5097 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5098 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5099 fragP->fr_fix += 4; 5100 break; 5101 case TAB (BRABSJUNC, LONG): 5102 if (fragP->fr_opcode[0] == 0x61) /* jbsr */ 5103 { 5104 if (flag_keep_pcrel) 5105 as_bad_where (fragP->fr_file, fragP->fr_line, 5106 _("Conversion of PC relative BSR to absolute JSR")); 5107 fragP->fr_opcode[0] = 0x4E; 5108 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ 5109 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5110 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5111 fragP->fr_fix += 4; 5112 } 5113 else if (fragP->fr_opcode[0] == 0x60) /* jbra */ 5114 { 5115 if (flag_keep_pcrel) 5116 as_bad_where (fragP->fr_file, fragP->fr_line, 5117 _("Conversion of PC relative branch to absolute jump")); 5118 fragP->fr_opcode[0] = 0x4E; 5119 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ 5120 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5121 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5122 fragP->fr_fix += 4; 5123 } 5124 else 5125 { 5126 /* This cannot happen, because jbsr and jbra are the only two 5127 unconditional branches. */ 5128 abort (); 5129 } 5130 break; 5131 case TAB (BRABSJCOND, LONG): 5132 if (flag_keep_pcrel) 5133 as_bad_where (fragP->fr_file, fragP->fr_line, 5134 _("Conversion of PC relative conditional branch to absolute jump")); 5135 5136 /* Only Bcc 68000 instructions can come here 5137 Change bcc into b!cc/jmp absl long. */ 5138 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ 5139 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ 5140 5141 /* JF: these used to be fr_opcode[2,3], but they may be in a 5142 different frag, in which case referring to them is a no-no. 5143 Only fr_opcode[0,1] are guaranteed to work. */ 5144 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ 5145 *buffer_address++ = (char) 0xf9; 5146 fragP->fr_fix += 2; /* Account for jmp instruction. */ 5147 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5148 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5149 fragP->fr_fix += 4; 5150 break; 5151 case TAB (FBRANCH, SHORT): 5152 know ((fragP->fr_opcode[1] & 0x40) == 0); 5153 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5154 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5155 fragP->fr_fix += 2; 5156 break; 5157 case TAB (FBRANCH, LONG): 5158 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ 5159 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5160 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5161 fragP->fr_fix += 4; 5162 break; 5163 case TAB (DBCCLBR, SHORT): 5164 case TAB (DBCCABSJ, SHORT): 5165 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5166 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5167 fragP->fr_fix += 2; 5168 break; 5169 case TAB (DBCCLBR, LONG): 5170 /* Only DBcc instructions can come here. 5171 Change dbcc into dbcc/bral. 5172 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5173 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5174 *buffer_address++ = 0x04; 5175 *buffer_address++ = 0x60; /* Put in bra pc+6. */ 5176 *buffer_address++ = 0x06; 5177 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ 5178 *buffer_address++ = (char) 0xff; 5179 5180 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5181 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5182 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5183 fragP->fr_fix += 4; 5184 break; 5185 case TAB (DBCCABSJ, LONG): 5186 /* Only DBcc instructions can come here. 5187 Change dbcc into dbcc/jmp. 5188 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5189 if (flag_keep_pcrel) 5190 as_bad_where (fragP->fr_file, fragP->fr_line, 5191 _("Conversion of PC relative conditional branch to absolute jump")); 5192 5193 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5194 *buffer_address++ = 0x04; 5195 *buffer_address++ = 0x60; /* Put in bra pc + 6. */ 5196 *buffer_address++ = 0x06; 5197 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ 5198 *buffer_address++ = (char) 0xf9; 5199 5200 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5201 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5202 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5203 fragP->fr_fix += 4; 5204 break; 5205 case TAB (PCREL1632, SHORT): 5206 fragP->fr_opcode[1] &= ~0x3F; 5207 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ 5208 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5209 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5210 fragP->fr_fix += 2; 5211 break; 5212 case TAB (PCREL1632, LONG): 5213 /* Already set to mode 7.3; this indicates: PC indirect with 5214 suppressed index, 32-bit displacement. */ 5215 *buffer_address++ = 0x01; 5216 *buffer_address++ = 0x70; 5217 fragP->fr_fix += 2; 5218 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5219 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5220 fixP->fx_pcrel_adjust = 2; 5221 fragP->fr_fix += 4; 5222 break; 5223 case TAB (PCINDEX, BYTE): 5224 gas_assert (fragP->fr_fix >= 2); 5225 buffer_address[-2] &= ~1; 5226 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5227 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5228 fixP->fx_pcrel_adjust = 1; 5229 break; 5230 case TAB (PCINDEX, SHORT): 5231 gas_assert (fragP->fr_fix >= 2); 5232 buffer_address[-2] |= 0x1; 5233 buffer_address[-1] = 0x20; 5234 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5235 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5236 fixP->fx_pcrel_adjust = 2; 5237 fragP->fr_fix += 2; 5238 break; 5239 case TAB (PCINDEX, LONG): 5240 gas_assert (fragP->fr_fix >= 2); 5241 buffer_address[-2] |= 0x1; 5242 buffer_address[-1] = 0x30; 5243 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5244 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5245 fixP->fx_pcrel_adjust = 2; 5246 fragP->fr_fix += 4; 5247 break; 5248 case TAB (ABSTOPCREL, SHORT): 5249 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5250 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5251 fragP->fr_fix += 2; 5252 break; 5253 case TAB (ABSTOPCREL, LONG): 5254 if (flag_keep_pcrel) 5255 as_bad_where (fragP->fr_file, fragP->fr_line, 5256 _("Conversion of PC relative displacement to absolute")); 5257 /* The thing to do here is force it to ABSOLUTE LONG, since 5258 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ 5259 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) 5260 abort (); 5261 fragP->fr_opcode[1] &= ~0x3F; 5262 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 5263 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5264 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5265 fragP->fr_fix += 4; 5266 break; 5267 } 5268 if (fixP) 5269 { 5270 fixP->fx_file = fragP->fr_file; 5271 fixP->fx_line = fragP->fr_line; 5272 } 5273 } 5274 5275 void 5276 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 5277 segT sec ATTRIBUTE_UNUSED, 5278 fragS *fragP) 5279 { 5280 md_convert_frag_1 (fragP); 5281 } 5282 5283 /* Force truly undefined symbols to their maximum size, and generally set up 5284 the frag list to be relaxed 5285 */ 5286 int 5287 md_estimate_size_before_relax (fragS *fragP, segT segment) 5288 { 5289 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ 5290 switch (fragP->fr_subtype) 5291 { 5292 case TAB (BRANCHBWL, SZ_UNDEF): 5293 case TAB (BRANCHBWPL, SZ_UNDEF): 5294 case TAB (BRABSJUNC, SZ_UNDEF): 5295 case TAB (BRABSJCOND, SZ_UNDEF): 5296 { 5297 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5298 && relaxable_symbol (fragP->fr_symbol)) 5299 { 5300 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5301 } 5302 else if (flag_short_refs) 5303 { 5304 /* Symbol is undefined and we want short ref. */ 5305 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5306 } 5307 else 5308 { 5309 /* Symbol is still undefined. Make it LONG. */ 5310 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5311 } 5312 break; 5313 } 5314 5315 case TAB (BRANCHBW, SZ_UNDEF): 5316 { 5317 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5318 && relaxable_symbol (fragP->fr_symbol)) 5319 { 5320 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5321 } 5322 else 5323 { 5324 /* Symbol is undefined and we don't have long branches. */ 5325 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5326 } 5327 break; 5328 } 5329 5330 case TAB (FBRANCH, SZ_UNDEF): 5331 case TAB (DBCCLBR, SZ_UNDEF): 5332 case TAB (DBCCABSJ, SZ_UNDEF): 5333 case TAB (PCREL1632, SZ_UNDEF): 5334 { 5335 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5336 && relaxable_symbol (fragP->fr_symbol)) 5337 || flag_short_refs) 5338 { 5339 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5340 } 5341 else 5342 { 5343 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5344 } 5345 break; 5346 } 5347 5348 case TAB (PCINDEX, SZ_UNDEF): 5349 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5350 && relaxable_symbol (fragP->fr_symbol))) 5351 { 5352 fragP->fr_subtype = TAB (PCINDEX, BYTE); 5353 } 5354 else 5355 { 5356 fragP->fr_subtype = TAB (PCINDEX, LONG); 5357 } 5358 break; 5359 5360 case TAB (ABSTOPCREL, SZ_UNDEF): 5361 { 5362 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5363 && relaxable_symbol (fragP->fr_symbol))) 5364 { 5365 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); 5366 } 5367 else 5368 { 5369 fragP->fr_subtype = TAB (ABSTOPCREL, LONG); 5370 } 5371 break; 5372 } 5373 5374 default: 5375 break; 5376 } 5377 5378 /* Now that SZ_UNDEF are taken care of, check others. */ 5379 switch (fragP->fr_subtype) 5380 { 5381 case TAB (BRANCHBWL, BYTE): 5382 case TAB (BRABSJUNC, BYTE): 5383 case TAB (BRABSJCOND, BYTE): 5384 case TAB (BRANCHBW, BYTE): 5385 /* We can't do a short jump to the next instruction, so in that 5386 case we force word mode. If the symbol is at the start of a 5387 frag, and it is the next frag with any data in it (usually 5388 this is just the next frag, but assembler listings may 5389 introduce empty frags), we must use word mode. */ 5390 if (fragP->fr_symbol) 5391 { 5392 fragS *sym_frag; 5393 5394 sym_frag = symbol_get_frag (fragP->fr_symbol); 5395 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) 5396 { 5397 fragS *l; 5398 5399 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) 5400 if (l->fr_fix != 0) 5401 break; 5402 if (l == sym_frag) 5403 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5404 } 5405 } 5406 break; 5407 default: 5408 break; 5409 } 5410 return md_relax_table[fragP->fr_subtype].rlx_length; 5411 } 5412 5413 #if defined(OBJ_AOUT) | defined(OBJ_BOUT) 5414 /* the bit-field entries in the relocation_info struct plays hell 5415 with the byte-order problems of cross-assembly. So as a hack, 5416 I added this mach. dependent ri twiddler. Ugly, but it gets 5417 you there. -KWK */ 5418 /* on m68k: first 4 bytes are normal unsigned long, next three bytes 5419 are symbolnum, most sig. byte first. Last byte is broken up with 5420 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower 5421 nibble as nuthin. (on Sun 3 at least) */ 5422 /* Translate the internal relocation information into target-specific 5423 format. */ 5424 #ifdef comment 5425 void 5426 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) 5427 { 5428 /* This is easy. */ 5429 md_number_to_chars (the_bytes, ri->r_address, 4); 5430 /* Now the fun stuff. */ 5431 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; 5432 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; 5433 the_bytes[6] = ri->r_symbolnum & 0x0ff; 5434 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) 5435 | ((ri->r_length << 5) & 0x60) 5436 | ((ri->r_extern << 4) & 0x10)); 5437 } 5438 5439 #endif 5440 5441 #endif /* OBJ_AOUT or OBJ_BOUT */ 5442 5443 #ifndef WORKING_DOT_WORD 5444 int md_short_jump_size = 4; 5445 int md_long_jump_size = 6; 5446 5447 void 5448 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, 5449 fragS *frag ATTRIBUTE_UNUSED, 5450 symbolS *to_symbol ATTRIBUTE_UNUSED) 5451 { 5452 valueT offset; 5453 5454 offset = to_addr - (from_addr + 2); 5455 5456 md_number_to_chars (ptr, (valueT) 0x6000, 2); 5457 md_number_to_chars (ptr + 2, (valueT) offset, 2); 5458 } 5459 5460 void 5461 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, 5462 fragS *frag, symbolS *to_symbol) 5463 { 5464 valueT offset; 5465 5466 if (!HAVE_LONG_BRANCH (current_architecture)) 5467 { 5468 if (flag_keep_pcrel) 5469 as_fatal (_("Tried to convert PC relative branch to absolute jump")); 5470 offset = to_addr - S_GET_VALUE (to_symbol); 5471 md_number_to_chars (ptr, (valueT) 0x4EF9, 2); 5472 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5473 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, 5474 0, NO_RELOC); 5475 } 5476 else 5477 { 5478 offset = to_addr - (from_addr + 2); 5479 md_number_to_chars (ptr, (valueT) 0x60ff, 2); 5480 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5481 } 5482 } 5483 5484 #endif 5485 5486 /* Different values of OK tell what its OK to return. Things that 5487 aren't OK are an error (what a shock, no?) 5488 5489 0: Everything is OK 5490 10: Absolute 1:8 only 5491 20: Absolute 0:7 only 5492 30: absolute 0:15 only 5493 40: Absolute 0:31 only 5494 50: absolute 0:127 only 5495 55: absolute -64:63 only 5496 60: absolute -128:127 only 5497 65: absolute 0:511 only 5498 70: absolute 0:4095 only 5499 80: absolute -1, 1:7 only 5500 90: No bignums. */ 5501 5502 static int 5503 get_num (struct m68k_exp *exp, int ok) 5504 { 5505 if (exp->exp.X_op == O_absent) 5506 { 5507 /* Do the same thing the VAX asm does. */ 5508 op (exp) = O_constant; 5509 adds (exp) = 0; 5510 subs (exp) = 0; 5511 offs (exp) = 0; 5512 if (ok == 10) 5513 { 5514 as_warn (_("expression out of range: defaulting to 1")); 5515 offs (exp) = 1; 5516 } 5517 } 5518 else if (exp->exp.X_op == O_constant) 5519 { 5520 switch (ok) 5521 { 5522 case 10: 5523 if ((valueT) TRUNC (offs (exp)) - 1 > 7) 5524 { 5525 as_warn (_("expression out of range: defaulting to 1")); 5526 offs (exp) = 1; 5527 } 5528 break; 5529 case 20: 5530 if ((valueT) TRUNC (offs (exp)) > 7) 5531 goto outrange; 5532 break; 5533 case 30: 5534 if ((valueT) TRUNC (offs (exp)) > 15) 5535 goto outrange; 5536 break; 5537 case 40: 5538 if ((valueT) TRUNC (offs (exp)) > 32) 5539 goto outrange; 5540 break; 5541 case 50: 5542 if ((valueT) TRUNC (offs (exp)) > 127) 5543 goto outrange; 5544 break; 5545 case 55: 5546 if ((valueT) SEXT (offs (exp)) + 64 > 127) 5547 goto outrange; 5548 break; 5549 case 60: 5550 if ((valueT) SEXT (offs (exp)) + 128 > 255) 5551 goto outrange; 5552 break; 5553 case 65: 5554 if ((valueT) TRUNC (offs (exp)) > 511) 5555 goto outrange; 5556 break; 5557 case 70: 5558 if ((valueT) TRUNC (offs (exp)) > 4095) 5559 { 5560 outrange: 5561 as_warn (_("expression out of range: defaulting to 0")); 5562 offs (exp) = 0; 5563 } 5564 break; 5565 case 80: 5566 if ((valueT) TRUNC (offs (exp)) != 0xffffffff 5567 && (valueT) TRUNC (offs (exp)) - 1 > 6) 5568 { 5569 as_warn (_("expression out of range: defaulting to 1")); 5570 offs (exp) = 1; 5571 } 5572 break; 5573 default: 5574 break; 5575 } 5576 } 5577 else if (exp->exp.X_op == O_big) 5578 { 5579 if (offs (exp) <= 0 /* flonum. */ 5580 && (ok == 90 /* no bignums */ 5581 || (ok > 10 /* Small-int ranges including 0 ok. */ 5582 /* If we have a flonum zero, a zero integer should 5583 do as well (e.g., in moveq). */ 5584 && generic_floating_point_number.exponent == 0 5585 && generic_floating_point_number.low[0] == 0))) 5586 { 5587 /* HACK! Turn it into a long. */ 5588 LITTLENUM_TYPE words[6]; 5589 5590 gen_to_words (words, 2, 8L); /* These numbers are magic! */ 5591 op (exp) = O_constant; 5592 adds (exp) = 0; 5593 subs (exp) = 0; 5594 offs (exp) = words[1] | (words[0] << 16); 5595 } 5596 else if (ok != 0) 5597 { 5598 op (exp) = O_constant; 5599 adds (exp) = 0; 5600 subs (exp) = 0; 5601 offs (exp) = (ok == 10) ? 1 : 0; 5602 as_warn (_("Can't deal with expression; defaulting to %ld"), 5603 (long) offs (exp)); 5604 } 5605 } 5606 else 5607 { 5608 if (ok >= 10 && ok <= 80) 5609 { 5610 op (exp) = O_constant; 5611 adds (exp) = 0; 5612 subs (exp) = 0; 5613 offs (exp) = (ok == 10) ? 1 : 0; 5614 as_warn (_("Can't deal with expression; defaulting to %ld"), 5615 (long) offs (exp)); 5616 } 5617 } 5618 5619 if (exp->size != SIZE_UNSPEC) 5620 { 5621 switch (exp->size) 5622 { 5623 case SIZE_UNSPEC: 5624 case SIZE_LONG: 5625 break; 5626 case SIZE_BYTE: 5627 if (!isbyte (offs (exp))) 5628 as_warn (_("expression doesn't fit in BYTE")); 5629 break; 5630 case SIZE_WORD: 5631 if (!isword (offs (exp))) 5632 as_warn (_("expression doesn't fit in WORD")); 5633 break; 5634 } 5635 } 5636 5637 return offs (exp); 5638 } 5639 5640 /* These are the back-ends for the various machine dependent pseudo-ops. */ 5641 5642 static void 5643 s_data1 (int ignore ATTRIBUTE_UNUSED) 5644 { 5645 subseg_set (data_section, 1); 5646 demand_empty_rest_of_line (); 5647 } 5648 5649 static void 5650 s_data2 (int ignore ATTRIBUTE_UNUSED) 5651 { 5652 subseg_set (data_section, 2); 5653 demand_empty_rest_of_line (); 5654 } 5655 5656 static void 5657 s_bss (int ignore ATTRIBUTE_UNUSED) 5658 { 5659 /* We don't support putting frags in the BSS segment, we fake it 5660 by marking in_bss, then looking at s_skip for clues. */ 5661 5662 subseg_set (bss_section, 0); 5663 demand_empty_rest_of_line (); 5664 } 5665 5666 static void 5667 s_even (int ignore ATTRIBUTE_UNUSED) 5668 { 5669 int temp; 5670 long temp_fill; 5671 5672 temp = 1; /* JF should be 2? */ 5673 temp_fill = get_absolute_expression (); 5674 if (!need_pass_2) /* Never make frag if expect extra pass. */ 5675 frag_align (temp, (int) temp_fill, 0); 5676 demand_empty_rest_of_line (); 5677 record_alignment (now_seg, temp); 5678 } 5679 5680 static void 5681 s_proc (int ignore ATTRIBUTE_UNUSED) 5682 { 5683 demand_empty_rest_of_line (); 5684 } 5685 5686 /* Pseudo-ops handled for MRI compatibility. */ 5688 5689 /* This function returns non-zero if the argument is a conditional 5690 pseudo-op. This is called when checking whether a pending 5691 alignment is needed. */ 5692 5693 int 5694 m68k_conditional_pseudoop (pseudo_typeS *pop) 5695 { 5696 return (pop->poc_handler == s_mri_if 5697 || pop->poc_handler == s_mri_else); 5698 } 5699 5700 /* Handle an MRI style chip specification. */ 5701 5702 static void 5703 mri_chip (void) 5704 { 5705 char *s; 5706 char c; 5707 int i; 5708 5709 s = input_line_pointer; 5710 /* We can't use get_symbol_end since the processor names are not proper 5711 symbols. */ 5712 while (is_part_of_name (c = *input_line_pointer++)) 5713 ; 5714 *--input_line_pointer = 0; 5715 for (i = 0; m68k_cpus[i].name; i++) 5716 if (strcasecmp (s, m68k_cpus[i].name) == 0) 5717 break; 5718 if (!m68k_cpus[i].name) 5719 { 5720 as_bad (_("%s: unrecognized processor name"), s); 5721 *input_line_pointer = c; 5722 ignore_rest_of_line (); 5723 return; 5724 } 5725 *input_line_pointer = c; 5726 5727 if (*input_line_pointer == '/') 5728 current_architecture = 0; 5729 else 5730 current_architecture &= m68881 | m68851; 5731 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); 5732 control_regs = m68k_cpus[i].control_regs; 5733 5734 while (*input_line_pointer == '/') 5735 { 5736 ++input_line_pointer; 5737 s = input_line_pointer; 5738 /* We can't use get_symbol_end since the processor names are not 5739 proper symbols. */ 5740 while (is_part_of_name (c = *input_line_pointer++)) 5741 ; 5742 *--input_line_pointer = 0; 5743 if (strcmp (s, "68881") == 0) 5744 current_architecture |= m68881; 5745 else if (strcmp (s, "68851") == 0) 5746 current_architecture |= m68851; 5747 *input_line_pointer = c; 5748 } 5749 } 5750 5751 /* The MRI CHIP pseudo-op. */ 5752 5753 static void 5754 s_chip (int ignore ATTRIBUTE_UNUSED) 5755 { 5756 char *stop = NULL; 5757 char stopc; 5758 5759 if (flag_mri) 5760 stop = mri_comment_field (&stopc); 5761 mri_chip (); 5762 if (flag_mri) 5763 mri_comment_end (stop, stopc); 5764 demand_empty_rest_of_line (); 5765 } 5766 5767 /* The MRI FOPT pseudo-op. */ 5768 5769 static void 5770 s_fopt (int ignore ATTRIBUTE_UNUSED) 5771 { 5772 SKIP_WHITESPACE (); 5773 5774 if (strncasecmp (input_line_pointer, "ID=", 3) == 0) 5775 { 5776 int temp; 5777 5778 input_line_pointer += 3; 5779 temp = get_absolute_expression (); 5780 if (temp < 0 || temp > 7) 5781 as_bad (_("bad coprocessor id")); 5782 else 5783 m68k_float_copnum = COP0 + temp; 5784 } 5785 else 5786 { 5787 as_bad (_("unrecognized fopt option")); 5788 ignore_rest_of_line (); 5789 return; 5790 } 5791 5792 demand_empty_rest_of_line (); 5793 } 5794 5795 /* The structure used to handle the MRI OPT pseudo-op. */ 5796 5797 struct opt_action 5798 { 5799 /* The name of the option. */ 5800 const char *name; 5801 5802 /* If this is not NULL, just call this function. The first argument 5803 is the ARG field of this structure, the second argument is 5804 whether the option was negated. */ 5805 void (*pfn) (int arg, int on); 5806 5807 /* If this is not NULL, and the PFN field is NULL, set the variable 5808 this points to. Set it to the ARG field if the option was not 5809 negated, and the NOTARG field otherwise. */ 5810 int *pvar; 5811 5812 /* The value to pass to PFN or to assign to *PVAR. */ 5813 int arg; 5814 5815 /* The value to assign to *PVAR if the option is negated. If PFN is 5816 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then 5817 the option may not be negated. */ 5818 int notarg; 5819 }; 5820 5821 /* The table used to handle the MRI OPT pseudo-op. */ 5822 5823 static void skip_to_comma (int, int); 5824 static void opt_nest (int, int); 5825 static void opt_chip (int, int); 5826 static void opt_list (int, int); 5827 static void opt_list_symbols (int, int); 5828 5829 static const struct opt_action opt_table[] = 5830 { 5831 { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, 5832 5833 /* We do relaxing, so there is little use for these options. */ 5834 { "b", 0, 0, 0, 0 }, 5835 { "brs", 0, 0, 0, 0 }, 5836 { "brb", 0, 0, 0, 0 }, 5837 { "brl", 0, 0, 0, 0 }, 5838 { "brw", 0, 0, 0, 0 }, 5839 5840 { "c", 0, 0, 0, 0 }, 5841 { "cex", 0, 0, 0, 0 }, 5842 { "case", 0, &symbols_case_sensitive, 1, 0 }, 5843 { "cl", 0, 0, 0, 0 }, 5844 { "cre", 0, 0, 0, 0 }, 5845 { "d", 0, &flag_keep_locals, 1, 0 }, 5846 { "e", 0, 0, 0, 0 }, 5847 { "f", 0, &flag_short_refs, 1, 0 }, 5848 { "frs", 0, &flag_short_refs, 1, 0 }, 5849 { "frl", 0, &flag_short_refs, 0, 1 }, 5850 { "g", 0, 0, 0, 0 }, 5851 { "i", 0, 0, 0, 0 }, 5852 { "m", 0, 0, 0, 0 }, 5853 { "mex", 0, 0, 0, 0 }, 5854 { "mc", 0, 0, 0, 0 }, 5855 { "md", 0, 0, 0, 0 }, 5856 { "nest", opt_nest, 0, 0, 0 }, 5857 { "next", skip_to_comma, 0, 0, 0 }, 5858 { "o", 0, 0, 0, 0 }, 5859 { "old", 0, 0, 0, 0 }, 5860 { "op", skip_to_comma, 0, 0, 0 }, 5861 { "pco", 0, 0, 0, 0 }, 5862 { "p", opt_chip, 0, 0, 0 }, 5863 { "pcr", 0, 0, 0, 0 }, 5864 { "pcs", 0, 0, 0, 0 }, 5865 { "r", 0, 0, 0, 0 }, 5866 { "quick", 0, &m68k_quick, 1, 0 }, 5867 { "rel32", 0, &m68k_rel32, 1, 0 }, 5868 { "s", opt_list, 0, 0, 0 }, 5869 { "t", opt_list_symbols, 0, 0, 0 }, 5870 { "w", 0, &flag_no_warnings, 0, 1 }, 5871 { "x", 0, 0, 0, 0 } 5872 }; 5873 5874 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) 5875 5876 /* The MRI OPT pseudo-op. */ 5877 5878 static void 5879 s_opt (int ignore ATTRIBUTE_UNUSED) 5880 { 5881 do 5882 { 5883 int t; 5884 char *s; 5885 char c; 5886 int i; 5887 const struct opt_action *o; 5888 5889 SKIP_WHITESPACE (); 5890 5891 t = 1; 5892 if (*input_line_pointer == '-') 5893 { 5894 ++input_line_pointer; 5895 t = 0; 5896 } 5897 else if (strncasecmp (input_line_pointer, "NO", 2) == 0) 5898 { 5899 input_line_pointer += 2; 5900 t = 0; 5901 } 5902 5903 s = input_line_pointer; 5904 c = get_symbol_end (); 5905 5906 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) 5907 { 5908 if (strcasecmp (s, o->name) == 0) 5909 { 5910 if (o->pfn) 5911 { 5912 /* Restore input_line_pointer now in case the option 5913 takes arguments. */ 5914 *input_line_pointer = c; 5915 (*o->pfn) (o->arg, t); 5916 } 5917 else if (o->pvar != NULL) 5918 { 5919 if (! t && o->arg == o->notarg) 5920 as_bad (_("option `%s' may not be negated"), s); 5921 *input_line_pointer = c; 5922 *o->pvar = t ? o->arg : o->notarg; 5923 } 5924 else 5925 *input_line_pointer = c; 5926 break; 5927 } 5928 } 5929 if (i >= OPTCOUNT) 5930 { 5931 as_bad (_("option `%s' not recognized"), s); 5932 *input_line_pointer = c; 5933 } 5934 } 5935 while (*input_line_pointer++ == ','); 5936 5937 /* Move back to terminating character. */ 5938 --input_line_pointer; 5939 demand_empty_rest_of_line (); 5940 } 5941 5942 /* Skip ahead to a comma. This is used for OPT options which we do 5943 not support and which take arguments. */ 5944 5945 static void 5946 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5947 { 5948 while (*input_line_pointer != ',' 5949 && ! is_end_of_line[(unsigned char) *input_line_pointer]) 5950 ++input_line_pointer; 5951 } 5952 5953 /* Handle the OPT NEST=depth option. */ 5954 5955 static void 5956 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5957 { 5958 if (*input_line_pointer != '=') 5959 { 5960 as_bad (_("bad format of OPT NEST=depth")); 5961 return; 5962 } 5963 5964 ++input_line_pointer; 5965 max_macro_nest = get_absolute_expression (); 5966 } 5967 5968 /* Handle the OPT P=chip option. */ 5969 5970 static void 5971 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5972 { 5973 if (*input_line_pointer != '=') 5974 { 5975 /* This is just OPT P, which we do not support. */ 5976 return; 5977 } 5978 5979 ++input_line_pointer; 5980 mri_chip (); 5981 } 5982 5983 /* Handle the OPT S option. */ 5984 5985 static void 5986 opt_list (int arg ATTRIBUTE_UNUSED, int on) 5987 { 5988 listing_list (on); 5989 } 5990 5991 /* Handle the OPT T option. */ 5992 5993 static void 5994 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) 5995 { 5996 if (on) 5997 listing |= LISTING_SYMBOLS; 5998 else 5999 listing &= ~LISTING_SYMBOLS; 6000 } 6001 6002 /* Handle the MRI REG pseudo-op. */ 6003 6004 static void 6005 s_reg (int ignore ATTRIBUTE_UNUSED) 6006 { 6007 char *s; 6008 int c; 6009 struct m68k_op rop; 6010 int mask; 6011 char *stop = NULL; 6012 char stopc; 6013 6014 if (line_label == NULL) 6015 { 6016 as_bad (_("missing label")); 6017 ignore_rest_of_line (); 6018 return; 6019 } 6020 6021 if (flag_mri) 6022 stop = mri_comment_field (&stopc); 6023 6024 SKIP_WHITESPACE (); 6025 6026 s = input_line_pointer; 6027 while (ISALNUM (*input_line_pointer) 6028 #ifdef REGISTER_PREFIX 6029 || *input_line_pointer == REGISTER_PREFIX 6030 #endif 6031 || *input_line_pointer == '/' 6032 || *input_line_pointer == '-') 6033 ++input_line_pointer; 6034 c = *input_line_pointer; 6035 *input_line_pointer = '\0'; 6036 6037 if (m68k_ip_op (s, &rop) != 0) 6038 { 6039 if (rop.error == NULL) 6040 as_bad (_("bad register list")); 6041 else 6042 as_bad (_("bad register list: %s"), rop.error); 6043 *input_line_pointer = c; 6044 ignore_rest_of_line (); 6045 return; 6046 } 6047 6048 *input_line_pointer = c; 6049 6050 if (rop.mode == REGLST) 6051 mask = rop.mask; 6052 else if (rop.mode == DREG) 6053 mask = 1 << (rop.reg - DATA0); 6054 else if (rop.mode == AREG) 6055 mask = 1 << (rop.reg - ADDR0 + 8); 6056 else if (rop.mode == FPREG) 6057 mask = 1 << (rop.reg - FP0 + 16); 6058 else if (rop.mode == CONTROL 6059 && rop.reg == FPI) 6060 mask = 1 << 24; 6061 else if (rop.mode == CONTROL 6062 && rop.reg == FPS) 6063 mask = 1 << 25; 6064 else if (rop.mode == CONTROL 6065 && rop.reg == FPC) 6066 mask = 1 << 26; 6067 else 6068 { 6069 as_bad (_("bad register list")); 6070 ignore_rest_of_line (); 6071 return; 6072 } 6073 6074 S_SET_SEGMENT (line_label, reg_section); 6075 S_SET_VALUE (line_label, ~mask); 6076 symbol_set_frag (line_label, &zero_address_frag); 6077 6078 if (flag_mri) 6079 mri_comment_end (stop, stopc); 6080 6081 demand_empty_rest_of_line (); 6082 } 6083 6084 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ 6085 6086 struct save_opts 6087 { 6088 struct save_opts *next; 6089 int abspcadd; 6090 int symbols_case_sensitive; 6091 int keep_locals; 6092 int short_refs; 6093 int architecture; 6094 const enum m68k_register *control_regs; 6095 int quick; 6096 int rel32; 6097 int listing; 6098 int no_warnings; 6099 /* FIXME: We don't save OPT S. */ 6100 }; 6101 6102 /* This variable holds the stack of saved options. */ 6103 6104 static struct save_opts *save_stack; 6105 6106 /* The MRI SAVE pseudo-op. */ 6107 6108 static void 6109 s_save (int ignore ATTRIBUTE_UNUSED) 6110 { 6111 struct save_opts *s; 6112 6113 s = (struct save_opts *) xmalloc (sizeof (struct save_opts)); 6114 s->abspcadd = m68k_abspcadd; 6115 s->symbols_case_sensitive = symbols_case_sensitive; 6116 s->keep_locals = flag_keep_locals; 6117 s->short_refs = flag_short_refs; 6118 s->architecture = current_architecture; 6119 s->control_regs = control_regs; 6120 s->quick = m68k_quick; 6121 s->rel32 = m68k_rel32; 6122 s->listing = listing; 6123 s->no_warnings = flag_no_warnings; 6124 6125 s->next = save_stack; 6126 save_stack = s; 6127 6128 demand_empty_rest_of_line (); 6129 } 6130 6131 /* The MRI RESTORE pseudo-op. */ 6132 6133 static void 6134 s_restore (int ignore ATTRIBUTE_UNUSED) 6135 { 6136 struct save_opts *s; 6137 6138 if (save_stack == NULL) 6139 { 6140 as_bad (_("restore without save")); 6141 ignore_rest_of_line (); 6142 return; 6143 } 6144 6145 s = save_stack; 6146 save_stack = s->next; 6147 6148 m68k_abspcadd = s->abspcadd; 6149 symbols_case_sensitive = s->symbols_case_sensitive; 6150 flag_keep_locals = s->keep_locals; 6151 flag_short_refs = s->short_refs; 6152 current_architecture = s->architecture; 6153 control_regs = s->control_regs; 6154 m68k_quick = s->quick; 6155 m68k_rel32 = s->rel32; 6156 listing = s->listing; 6157 flag_no_warnings = s->no_warnings; 6158 6159 free (s); 6160 6161 demand_empty_rest_of_line (); 6162 } 6163 6164 /* Types of MRI structured control directives. */ 6165 6166 enum mri_control_type 6167 { 6168 mri_for, 6169 mri_if, 6170 mri_repeat, 6171 mri_while 6172 }; 6173 6174 /* This structure is used to stack the MRI structured control 6175 directives. */ 6176 6177 struct mri_control_info 6178 { 6179 /* The directive within which this one is enclosed. */ 6180 struct mri_control_info *outer; 6181 6182 /* The type of directive. */ 6183 enum mri_control_type type; 6184 6185 /* Whether an ELSE has been in an IF. */ 6186 int else_seen; 6187 6188 /* The add or sub statement at the end of a FOR. */ 6189 char *incr; 6190 6191 /* The label of the top of a FOR or REPEAT loop. */ 6192 char *top; 6193 6194 /* The label to jump to for the next iteration, or the else 6195 expression of a conditional. */ 6196 char *next; 6197 6198 /* The label to jump to to break out of the loop, or the label past 6199 the end of a conditional. */ 6200 char *bottom; 6201 }; 6202 6203 /* The stack of MRI structured control directives. */ 6204 6205 static struct mri_control_info *mri_control_stack; 6206 6207 /* The current MRI structured control directive index number, used to 6208 generate label names. */ 6209 6210 static int mri_control_index; 6211 6212 /* Assemble an instruction for an MRI structured control directive. */ 6213 6214 static void 6215 mri_assemble (char *str) 6216 { 6217 char *s; 6218 6219 /* md_assemble expects the opcode to be in lower case. */ 6220 for (s = str; *s != ' ' && *s != '\0'; s++) 6221 *s = TOLOWER (*s); 6222 6223 md_assemble (str); 6224 } 6225 6226 /* Generate a new MRI label structured control directive label name. */ 6227 6228 static char * 6229 mri_control_label (void) 6230 { 6231 char *n; 6232 6233 n = (char *) xmalloc (20); 6234 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); 6235 ++mri_control_index; 6236 return n; 6237 } 6238 6239 /* Create a new MRI structured control directive. */ 6240 6241 static struct mri_control_info * 6242 push_mri_control (enum mri_control_type type) 6243 { 6244 struct mri_control_info *n; 6245 6246 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info)); 6247 6248 n->type = type; 6249 n->else_seen = 0; 6250 if (type == mri_if || type == mri_while) 6251 n->top = NULL; 6252 else 6253 n->top = mri_control_label (); 6254 n->next = mri_control_label (); 6255 n->bottom = mri_control_label (); 6256 6257 n->outer = mri_control_stack; 6258 mri_control_stack = n; 6259 6260 return n; 6261 } 6262 6263 /* Pop off the stack of MRI structured control directives. */ 6264 6265 static void 6266 pop_mri_control (void) 6267 { 6268 struct mri_control_info *n; 6269 6270 n = mri_control_stack; 6271 mri_control_stack = n->outer; 6272 if (n->top != NULL) 6273 free (n->top); 6274 free (n->next); 6275 free (n->bottom); 6276 free (n); 6277 } 6278 6279 /* Recognize a condition code in an MRI structured control expression. */ 6280 6281 static int 6282 parse_mri_condition (int *pcc) 6283 { 6284 char c1, c2; 6285 6286 know (*input_line_pointer == '<'); 6287 6288 ++input_line_pointer; 6289 c1 = *input_line_pointer++; 6290 c2 = *input_line_pointer++; 6291 6292 if (*input_line_pointer != '>') 6293 { 6294 as_bad (_("syntax error in structured control directive")); 6295 return 0; 6296 } 6297 6298 ++input_line_pointer; 6299 SKIP_WHITESPACE (); 6300 6301 c1 = TOLOWER (c1); 6302 c2 = TOLOWER (c2); 6303 6304 *pcc = (c1 << 8) | c2; 6305 6306 return 1; 6307 } 6308 6309 /* Parse a single operand in an MRI structured control expression. */ 6310 6311 static int 6312 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, 6313 char **rightstart, char **rightstop) 6314 { 6315 char *s; 6316 6317 SKIP_WHITESPACE (); 6318 6319 *pcc = -1; 6320 *leftstart = NULL; 6321 *leftstop = NULL; 6322 *rightstart = NULL; 6323 *rightstop = NULL; 6324 6325 if (*input_line_pointer == '<') 6326 { 6327 /* It's just a condition code. */ 6328 return parse_mri_condition (pcc); 6329 } 6330 6331 /* Look ahead for the condition code. */ 6332 for (s = input_line_pointer; *s != '\0'; ++s) 6333 { 6334 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') 6335 break; 6336 } 6337 if (*s == '\0') 6338 { 6339 as_bad (_("missing condition code in structured control directive")); 6340 return 0; 6341 } 6342 6343 *leftstart = input_line_pointer; 6344 *leftstop = s; 6345 if (*leftstop > *leftstart 6346 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) 6347 --*leftstop; 6348 6349 input_line_pointer = s; 6350 if (! parse_mri_condition (pcc)) 6351 return 0; 6352 6353 /* Look ahead for AND or OR or end of line. */ 6354 for (s = input_line_pointer; *s != '\0'; ++s) 6355 { 6356 /* We must make sure we don't misinterpret AND/OR at the end of labels! 6357 if d0 <eq> #FOOAND and d1 <ne> #BAROR then 6358 ^^^ ^^ */ 6359 if ((s == input_line_pointer 6360 || *(s-1) == ' ' 6361 || *(s-1) == '\t') 6362 && ((strncasecmp (s, "AND", 3) == 0 6363 && (s[3] == '.' || ! is_part_of_name (s[3]))) 6364 || (strncasecmp (s, "OR", 2) == 0 6365 && (s[2] == '.' || ! is_part_of_name (s[2]))))) 6366 break; 6367 } 6368 6369 *rightstart = input_line_pointer; 6370 *rightstop = s; 6371 if (*rightstop > *rightstart 6372 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) 6373 --*rightstop; 6374 6375 input_line_pointer = s; 6376 6377 return 1; 6378 } 6379 6380 #define MCC(b1, b2) (((b1) << 8) | (b2)) 6381 6382 /* Swap the sense of a condition. This changes the condition so that 6383 it generates the same result when the operands are swapped. */ 6384 6385 static int 6386 swap_mri_condition (int cc) 6387 { 6388 switch (cc) 6389 { 6390 case MCC ('h', 'i'): return MCC ('c', 's'); 6391 case MCC ('l', 's'): return MCC ('c', 'c'); 6392 /* <HS> is an alias for <CC>. */ 6393 case MCC ('h', 's'): 6394 case MCC ('c', 'c'): return MCC ('l', 's'); 6395 /* <LO> is an alias for <CS>. */ 6396 case MCC ('l', 'o'): 6397 case MCC ('c', 's'): return MCC ('h', 'i'); 6398 case MCC ('p', 'l'): return MCC ('m', 'i'); 6399 case MCC ('m', 'i'): return MCC ('p', 'l'); 6400 case MCC ('g', 'e'): return MCC ('l', 'e'); 6401 case MCC ('l', 't'): return MCC ('g', 't'); 6402 case MCC ('g', 't'): return MCC ('l', 't'); 6403 case MCC ('l', 'e'): return MCC ('g', 'e'); 6404 /* Issue a warning for conditions we can not swap. */ 6405 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ 6406 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ 6407 case MCC ('v', 'c'): 6408 case MCC ('v', 's'): 6409 default : 6410 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), 6411 (char) (cc >> 8), (char) (cc)); 6412 break; 6413 } 6414 return cc; 6415 } 6416 6417 /* Reverse the sense of a condition. */ 6418 6419 static int 6420 reverse_mri_condition (int cc) 6421 { 6422 switch (cc) 6423 { 6424 case MCC ('h', 'i'): return MCC ('l', 's'); 6425 case MCC ('l', 's'): return MCC ('h', 'i'); 6426 /* <HS> is an alias for <CC> */ 6427 case MCC ('h', 's'): return MCC ('l', 'o'); 6428 case MCC ('c', 'c'): return MCC ('c', 's'); 6429 /* <LO> is an alias for <CS> */ 6430 case MCC ('l', 'o'): return MCC ('h', 's'); 6431 case MCC ('c', 's'): return MCC ('c', 'c'); 6432 case MCC ('n', 'e'): return MCC ('e', 'q'); 6433 case MCC ('e', 'q'): return MCC ('n', 'e'); 6434 case MCC ('v', 'c'): return MCC ('v', 's'); 6435 case MCC ('v', 's'): return MCC ('v', 'c'); 6436 case MCC ('p', 'l'): return MCC ('m', 'i'); 6437 case MCC ('m', 'i'): return MCC ('p', 'l'); 6438 case MCC ('g', 'e'): return MCC ('l', 't'); 6439 case MCC ('l', 't'): return MCC ('g', 'e'); 6440 case MCC ('g', 't'): return MCC ('l', 'e'); 6441 case MCC ('l', 'e'): return MCC ('g', 't'); 6442 } 6443 return cc; 6444 } 6445 6446 /* Build an MRI structured control expression. This generates test 6447 and branch instructions. It goes to TRUELAB if the condition is 6448 true, and to FALSELAB if the condition is false. Exactly one of 6449 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL 6450 is the size qualifier for the expression. EXTENT is the size to 6451 use for the branch. */ 6452 6453 static void 6454 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, 6455 char *rightstart, char *rightstop, 6456 const char *truelab, const char *falselab, 6457 int extent) 6458 { 6459 char *buf; 6460 char *s; 6461 6462 if (leftstart != NULL) 6463 { 6464 struct m68k_op leftop, rightop; 6465 char c; 6466 6467 /* Swap the compare operands, if necessary, to produce a legal 6468 m68k compare instruction. Comparing a register operand with 6469 a non-register operand requires the register to be on the 6470 right (cmp, cmpa). Comparing an immediate value with 6471 anything requires the immediate value to be on the left 6472 (cmpi). */ 6473 6474 c = *leftstop; 6475 *leftstop = '\0'; 6476 (void) m68k_ip_op (leftstart, &leftop); 6477 *leftstop = c; 6478 6479 c = *rightstop; 6480 *rightstop = '\0'; 6481 (void) m68k_ip_op (rightstart, &rightop); 6482 *rightstop = c; 6483 6484 if (rightop.mode == IMMED 6485 || ((leftop.mode == DREG || leftop.mode == AREG) 6486 && (rightop.mode != DREG && rightop.mode != AREG))) 6487 { 6488 char *temp; 6489 6490 /* Correct conditional handling: 6491 if #1 <lt> d0 then ;means if (1 < d0) 6492 ... 6493 endi 6494 6495 should assemble to: 6496 6497 cmp #1,d0 if we do *not* swap the operands 6498 bgt true we need the swapped condition! 6499 ble false 6500 true: 6501 ... 6502 false: 6503 */ 6504 temp = leftstart; 6505 leftstart = rightstart; 6506 rightstart = temp; 6507 temp = leftstop; 6508 leftstop = rightstop; 6509 rightstop = temp; 6510 } 6511 else 6512 { 6513 cc = swap_mri_condition (cc); 6514 } 6515 } 6516 6517 if (truelab == NULL) 6518 { 6519 cc = reverse_mri_condition (cc); 6520 truelab = falselab; 6521 } 6522 6523 if (leftstart != NULL) 6524 { 6525 buf = (char *) xmalloc (20 6526 + (leftstop - leftstart) 6527 + (rightstop - rightstart)); 6528 s = buf; 6529 *s++ = 'c'; 6530 *s++ = 'm'; 6531 *s++ = 'p'; 6532 if (qual != '\0') 6533 *s++ = TOLOWER (qual); 6534 *s++ = ' '; 6535 memcpy (s, leftstart, leftstop - leftstart); 6536 s += leftstop - leftstart; 6537 *s++ = ','; 6538 memcpy (s, rightstart, rightstop - rightstart); 6539 s += rightstop - rightstart; 6540 *s = '\0'; 6541 mri_assemble (buf); 6542 free (buf); 6543 } 6544 6545 buf = (char *) xmalloc (20 + strlen (truelab)); 6546 s = buf; 6547 *s++ = 'b'; 6548 *s++ = cc >> 8; 6549 *s++ = cc & 0xff; 6550 if (extent != '\0') 6551 *s++ = TOLOWER (extent); 6552 *s++ = ' '; 6553 strcpy (s, truelab); 6554 mri_assemble (buf); 6555 free (buf); 6556 } 6557 6558 /* Parse an MRI structured control expression. This generates test 6559 and branch instructions. STOP is where the expression ends. It 6560 goes to TRUELAB if the condition is true, and to FALSELAB if the 6561 condition is false. Exactly one of TRUELAB and FALSELAB will be 6562 NULL, meaning to fall through. QUAL is the size qualifier for the 6563 expression. EXTENT is the size to use for the branch. */ 6564 6565 static void 6566 parse_mri_control_expression (char *stop, int qual, const char *truelab, 6567 const char *falselab, int extent) 6568 { 6569 int c; 6570 int cc; 6571 char *leftstart; 6572 char *leftstop; 6573 char *rightstart; 6574 char *rightstop; 6575 6576 c = *stop; 6577 *stop = '\0'; 6578 6579 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6580 &rightstart, &rightstop)) 6581 { 6582 *stop = c; 6583 return; 6584 } 6585 6586 if (strncasecmp (input_line_pointer, "AND", 3) == 0) 6587 { 6588 const char *flab; 6589 6590 if (falselab != NULL) 6591 flab = falselab; 6592 else 6593 flab = mri_control_label (); 6594 6595 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6596 rightstop, (const char *) NULL, flab, extent); 6597 6598 input_line_pointer += 3; 6599 if (*input_line_pointer != '.' 6600 || input_line_pointer[1] == '\0') 6601 qual = '\0'; 6602 else 6603 { 6604 qual = input_line_pointer[1]; 6605 input_line_pointer += 2; 6606 } 6607 6608 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6609 &rightstart, &rightstop)) 6610 { 6611 *stop = c; 6612 return; 6613 } 6614 6615 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6616 rightstop, truelab, falselab, extent); 6617 6618 if (falselab == NULL) 6619 colon (flab); 6620 } 6621 else if (strncasecmp (input_line_pointer, "OR", 2) == 0) 6622 { 6623 const char *tlab; 6624 6625 if (truelab != NULL) 6626 tlab = truelab; 6627 else 6628 tlab = mri_control_label (); 6629 6630 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6631 rightstop, tlab, (const char *) NULL, extent); 6632 6633 input_line_pointer += 2; 6634 if (*input_line_pointer != '.' 6635 || input_line_pointer[1] == '\0') 6636 qual = '\0'; 6637 else 6638 { 6639 qual = input_line_pointer[1]; 6640 input_line_pointer += 2; 6641 } 6642 6643 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6644 &rightstart, &rightstop)) 6645 { 6646 *stop = c; 6647 return; 6648 } 6649 6650 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6651 rightstop, truelab, falselab, extent); 6652 6653 if (truelab == NULL) 6654 colon (tlab); 6655 } 6656 else 6657 { 6658 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6659 rightstop, truelab, falselab, extent); 6660 } 6661 6662 *stop = c; 6663 if (input_line_pointer != stop) 6664 as_bad (_("syntax error in structured control directive")); 6665 } 6666 6667 /* Handle the MRI IF pseudo-op. This may be a structured control 6668 directive, or it may be a regular assembler conditional, depending 6669 on its operands. */ 6670 6671 static void 6672 s_mri_if (int qual) 6673 { 6674 char *s; 6675 int c; 6676 struct mri_control_info *n; 6677 6678 /* A structured control directive must end with THEN with an 6679 optional qualifier. */ 6680 s = input_line_pointer; 6681 /* We only accept '*' as introduction of comments if preceded by white space 6682 or at first column of a line (I think this can't actually happen here?) 6683 This is important when assembling: 6684 if d0 <ne> 12(a0,d0*2) then 6685 if d0 <ne> #CONST*20 then. */ 6686 while (! (is_end_of_line[(unsigned char) *s] 6687 || (flag_mri 6688 && *s == '*' 6689 && (s == input_line_pointer 6690 || *(s-1) == ' ' 6691 || *(s-1) == '\t')))) 6692 ++s; 6693 --s; 6694 while (s > input_line_pointer && (*s == ' ' || *s == '\t')) 6695 --s; 6696 6697 if (s - input_line_pointer > 1 6698 && s[-1] == '.') 6699 s -= 2; 6700 6701 if (s - input_line_pointer < 3 6702 || strncasecmp (s - 3, "THEN", 4) != 0) 6703 { 6704 if (qual != '\0') 6705 { 6706 as_bad (_("missing then")); 6707 ignore_rest_of_line (); 6708 return; 6709 } 6710 6711 /* It's a conditional. */ 6712 s_if (O_ne); 6713 return; 6714 } 6715 6716 /* Since this might be a conditional if, this pseudo-op will be 6717 called even if we are supported to be ignoring input. Double 6718 check now. Clobber *input_line_pointer so that ignore_input 6719 thinks that this is not a special pseudo-op. */ 6720 c = *input_line_pointer; 6721 *input_line_pointer = 0; 6722 if (ignore_input ()) 6723 { 6724 *input_line_pointer = c; 6725 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6726 ++input_line_pointer; 6727 demand_empty_rest_of_line (); 6728 return; 6729 } 6730 *input_line_pointer = c; 6731 6732 n = push_mri_control (mri_if); 6733 6734 parse_mri_control_expression (s - 3, qual, (const char *) NULL, 6735 n->next, s[1] == '.' ? s[2] : '\0'); 6736 6737 if (s[1] == '.') 6738 input_line_pointer = s + 3; 6739 else 6740 input_line_pointer = s + 1; 6741 6742 if (flag_mri) 6743 { 6744 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6745 ++input_line_pointer; 6746 } 6747 6748 demand_empty_rest_of_line (); 6749 } 6750 6751 /* Handle the MRI else pseudo-op. If we are currently doing an MRI 6752 structured IF, associate the ELSE with the IF. Otherwise, assume 6753 it is a conditional else. */ 6754 6755 static void 6756 s_mri_else (int qual) 6757 { 6758 int c; 6759 char *buf; 6760 char q[2]; 6761 6762 if (qual == '\0' 6763 && (mri_control_stack == NULL 6764 || mri_control_stack->type != mri_if 6765 || mri_control_stack->else_seen)) 6766 { 6767 s_else (0); 6768 return; 6769 } 6770 6771 c = *input_line_pointer; 6772 *input_line_pointer = 0; 6773 if (ignore_input ()) 6774 { 6775 *input_line_pointer = c; 6776 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6777 ++input_line_pointer; 6778 demand_empty_rest_of_line (); 6779 return; 6780 } 6781 *input_line_pointer = c; 6782 6783 if (mri_control_stack == NULL 6784 || mri_control_stack->type != mri_if 6785 || mri_control_stack->else_seen) 6786 { 6787 as_bad (_("else without matching if")); 6788 ignore_rest_of_line (); 6789 return; 6790 } 6791 6792 mri_control_stack->else_seen = 1; 6793 6794 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom)); 6795 q[0] = TOLOWER (qual); 6796 q[1] = '\0'; 6797 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); 6798 mri_assemble (buf); 6799 free (buf); 6800 6801 colon (mri_control_stack->next); 6802 6803 if (flag_mri) 6804 { 6805 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6806 ++input_line_pointer; 6807 } 6808 6809 demand_empty_rest_of_line (); 6810 } 6811 6812 /* Handle the MRI ENDI pseudo-op. */ 6813 6814 static void 6815 s_mri_endi (int ignore ATTRIBUTE_UNUSED) 6816 { 6817 if (mri_control_stack == NULL 6818 || mri_control_stack->type != mri_if) 6819 { 6820 as_bad (_("endi without matching if")); 6821 ignore_rest_of_line (); 6822 return; 6823 } 6824 6825 /* ignore_input will not return true for ENDI, so we don't need to 6826 worry about checking it again here. */ 6827 6828 if (! mri_control_stack->else_seen) 6829 colon (mri_control_stack->next); 6830 colon (mri_control_stack->bottom); 6831 6832 pop_mri_control (); 6833 6834 if (flag_mri) 6835 { 6836 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6837 ++input_line_pointer; 6838 } 6839 6840 demand_empty_rest_of_line (); 6841 } 6842 6843 /* Handle the MRI BREAK pseudo-op. */ 6844 6845 static void 6846 s_mri_break (int extent) 6847 { 6848 struct mri_control_info *n; 6849 char *buf; 6850 char ex[2]; 6851 6852 n = mri_control_stack; 6853 while (n != NULL 6854 && n->type != mri_for 6855 && n->type != mri_repeat 6856 && n->type != mri_while) 6857 n = n->outer; 6858 if (n == NULL) 6859 { 6860 as_bad (_("break outside of structured loop")); 6861 ignore_rest_of_line (); 6862 return; 6863 } 6864 6865 buf = (char *) xmalloc (20 + strlen (n->bottom)); 6866 ex[0] = TOLOWER (extent); 6867 ex[1] = '\0'; 6868 sprintf (buf, "bra%s %s", ex, n->bottom); 6869 mri_assemble (buf); 6870 free (buf); 6871 6872 if (flag_mri) 6873 { 6874 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6875 ++input_line_pointer; 6876 } 6877 6878 demand_empty_rest_of_line (); 6879 } 6880 6881 /* Handle the MRI NEXT pseudo-op. */ 6882 6883 static void 6884 s_mri_next (int extent) 6885 { 6886 struct mri_control_info *n; 6887 char *buf; 6888 char ex[2]; 6889 6890 n = mri_control_stack; 6891 while (n != NULL 6892 && n->type != mri_for 6893 && n->type != mri_repeat 6894 && n->type != mri_while) 6895 n = n->outer; 6896 if (n == NULL) 6897 { 6898 as_bad (_("next outside of structured loop")); 6899 ignore_rest_of_line (); 6900 return; 6901 } 6902 6903 buf = (char *) xmalloc (20 + strlen (n->next)); 6904 ex[0] = TOLOWER (extent); 6905 ex[1] = '\0'; 6906 sprintf (buf, "bra%s %s", ex, n->next); 6907 mri_assemble (buf); 6908 free (buf); 6909 6910 if (flag_mri) 6911 { 6912 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6913 ++input_line_pointer; 6914 } 6915 6916 demand_empty_rest_of_line (); 6917 } 6918 6919 /* Handle the MRI FOR pseudo-op. */ 6920 6921 static void 6922 s_mri_for (int qual) 6923 { 6924 const char *varstart, *varstop; 6925 const char *initstart, *initstop; 6926 const char *endstart, *endstop; 6927 const char *bystart, *bystop; 6928 int up; 6929 int by; 6930 int extent; 6931 struct mri_control_info *n; 6932 char *buf; 6933 char *s; 6934 char ex[2]; 6935 6936 /* The syntax is 6937 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e 6938 */ 6939 6940 SKIP_WHITESPACE (); 6941 varstart = input_line_pointer; 6942 6943 /* Look for the '='. */ 6944 while (! is_end_of_line[(unsigned char) *input_line_pointer] 6945 && *input_line_pointer != '=') 6946 ++input_line_pointer; 6947 if (*input_line_pointer != '=') 6948 { 6949 as_bad (_("missing =")); 6950 ignore_rest_of_line (); 6951 return; 6952 } 6953 6954 varstop = input_line_pointer; 6955 if (varstop > varstart 6956 && (varstop[-1] == ' ' || varstop[-1] == '\t')) 6957 --varstop; 6958 6959 ++input_line_pointer; 6960 6961 initstart = input_line_pointer; 6962 6963 /* Look for TO or DOWNTO. */ 6964 up = 1; 6965 initstop = NULL; 6966 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6967 { 6968 if (strncasecmp (input_line_pointer, "TO", 2) == 0 6969 && ! is_part_of_name (input_line_pointer[2])) 6970 { 6971 initstop = input_line_pointer; 6972 input_line_pointer += 2; 6973 break; 6974 } 6975 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 6976 && ! is_part_of_name (input_line_pointer[6])) 6977 { 6978 initstop = input_line_pointer; 6979 up = 0; 6980 input_line_pointer += 6; 6981 break; 6982 } 6983 ++input_line_pointer; 6984 } 6985 if (initstop == NULL) 6986 { 6987 as_bad (_("missing to or downto")); 6988 ignore_rest_of_line (); 6989 return; 6990 } 6991 if (initstop > initstart 6992 && (initstop[-1] == ' ' || initstop[-1] == '\t')) 6993 --initstop; 6994 6995 SKIP_WHITESPACE (); 6996 endstart = input_line_pointer; 6997 6998 /* Look for BY or DO. */ 6999 by = 0; 7000 endstop = NULL; 7001 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7002 { 7003 if (strncasecmp (input_line_pointer, "BY", 2) == 0 7004 && ! is_part_of_name (input_line_pointer[2])) 7005 { 7006 endstop = input_line_pointer; 7007 by = 1; 7008 input_line_pointer += 2; 7009 break; 7010 } 7011 if (strncasecmp (input_line_pointer, "DO", 2) == 0 7012 && (input_line_pointer[2] == '.' 7013 || ! is_part_of_name (input_line_pointer[2]))) 7014 { 7015 endstop = input_line_pointer; 7016 input_line_pointer += 2; 7017 break; 7018 } 7019 ++input_line_pointer; 7020 } 7021 if (endstop == NULL) 7022 { 7023 as_bad (_("missing do")); 7024 ignore_rest_of_line (); 7025 return; 7026 } 7027 if (endstop > endstart 7028 && (endstop[-1] == ' ' || endstop[-1] == '\t')) 7029 --endstop; 7030 7031 if (! by) 7032 { 7033 bystart = "#1"; 7034 bystop = bystart + 2; 7035 } 7036 else 7037 { 7038 SKIP_WHITESPACE (); 7039 bystart = input_line_pointer; 7040 7041 /* Look for DO. */ 7042 bystop = NULL; 7043 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7044 { 7045 if (strncasecmp (input_line_pointer, "DO", 2) == 0 7046 && (input_line_pointer[2] == '.' 7047 || ! is_part_of_name (input_line_pointer[2]))) 7048 { 7049 bystop = input_line_pointer; 7050 input_line_pointer += 2; 7051 break; 7052 } 7053 ++input_line_pointer; 7054 } 7055 if (bystop == NULL) 7056 { 7057 as_bad (_("missing do")); 7058 ignore_rest_of_line (); 7059 return; 7060 } 7061 if (bystop > bystart 7062 && (bystop[-1] == ' ' || bystop[-1] == '\t')) 7063 --bystop; 7064 } 7065 7066 if (*input_line_pointer != '.') 7067 extent = '\0'; 7068 else 7069 { 7070 extent = input_line_pointer[1]; 7071 input_line_pointer += 2; 7072 } 7073 7074 /* We have fully parsed the FOR operands. Now build the loop. */ 7075 n = push_mri_control (mri_for); 7076 7077 buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); 7078 7079 /* Move init,var. */ 7080 s = buf; 7081 *s++ = 'm'; 7082 *s++ = 'o'; 7083 *s++ = 'v'; 7084 *s++ = 'e'; 7085 if (qual != '\0') 7086 *s++ = TOLOWER (qual); 7087 *s++ = ' '; 7088 memcpy (s, initstart, initstop - initstart); 7089 s += initstop - initstart; 7090 *s++ = ','; 7091 memcpy (s, varstart, varstop - varstart); 7092 s += varstop - varstart; 7093 *s = '\0'; 7094 mri_assemble (buf); 7095 7096 colon (n->top); 7097 7098 /* cmp end,var. */ 7099 s = buf; 7100 *s++ = 'c'; 7101 *s++ = 'm'; 7102 *s++ = 'p'; 7103 if (qual != '\0') 7104 *s++ = TOLOWER (qual); 7105 *s++ = ' '; 7106 memcpy (s, endstart, endstop - endstart); 7107 s += endstop - endstart; 7108 *s++ = ','; 7109 memcpy (s, varstart, varstop - varstart); 7110 s += varstop - varstart; 7111 *s = '\0'; 7112 mri_assemble (buf); 7113 7114 /* bcc bottom. */ 7115 ex[0] = TOLOWER (extent); 7116 ex[1] = '\0'; 7117 if (up) 7118 sprintf (buf, "blt%s %s", ex, n->bottom); 7119 else 7120 sprintf (buf, "bgt%s %s", ex, n->bottom); 7121 mri_assemble (buf); 7122 7123 /* Put together the add or sub instruction used by ENDF. */ 7124 s = buf; 7125 if (up) 7126 strcpy (s, "add"); 7127 else 7128 strcpy (s, "sub"); 7129 s += 3; 7130 if (qual != '\0') 7131 *s++ = TOLOWER (qual); 7132 *s++ = ' '; 7133 memcpy (s, bystart, bystop - bystart); 7134 s += bystop - bystart; 7135 *s++ = ','; 7136 memcpy (s, varstart, varstop - varstart); 7137 s += varstop - varstart; 7138 *s = '\0'; 7139 n->incr = buf; 7140 7141 if (flag_mri) 7142 { 7143 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7144 ++input_line_pointer; 7145 } 7146 7147 demand_empty_rest_of_line (); 7148 } 7149 7150 /* Handle the MRI ENDF pseudo-op. */ 7151 7152 static void 7153 s_mri_endf (int ignore ATTRIBUTE_UNUSED) 7154 { 7155 if (mri_control_stack == NULL 7156 || mri_control_stack->type != mri_for) 7157 { 7158 as_bad (_("endf without for")); 7159 ignore_rest_of_line (); 7160 return; 7161 } 7162 7163 colon (mri_control_stack->next); 7164 7165 mri_assemble (mri_control_stack->incr); 7166 7167 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); 7168 mri_assemble (mri_control_stack->incr); 7169 7170 free (mri_control_stack->incr); 7171 7172 colon (mri_control_stack->bottom); 7173 7174 pop_mri_control (); 7175 7176 if (flag_mri) 7177 { 7178 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7179 ++input_line_pointer; 7180 } 7181 7182 demand_empty_rest_of_line (); 7183 } 7184 7185 /* Handle the MRI REPEAT pseudo-op. */ 7186 7187 static void 7188 s_mri_repeat (int ignore ATTRIBUTE_UNUSED) 7189 { 7190 struct mri_control_info *n; 7191 7192 n = push_mri_control (mri_repeat); 7193 colon (n->top); 7194 if (flag_mri) 7195 { 7196 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7197 ++input_line_pointer; 7198 } 7199 demand_empty_rest_of_line (); 7200 } 7201 7202 /* Handle the MRI UNTIL pseudo-op. */ 7203 7204 static void 7205 s_mri_until (int qual) 7206 { 7207 char *s; 7208 7209 if (mri_control_stack == NULL 7210 || mri_control_stack->type != mri_repeat) 7211 { 7212 as_bad (_("until without repeat")); 7213 ignore_rest_of_line (); 7214 return; 7215 } 7216 7217 colon (mri_control_stack->next); 7218 7219 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) 7220 ; 7221 7222 parse_mri_control_expression (s, qual, (const char *) NULL, 7223 mri_control_stack->top, '\0'); 7224 7225 colon (mri_control_stack->bottom); 7226 7227 input_line_pointer = s; 7228 7229 pop_mri_control (); 7230 7231 if (flag_mri) 7232 { 7233 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7234 ++input_line_pointer; 7235 } 7236 7237 demand_empty_rest_of_line (); 7238 } 7239 7240 /* Handle the MRI WHILE pseudo-op. */ 7241 7242 static void 7243 s_mri_while (int qual) 7244 { 7245 char *s; 7246 7247 struct mri_control_info *n; 7248 7249 s = input_line_pointer; 7250 /* We only accept '*' as introduction of comments if preceded by white space 7251 or at first column of a line (I think this can't actually happen here?) 7252 This is important when assembling: 7253 while d0 <ne> 12(a0,d0*2) do 7254 while d0 <ne> #CONST*20 do. */ 7255 while (! (is_end_of_line[(unsigned char) *s] 7256 || (flag_mri 7257 && *s == '*' 7258 && (s == input_line_pointer 7259 || *(s-1) == ' ' 7260 || *(s-1) == '\t')))) 7261 s++; 7262 --s; 7263 while (*s == ' ' || *s == '\t') 7264 --s; 7265 if (s - input_line_pointer > 1 7266 && s[-1] == '.') 7267 s -= 2; 7268 if (s - input_line_pointer < 2 7269 || strncasecmp (s - 1, "DO", 2) != 0) 7270 { 7271 as_bad (_("missing do")); 7272 ignore_rest_of_line (); 7273 return; 7274 } 7275 7276 n = push_mri_control (mri_while); 7277 7278 colon (n->next); 7279 7280 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, 7281 s[1] == '.' ? s[2] : '\0'); 7282 7283 input_line_pointer = s + 1; 7284 if (*input_line_pointer == '.') 7285 input_line_pointer += 2; 7286 7287 if (flag_mri) 7288 { 7289 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7290 ++input_line_pointer; 7291 } 7292 7293 demand_empty_rest_of_line (); 7294 } 7295 7296 /* Handle the MRI ENDW pseudo-op. */ 7297 7298 static void 7299 s_mri_endw (int ignore ATTRIBUTE_UNUSED) 7300 { 7301 char *buf; 7302 7303 if (mri_control_stack == NULL 7304 || mri_control_stack->type != mri_while) 7305 { 7306 as_bad (_("endw without while")); 7307 ignore_rest_of_line (); 7308 return; 7309 } 7310 7311 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next)); 7312 sprintf (buf, "bra %s", mri_control_stack->next); 7313 mri_assemble (buf); 7314 free (buf); 7315 7316 colon (mri_control_stack->bottom); 7317 7318 pop_mri_control (); 7319 7320 if (flag_mri) 7321 { 7322 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7323 ++input_line_pointer; 7324 } 7325 7326 demand_empty_rest_of_line (); 7327 } 7328 7329 /* Parse a .cpu directive. */ 7331 7332 static void 7333 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) 7334 { 7335 char saved_char; 7336 char *name; 7337 7338 if (initialized) 7339 { 7340 as_bad (_("already assembled instructions")); 7341 ignore_rest_of_line (); 7342 return; 7343 } 7344 7345 name = input_line_pointer; 7346 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 7347 input_line_pointer++; 7348 saved_char = *input_line_pointer; 7349 *input_line_pointer = 0; 7350 7351 m68k_set_cpu (name, 1, 0); 7352 7353 *input_line_pointer = saved_char; 7354 demand_empty_rest_of_line (); 7355 return; 7356 } 7357 7358 /* Parse a .arch directive. */ 7359 7360 static void 7361 s_m68k_arch (int ignored ATTRIBUTE_UNUSED) 7362 { 7363 char saved_char; 7364 char *name; 7365 7366 if (initialized) 7367 { 7368 as_bad (_("already assembled instructions")); 7369 ignore_rest_of_line (); 7370 return; 7371 } 7372 7373 name = input_line_pointer; 7374 while (*input_line_pointer && *input_line_pointer != ',' 7375 && !ISSPACE (*input_line_pointer)) 7376 input_line_pointer++; 7377 saved_char = *input_line_pointer; 7378 *input_line_pointer = 0; 7379 7380 if (m68k_set_arch (name, 1, 0)) 7381 { 7382 /* Scan extensions. */ 7383 do 7384 { 7385 *input_line_pointer++ = saved_char; 7386 if (!*input_line_pointer || ISSPACE (*input_line_pointer)) 7387 break; 7388 name = input_line_pointer; 7389 while (*input_line_pointer && *input_line_pointer != ',' 7390 && !ISSPACE (*input_line_pointer)) 7391 input_line_pointer++; 7392 saved_char = *input_line_pointer; 7393 *input_line_pointer = 0; 7394 } 7395 while (m68k_set_extension (name, 1, 0)); 7396 } 7397 7398 *input_line_pointer = saved_char; 7399 demand_empty_rest_of_line (); 7400 return; 7401 } 7402 7403 /* Lookup a cpu name in TABLE and return the slot found. Return NULL 7405 if none is found, the caller is responsible for emitting an error 7406 message. If ALLOW_M is non-zero, we allow an initial 'm' on the 7407 cpu name, if it begins with a '6' (possibly skipping an intervening 7408 'c'. We also allow a 'c' in the same place. if NEGATED is 7409 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if 7410 the option is indeed negated. */ 7411 7412 static const struct m68k_cpu * 7413 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, 7414 int allow_m, int *negated) 7415 { 7416 /* allow negated value? */ 7417 if (negated) 7418 { 7419 *negated = 0; 7420 7421 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') 7422 { 7423 arg += 3; 7424 *negated = 1; 7425 } 7426 } 7427 7428 /* Remove 'm' or 'mc' prefix from 68k variants. */ 7429 if (allow_m) 7430 { 7431 if (arg[0] == 'm') 7432 { 7433 if (arg[1] == '6') 7434 arg += 1; 7435 else if (arg[1] == 'c' && arg[2] == '6') 7436 arg += 2; 7437 } 7438 } 7439 else if (arg[0] == 'c' && arg[1] == '6') 7440 arg += 1; 7441 7442 for (; table->name; table++) 7443 if (!strcmp (arg, table->name)) 7444 { 7445 if (table->alias < -1 || table->alias > 1) 7446 as_bad (_("`%s' is deprecated, use `%s'"), 7447 table->name, table[table->alias < 0 ? 1 : -1].name); 7448 return table; 7449 } 7450 return 0; 7451 } 7452 7453 /* Set the cpu, issuing errors if it is unrecognized. */ 7454 7455 static int 7456 m68k_set_cpu (char const *name, int allow_m, int silent) 7457 { 7458 const struct m68k_cpu *cpu; 7459 7460 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); 7461 7462 if (!cpu) 7463 { 7464 if (!silent) 7465 as_bad (_("cpu `%s' unrecognized"), name); 7466 return 0; 7467 } 7468 selected_cpu = cpu; 7469 return 1; 7470 } 7471 7472 /* Set the architecture, issuing errors if it is unrecognized. */ 7473 7474 static int 7475 m68k_set_arch (char const *name, int allow_m, int silent) 7476 { 7477 const struct m68k_cpu *arch; 7478 7479 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); 7480 7481 if (!arch) 7482 { 7483 if (!silent) 7484 as_bad (_("architecture `%s' unrecognized"), name); 7485 return 0; 7486 } 7487 selected_arch = arch; 7488 return 1; 7489 } 7490 7491 /* Set the architecture extension, issuing errors if it is 7492 unrecognized, or invalid */ 7493 7494 static int 7495 m68k_set_extension (char const *name, int allow_m, int silent) 7496 { 7497 int negated; 7498 const struct m68k_cpu *ext; 7499 7500 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); 7501 7502 if (!ext) 7503 { 7504 if (!silent) 7505 as_bad (_("extension `%s' unrecognized"), name); 7506 return 0; 7507 } 7508 7509 if (negated) 7510 not_current_architecture |= (ext->control_regs 7511 ? *(unsigned *)ext->control_regs: ext->arch); 7512 else 7513 current_architecture |= ext->arch; 7514 return 1; 7515 } 7516 7517 /* md_parse_option 7518 Invocation line includes a switch not recognized by the base assembler. 7519 */ 7520 7521 #ifdef OBJ_ELF 7522 const char *md_shortopts = "lSA:m:kQ:V"; 7523 #else 7524 const char *md_shortopts = "lSA:m:k"; 7525 #endif 7526 7527 struct option md_longopts[] = { 7528 #define OPTION_PIC (OPTION_MD_BASE) 7529 {"pic", no_argument, NULL, OPTION_PIC}, 7530 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) 7531 {"register-prefix-optional", no_argument, NULL, 7532 OPTION_REGISTER_PREFIX_OPTIONAL}, 7533 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) 7534 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, 7535 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) 7536 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, 7537 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) 7538 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, 7539 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) 7540 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, 7541 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) 7542 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 7543 #define OPTION_PCREL (OPTION_MD_BASE + 7) 7544 {"pcrel", no_argument, NULL, OPTION_PCREL}, 7545 {NULL, no_argument, NULL, 0} 7546 }; 7547 size_t md_longopts_size = sizeof (md_longopts); 7548 7549 int 7550 md_parse_option (int c, char *arg) 7551 { 7552 switch (c) 7553 { 7554 case 'l': /* -l means keep external to 2 bit offset 7555 rather than 16 bit one. */ 7556 flag_short_refs = 1; 7557 break; 7558 7559 case 'S': /* -S means that jbsr's always turn into 7560 jsr's. */ 7561 flag_long_jumps = 1; 7562 break; 7563 7564 case OPTION_PCREL: /* --pcrel means never turn PC-relative 7565 branches into absolute jumps. */ 7566 flag_keep_pcrel = 1; 7567 break; 7568 7569 case OPTION_PIC: 7570 case 'k': 7571 flag_want_pic = 1; 7572 break; /* -pic, Position Independent Code. */ 7573 7574 case OPTION_REGISTER_PREFIX_OPTIONAL: 7575 flag_reg_prefix_optional = 1; 7576 reg_prefix_optional_seen = 1; 7577 break; 7578 7579 /* -V: SVR4 argument to print version ID. */ 7580 case 'V': 7581 print_version_id (); 7582 break; 7583 7584 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 7585 should be emitted or not. FIXME: Not implemented. */ 7586 case 'Q': 7587 break; 7588 7589 case OPTION_BITWISE_OR: 7590 { 7591 char *n, *t; 7592 const char *s; 7593 7594 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1); 7595 t = n; 7596 for (s = m68k_comment_chars; *s != '\0'; s++) 7597 if (*s != '|') 7598 *t++ = *s; 7599 *t = '\0'; 7600 m68k_comment_chars = n; 7601 } 7602 break; 7603 7604 case OPTION_BASE_SIZE_DEFAULT_16: 7605 m68k_index_width_default = SIZE_WORD; 7606 break; 7607 7608 case OPTION_BASE_SIZE_DEFAULT_32: 7609 m68k_index_width_default = SIZE_LONG; 7610 break; 7611 7612 case OPTION_DISP_SIZE_DEFAULT_16: 7613 m68k_rel32 = 0; 7614 m68k_rel32_from_cmdline = 1; 7615 break; 7616 7617 case OPTION_DISP_SIZE_DEFAULT_32: 7618 m68k_rel32 = 1; 7619 m68k_rel32_from_cmdline = 1; 7620 break; 7621 7622 case 'A': 7623 #if WARN_DEPRECATED 7624 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", 7625 arg, arg)); 7626 #endif 7627 /* Intentional fall-through. */ 7628 case 'm': 7629 if (!strncmp (arg, "arch=", 5)) 7630 m68k_set_arch (arg + 5, 1, 0); 7631 else if (!strncmp (arg, "cpu=", 4)) 7632 m68k_set_cpu (arg + 4, 1, 0); 7633 else if (m68k_set_extension (arg, 0, 1)) 7634 ; 7635 else if (m68k_set_arch (arg, 0, 1)) 7636 ; 7637 else if (m68k_set_cpu (arg, 0, 1)) 7638 ; 7639 else 7640 return 0; 7641 break; 7642 7643 default: 7644 return 0; 7645 } 7646 7647 return 1; 7648 } 7649 7650 /* Setup tables from the selected arch and/or cpu */ 7651 7652 static void 7653 m68k_init_arch (void) 7654 { 7655 if (not_current_architecture & current_architecture) 7656 { 7657 as_bad (_("architecture features both enabled and disabled")); 7658 not_current_architecture &= ~current_architecture; 7659 } 7660 if (selected_arch) 7661 { 7662 current_architecture |= selected_arch->arch; 7663 control_regs = selected_arch->control_regs; 7664 } 7665 else 7666 current_architecture |= selected_cpu->arch; 7667 7668 current_architecture &= ~not_current_architecture; 7669 7670 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) 7671 { 7672 /* Determine which float is really meant. */ 7673 if (current_architecture & (m68k_mask & ~m68881)) 7674 current_architecture ^= cfloat; 7675 else 7676 current_architecture ^= m68881; 7677 } 7678 7679 if (selected_cpu) 7680 { 7681 control_regs = selected_cpu->control_regs; 7682 if (current_architecture & ~selected_cpu->arch) 7683 { 7684 as_bad (_("selected processor does not have all features of selected architecture")); 7685 current_architecture 7686 = selected_cpu->arch & ~not_current_architecture; 7687 } 7688 } 7689 7690 if ((current_architecture & m68k_mask) 7691 && (current_architecture & ~m68k_mask)) 7692 { 7693 as_bad (_ ("m68k and cf features both selected")); 7694 if (current_architecture & m68k_mask) 7695 current_architecture &= m68k_mask; 7696 else 7697 current_architecture &= ~m68k_mask; 7698 } 7699 7700 /* Permit m68881 specification with all cpus; those that can't work 7701 with a coprocessor could be doing emulation. */ 7702 if (current_architecture & m68851) 7703 { 7704 if (current_architecture & m68040) 7705 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); 7706 } 7707 /* What other incompatibilities could we check for? */ 7708 7709 if (cpu_of_arch (current_architecture) < m68020 7710 || arch_coldfire_p (current_architecture)) 7711 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; 7712 7713 initialized = 1; 7714 } 7715 7716 void 7717 md_show_usage (FILE *stream) 7718 { 7719 const char *default_cpu = TARGET_CPU; 7720 int i; 7721 7722 /* Get the canonical name for the default target CPU. */ 7723 if (*default_cpu == 'm') 7724 default_cpu++; 7725 for (i = 0; m68k_cpus[i].name; i++) 7726 { 7727 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) 7728 { 7729 while (m68k_cpus[i].alias > 0) 7730 i--; 7731 while (m68k_cpus[i].alias < 0) 7732 i++; 7733 default_cpu = m68k_cpus[i].name; 7734 } 7735 } 7736 7737 fprintf (stream, _("\ 7738 -march=<arch> set architecture\n\ 7739 -mcpu=<cpu> set cpu [default %s]\n\ 7740 "), default_cpu); 7741 for (i = 0; m68k_extensions[i].name; i++) 7742 fprintf (stream, _("\ 7743 -m[no-]%-16s enable/disable%s architecture extension\n\ 7744 "), m68k_extensions[i].name, 7745 m68k_extensions[i].alias > 0 ? " ColdFire" 7746 : m68k_extensions[i].alias < 0 ? " m68k" : ""); 7747 7748 fprintf (stream, _("\ 7749 -l use 1 word for refs to undefined symbols [default 2]\n\ 7750 -pic, -k generate position independent code\n\ 7751 -S turn jbsr into jsr\n\ 7752 --pcrel never turn PC-relative branches into absolute jumps\n\ 7753 --register-prefix-optional\n\ 7754 recognize register names without prefix character\n\ 7755 --bitwise-or do not treat `|' as a comment character\n\ 7756 --base-size-default-16 base reg without size is 16 bits\n\ 7757 --base-size-default-32 base reg without size is 32 bits (default)\n\ 7758 --disp-size-default-16 displacement with unknown size is 16 bits\n\ 7759 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ 7760 ")); 7761 7762 fprintf (stream, _("Architecture variants are: ")); 7763 for (i = 0; m68k_archs[i].name; i++) 7764 { 7765 if (i) 7766 fprintf (stream, " | "); 7767 fprintf (stream, "%s", m68k_archs[i].name); 7768 } 7769 fprintf (stream, "\n"); 7770 7771 fprintf (stream, _("Processor variants are: ")); 7772 for (i = 0; m68k_cpus[i].name; i++) 7773 { 7774 if (i) 7775 fprintf (stream, " | "); 7776 fprintf (stream, "%s", m68k_cpus[i].name); 7777 } 7778 fprintf (stream, _("\n")); 7779 } 7780 7781 #ifdef TEST2 7783 7784 /* TEST2: Test md_assemble() */ 7785 /* Warning, this routine probably doesn't work anymore. */ 7786 int 7787 main (void) 7788 { 7789 struct m68k_it the_ins; 7790 char buf[120]; 7791 char *cp; 7792 int n; 7793 7794 m68k_ip_begin (); 7795 for (;;) 7796 { 7797 if (!gets (buf) || !*buf) 7798 break; 7799 if (buf[0] == '|' || buf[1] == '.') 7800 continue; 7801 for (cp = buf; *cp; cp++) 7802 if (*cp == '\t') 7803 *cp = ' '; 7804 if (is_label (buf)) 7805 continue; 7806 memset (&the_ins, '\0', sizeof (the_ins)); 7807 m68k_ip (&the_ins, buf); 7808 if (the_ins.error) 7809 { 7810 printf (_("Error %s in %s\n"), the_ins.error, buf); 7811 } 7812 else 7813 { 7814 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); 7815 for (n = 0; n < the_ins.numo; n++) 7816 printf (" 0x%x", the_ins.opcode[n] & 0xffff); 7817 printf (" "); 7818 print_the_insn (&the_ins.opcode[0], stdout); 7819 (void) putchar ('\n'); 7820 } 7821 for (n = 0; n < strlen (the_ins.args) / 2; n++) 7822 { 7823 if (the_ins.operands[n].error) 7824 { 7825 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); 7826 continue; 7827 } 7828 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, 7829 the_ins.operands[n].reg); 7830 if (the_ins.operands[n].b_const) 7831 printf ("Constant: '%.*s', ", 7832 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, 7833 the_ins.operands[n].b_const); 7834 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, 7835 the_ins.operands[n].isiz, the_ins.operands[n].imul); 7836 if (the_ins.operands[n].b_iadd) 7837 printf ("Iadd: '%.*s',", 7838 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, 7839 the_ins.operands[n].b_iadd); 7840 putchar ('\n'); 7841 } 7842 } 7843 m68k_ip_end (); 7844 return 0; 7845 } 7846 7847 int 7848 is_label (char *str) 7849 { 7850 while (*str == ' ') 7851 str++; 7852 while (*str && *str != ' ') 7853 str++; 7854 if (str[-1] == ':' || str[1] == '=') 7855 return 1; 7856 return 0; 7857 } 7858 7859 #endif 7860 7861 /* Possible states for relaxation: 7862 7863 0 0 branch offset byte (bra, etc) 7864 0 1 word 7865 0 2 long 7866 7867 1 0 indexed offsets byte a0@(32,d4:w:1) etc 7868 1 1 word 7869 1 2 long 7870 7871 2 0 two-offset index word-word a0@(32,d4)@(45) etc 7872 2 1 word-long 7873 2 2 long-word 7874 2 3 long-long 7875 7876 */ 7877 7878 /* We have no need to default values of symbols. */ 7879 7880 symbolS * 7881 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 7882 { 7883 return 0; 7884 } 7885 7886 /* Round up a section size to the appropriate boundary. */ 7887 valueT 7888 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 7889 { 7890 #ifdef OBJ_AOUT 7891 /* For a.out, force the section size to be aligned. If we don't do 7892 this, BFD will align it for us, but it will not write out the 7893 final bytes of the section. This may be a bug in BFD, but it is 7894 easier to fix it here since that is how the other a.out targets 7895 work. */ 7896 int align; 7897 7898 align = bfd_get_section_alignment (stdoutput, segment); 7899 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 7900 #endif 7901 7902 return size; 7903 } 7904 7905 /* Exactly what point is a PC-relative offset relative TO? 7906 On the 68k, it is relative to the address of the first extension 7907 word. The difference between the addresses of the offset and the 7908 first extension word is stored in fx_pcrel_adjust. */ 7909 long 7910 md_pcrel_from (fixS *fixP) 7911 { 7912 int adjust; 7913 7914 adjust = fixP->fx_pcrel_adjust; 7915 if (adjust == 64) 7916 adjust = -1; 7917 return fixP->fx_where + fixP->fx_frag->fr_address - adjust; 7918 } 7919 7920 #ifdef OBJ_ELF 7921 void 7922 m68k_elf_final_processing (void) 7923 { 7924 unsigned flags = 0; 7925 7926 if (arch_coldfire_fpu (current_architecture)) 7927 flags |= EF_M68K_CFV4E; 7928 /* Set file-specific flags if this is a cpu32 processor. */ 7929 if (cpu_of_arch (current_architecture) & cpu32) 7930 flags |= EF_M68K_CPU32; 7931 else if (cpu_of_arch (current_architecture) & fido_a) 7932 flags |= EF_M68K_FIDO; 7933 else if ((cpu_of_arch (current_architecture) & m68000up) 7934 && !(cpu_of_arch (current_architecture) & m68020up)) 7935 flags |= EF_M68K_M68000; 7936 7937 if (current_architecture & mcfisa_a) 7938 { 7939 static const unsigned isa_features[][2] = 7940 { 7941 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, 7942 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, 7943 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, 7944 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, 7945 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, 7946 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, 7947 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, 7948 {0,0}, 7949 }; 7950 static const unsigned mac_features[][2] = 7951 { 7952 {EF_M68K_CF_MAC, mcfmac}, 7953 {EF_M68K_CF_EMAC, mcfemac}, 7954 {0,0}, 7955 }; 7956 unsigned ix; 7957 unsigned pattern; 7958 7959 pattern = (current_architecture 7960 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); 7961 for (ix = 0; isa_features[ix][1]; ix++) 7962 { 7963 if (pattern == isa_features[ix][1]) 7964 { 7965 flags |= isa_features[ix][0]; 7966 break; 7967 } 7968 } 7969 if (!isa_features[ix][1]) 7970 { 7971 cf_bad: 7972 as_warn (_("Not a defined coldfire architecture")); 7973 } 7974 else 7975 { 7976 if (current_architecture & cfloat) 7977 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; 7978 7979 pattern = current_architecture & (mcfmac|mcfemac); 7980 if (pattern) 7981 { 7982 for (ix = 0; mac_features[ix][1]; ix++) 7983 { 7984 if (pattern == mac_features[ix][1]) 7985 { 7986 flags |= mac_features[ix][0]; 7987 break; 7988 } 7989 } 7990 if (!mac_features[ix][1]) 7991 goto cf_bad; 7992 } 7993 } 7994 } 7995 elf_elfheader (stdoutput)->e_flags |= flags; 7996 } 7997 7998 /* Parse @TLSLDO and return the desired relocation. */ 7999 static bfd_reloc_code_real_type 8000 m68k_elf_suffix (char **str_p, expressionS *exp_p) 8001 { 8002 char ident[20]; 8003 char *str = *str_p; 8004 char *str2; 8005 int ch; 8006 int len; 8007 8008 if (*str++ != '@') 8009 return BFD_RELOC_UNUSED; 8010 8011 for (ch = *str, str2 = ident; 8012 (str2 < ident + sizeof (ident) - 1 8013 && (ISALNUM (ch) || ch == '@')); 8014 ch = *++str) 8015 { 8016 *str2++ = ch; 8017 } 8018 8019 *str2 = '\0'; 8020 len = str2 - ident; 8021 8022 if (strncmp (ident, "TLSLDO", 6) == 0 8023 && len == 6) 8024 { 8025 /* Now check for identifier@suffix+constant. */ 8026 if (*str == '-' || *str == '+') 8027 { 8028 char *orig_line = input_line_pointer; 8029 expressionS new_exp; 8030 8031 input_line_pointer = str; 8032 expression (&new_exp); 8033 if (new_exp.X_op == O_constant) 8034 { 8035 exp_p->X_add_number += new_exp.X_add_number; 8036 str = input_line_pointer; 8037 } 8038 8039 if (&input_line_pointer != str_p) 8040 input_line_pointer = orig_line; 8041 } 8042 *str_p = str; 8043 8044 return BFD_RELOC_68K_TLS_LDO32; 8045 } 8046 8047 return BFD_RELOC_UNUSED; 8048 } 8049 8050 /* Handles .long <tls_symbol>+0x8000 debug info. 8051 Clobbers input_line_pointer, checks end-of-line. 8052 Adapted from tc-ppc.c:ppc_elf_cons. */ 8053 static void 8054 m68k_elf_cons (int nbytes /* 4=.long */) 8055 { 8056 if (is_it_end_of_statement ()) 8057 { 8058 demand_empty_rest_of_line (); 8059 return; 8060 } 8061 8062 do 8063 { 8064 expressionS exp; 8065 bfd_reloc_code_real_type reloc; 8066 8067 expression (&exp); 8068 if (exp.X_op == O_symbol 8069 && *input_line_pointer == '@' 8070 && (reloc = m68k_elf_suffix (&input_line_pointer, 8071 &exp)) != BFD_RELOC_UNUSED) 8072 { 8073 reloc_howto_type *reloc_howto; 8074 int size; 8075 8076 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); 8077 size = bfd_get_reloc_size (reloc_howto); 8078 8079 if (size > nbytes) 8080 { 8081 as_bad (_("%s relocations do not fit in %d bytes\n"), 8082 reloc_howto->name, nbytes); 8083 } 8084 else 8085 { 8086 char *p; 8087 int offset; 8088 8089 p = frag_more (nbytes); 8090 offset = 0; 8091 if (target_big_endian) 8092 offset = nbytes - size; 8093 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, 8094 &exp, 0, reloc); 8095 } 8096 } 8097 else 8098 emit_expr (&exp, (unsigned int) nbytes); 8099 } 8100 while (*input_line_pointer++ == ','); 8101 8102 /* Put terminator back into stream. */ 8103 input_line_pointer--; 8104 demand_empty_rest_of_line (); 8105 } 8106 #endif 8107 8108 int 8109 tc_m68k_regname_to_dw2regnum (char *regname) 8110 { 8111 unsigned int regnum; 8112 static const char *const regnames[] = 8113 { 8114 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 8115 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", 8116 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", 8117 "pc" 8118 }; 8119 8120 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) 8121 if (strcmp (regname, regnames[regnum]) == 0) 8122 return regnum; 8123 8124 return -1; 8125 } 8126 8127 void 8128 tc_m68k_frame_initial_instructions (void) 8129 { 8130 static int sp_regno = -1; 8131 8132 if (sp_regno < 0) 8133 sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); 8134 8135 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); 8136 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); 8137 } 8138 8139 /* Check and emit error if broken-word handling has failed to fix up a 8140 case-table. This is called from write.c, after doing everything it 8141 knows about how to handle broken words. */ 8142 8143 void 8144 tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) 8145 { 8146 if (new_offset > 32767 || new_offset < -32768) 8147 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, 8148 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."), 8149 (long) new_offset); 8150 } 8151 8152
