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      1 /*
      2  * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved.
      3  * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions are met:
      7  *
      8  * Redistributions of source code must retain the above copyright notice, this
      9  * list of conditions and the following disclaimer.
     10  *
     11  * Redistributions in binary form must reproduce the above copyright notice,
     12  * this list of conditions and the following disclaimer in the documentation
     13  * and/or other materials provided with the distribution.
     14  *
     15  * Neither the name of ARM nor the names of its contributors may be used
     16  * to endorse or promote products derived from this software without specific
     17  * prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
     23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef __HI6220_AO_H__
     33 #define __HI6220_AO_H__
     34 
     35 #define AO_CTRL_BASE				0xF7800000
     36 
     37 #define AO_SC_SYS_CTRL0				(AO_CTRL_BASE + 0x000)
     38 #define AO_SC_SYS_CTRL1				(AO_CTRL_BASE + 0x004)
     39 #define AO_SC_SYS_CTRL2				(AO_CTRL_BASE + 0x008)
     40 #define AO_SC_SYS_STAT0				(AO_CTRL_BASE + 0x010)
     41 #define AO_SC_SYS_STAT1				(AO_CTRL_BASE + 0x014)
     42 #define AO_SC_MCU_IMCTRL			(AO_CTRL_BASE + 0x018)
     43 #define AO_SC_MCU_IMSTAT			(AO_CTRL_BASE + 0x01C)
     44 #define AO_SC_SECONDRY_INT_EN0			(AO_CTRL_BASE + 0x044)
     45 #define AO_SC_SECONDRY_INT_STATR0		(AO_CTRL_BASE + 0x048)
     46 #define AO_SC_SECONDRY_INT_STATM0		(AO_CTRL_BASE + 0x04C)
     47 #define AO_SC_MCU_WKUP_INT_EN6			(AO_CTRL_BASE + 0x054)
     48 #define AO_SC_MCU_WKUP_INT_STATR6		(AO_CTRL_BASE + 0x058)
     49 #define AO_SC_MCU_WKUP_INT_STATM6		(AO_CTRL_BASE + 0x05C)
     50 #define AO_SC_MCU_WKUP_INT_EN5			(AO_CTRL_BASE + 0x064)
     51 #define AO_SC_MCU_WKUP_INT_STATR5		(AO_CTRL_BASE + 0x068)
     52 #define AO_SC_MCU_WKUP_INT_STATM5		(AO_CTRL_BASE + 0x06C)
     53 #define AO_SC_MCU_WKUP_INT_EN4			(AO_CTRL_BASE + 0x094)
     54 #define AO_SC_MCU_WKUP_INT_STATR4		(AO_CTRL_BASE + 0x098)
     55 #define AO_SC_MCU_WKUP_INT_STATM4		(AO_CTRL_BASE + 0x09C)
     56 #define AO_SC_MCU_WKUP_INT_EN0			(AO_CTRL_BASE + 0x0A8)
     57 #define AO_SC_MCU_WKUP_INT_STATR0		(AO_CTRL_BASE + 0x0AC)
     58 #define AO_SC_MCU_WKUP_INT_STATM0		(AO_CTRL_BASE + 0x0B0)
     59 #define AO_SC_MCU_WKUP_INT_EN1			(AO_CTRL_BASE + 0x0B4)
     60 #define AO_SC_MCU_WKUP_INT_STATR1		(AO_CTRL_BASE + 0x0B8)
     61 #define AO_SC_MCU_WKUP_INT_STATM1		(AO_CTRL_BASE + 0x0BC)
     62 #define AO_SC_INT_STATR				(AO_CTRL_BASE + 0x0C4)
     63 #define AO_SC_INT_STATM				(AO_CTRL_BASE + 0x0C8)
     64 #define AO_SC_INT_CLEAR				(AO_CTRL_BASE + 0x0CC)
     65 #define AO_SC_INT_EN_SET			(AO_CTRL_BASE + 0x0D0)
     66 #define AO_SC_INT_EN_DIS			(AO_CTRL_BASE + 0x0D4)
     67 #define AO_SC_INT_EN_STAT			(AO_CTRL_BASE + 0x0D8)
     68 #define AO_SC_INT_STATR1			(AO_CTRL_BASE + 0x0E4)
     69 #define AO_SC_INT_STATM1			(AO_CTRL_BASE + 0x0E8)
     70 #define AO_SC_INT_CLEAR1			(AO_CTRL_BASE + 0x0EC)
     71 #define AO_SC_INT_EN_SET1			(AO_CTRL_BASE + 0x0F0)
     72 #define AO_SC_INT_EN_DIS1			(AO_CTRL_BASE + 0x0F4)
     73 #define AO_SC_INT_EN_STAT1			(AO_CTRL_BASE + 0x0F8)
     74 #define AO_SC_TIMER_EN0				(AO_CTRL_BASE + 0x1D0)
     75 #define AO_SC_TIMER_EN1				(AO_CTRL_BASE + 0x1D4)
     76 #define AO_SC_TIMER_EN4				(AO_CTRL_BASE + 0x1F0)
     77 #define AO_SC_TIMER_EN5				(AO_CTRL_BASE + 0x1F4)
     78 #define AO_SC_MCU_SUBSYS_CTRL0			(AO_CTRL_BASE + 0x400)
     79 #define AO_SC_MCU_SUBSYS_CTRL1			(AO_CTRL_BASE + 0x404)
     80 #define AO_SC_MCU_SUBSYS_CTRL2			(AO_CTRL_BASE + 0x408)
     81 #define AO_SC_MCU_SUBSYS_CTRL3			(AO_CTRL_BASE + 0x40C)
     82 #define AO_SC_MCU_SUBSYS_CTRL4			(AO_CTRL_BASE + 0x410)
     83 #define AO_SC_MCU_SUBSYS_CTRL5			(AO_CTRL_BASE + 0x414)
     84 #define AO_SC_MCU_SUBSYS_CTRL6			(AO_CTRL_BASE + 0x418)
     85 #define AO_SC_MCU_SUBSYS_CTRL7			(AO_CTRL_BASE + 0x41C)
     86 #define AO_SC_MCU_SUBSYS_STAT0			(AO_CTRL_BASE + 0x440)
     87 #define AO_SC_MCU_SUBSYS_STAT1			(AO_CTRL_BASE + 0x444)
     88 #define AO_SC_MCU_SUBSYS_STAT2			(AO_CTRL_BASE + 0x448)
     89 #define AO_SC_MCU_SUBSYS_STAT3			(AO_CTRL_BASE + 0x44C)
     90 #define AO_SC_MCU_SUBSYS_STAT4			(AO_CTRL_BASE + 0x450)
     91 #define AO_SC_MCU_SUBSYS_STAT5			(AO_CTRL_BASE + 0x454)
     92 #define AO_SC_MCU_SUBSYS_STAT6			(AO_CTRL_BASE + 0x458)
     93 #define AO_SC_MCU_SUBSYS_STAT7			(AO_CTRL_BASE + 0x45C)
     94 #define AO_SC_PERIPH_CLKEN4			(AO_CTRL_BASE + 0x630)
     95 #define AO_SC_PERIPH_CLKDIS4			(AO_CTRL_BASE + 0x634)
     96 #define AO_SC_PERIPH_CLKSTAT4			(AO_CTRL_BASE + 0x638)
     97 #define AO_SC_PERIPH_CLKEN5			(AO_CTRL_BASE + 0x63C)
     98 #define AO_SC_PERIPH_CLKDIS5			(AO_CTRL_BASE + 0x640)
     99 #define AO_SC_PERIPH_CLKSTAT5			(AO_CTRL_BASE + 0x644)
    100 #define AO_SC_PERIPH_RSTEN4			(AO_CTRL_BASE + 0x6F0)
    101 #define AO_SC_PERIPH_RSTDIS4			(AO_CTRL_BASE + 0x6F4)
    102 #define AO_SC_PERIPH_RSTSTAT4			(AO_CTRL_BASE + 0x6F8)
    103 #define AO_SC_PERIPH_RSTEN5			(AO_CTRL_BASE + 0x6FC)
    104 #define AO_SC_PERIPH_RSTDIS5			(AO_CTRL_BASE + 0x700)
    105 #define AO_SC_PERIPH_RSTSTAT5			(AO_CTRL_BASE + 0x704)
    106 #define AO_SC_PW_CLKEN0				(AO_CTRL_BASE + 0x800)
    107 #define AO_SC_PW_CLKDIS0			(AO_CTRL_BASE + 0x804)
    108 #define AO_SC_PW_CLK_STAT0			(AO_CTRL_BASE + 0x808)
    109 #define AO_SC_PW_RSTEN0				(AO_CTRL_BASE + 0x810)
    110 #define AO_SC_PW_RSTDIS0			(AO_CTRL_BASE + 0x814)
    111 #define AO_SC_PW_RST_STAT0			(AO_CTRL_BASE + 0x818)
    112 #define AO_SC_PW_ISOEN0				(AO_CTRL_BASE + 0x820)
    113 #define AO_SC_PW_ISODIS0			(AO_CTRL_BASE + 0x824)
    114 #define AO_SC_PW_ISO_STAT0			(AO_CTRL_BASE + 0x828)
    115 #define AO_SC_PW_MTCMOS_EN0			(AO_CTRL_BASE + 0x830)
    116 #define AO_SC_PW_MTCMOS_DIS0			(AO_CTRL_BASE + 0x834)
    117 #define AO_SC_PW_MTCMOS_STAT0			(AO_CTRL_BASE + 0x838)
    118 #define AO_SC_PW_MTCMOS_ACK_STAT0		(AO_CTRL_BASE + 0x83C)
    119 #define AO_SC_PW_MTCMOS_TIMEOUT_STAT0		(AO_CTRL_BASE + 0x840)
    120 #define AO_SC_PW_STAT0				(AO_CTRL_BASE + 0x850)
    121 #define AO_SC_PW_STAT1				(AO_CTRL_BASE + 0x854)
    122 #define AO_SC_SYSTEST_STAT			(AO_CTRL_BASE + 0x880)
    123 #define AO_SC_SYSTEST_SLICER_CNT0		(AO_CTRL_BASE + 0x890)
    124 #define AO_SC_SYSTEST_SLICER_CNT1		(AO_CTRL_BASE + 0x894)
    125 #define AO_SC_PW_CTRL1				(AO_CTRL_BASE + 0x8C8)
    126 #define AO_SC_PW_CTRL				(AO_CTRL_BASE + 0x8CC)
    127 #define AO_SC_MCPU_VOTEEN			(AO_CTRL_BASE + 0x8D0)
    128 #define AO_SC_MCPU_VOTEDIS			(AO_CTRL_BASE + 0x8D4)
    129 #define AO_SC_MCPU_VOTESTAT			(AO_CTRL_BASE + 0x8D8)
    130 #define AO_SC_MCPU_VOTE_MSK0			(AO_CTRL_BASE + 0x8E0)
    131 #define AO_SC_MCPU_VOTE_MSK1			(AO_CTRL_BASE + 0x8E4)
    132 #define AO_SC_MCPU_VOTESTAT0_MSK		(AO_CTRL_BASE + 0x8E8)
    133 #define AO_SC_MCPU_VOTESTAT1_MSK		(AO_CTRL_BASE + 0x8EC)
    134 #define AO_SC_PERI_VOTEEN			(AO_CTRL_BASE + 0x8F0)
    135 #define AO_SC_PERI_VOTEDIS			(AO_CTRL_BASE + 0x8F4)
    136 #define AO_SC_PERI_VOTESTAT			(AO_CTRL_BASE + 0x8F8)
    137 #define AO_SC_PERI_VOTE_MSK0			(AO_CTRL_BASE + 0x900)
    138 #define AO_SC_PERI_VOTE_MSK1			(AO_CTRL_BASE + 0x904)
    139 #define AO_SC_PERI_VOTESTAT0_MSK		(AO_CTRL_BASE + 0x908)
    140 #define AO_SC_PERI_VOTESTAT1_MSK		(AO_CTRL_BASE + 0x90C)
    141 #define AO_SC_ACPU_VOTEEN			(AO_CTRL_BASE + 0x910)
    142 #define AO_SC_ACPU_VOTEDIS			(AO_CTRL_BASE + 0x914)
    143 #define AO_SC_ACPU_VOTESTAT			(AO_CTRL_BASE + 0x918)
    144 #define AO_SC_ACPU_VOTE_MSK0			(AO_CTRL_BASE + 0x920)
    145 #define AO_SC_ACPU_VOTE_MSK1			(AO_CTRL_BASE + 0x924)
    146 #define AO_SC_ACPU_VOTESTAT0_MSK		(AO_CTRL_BASE + 0x928)
    147 #define AO_SC_ACPU_VOTESTAT1_MSK		(AO_CTRL_BASE + 0x92C)
    148 #define AO_SC_MCU_VOTEEN			(AO_CTRL_BASE + 0x930)
    149 #define AO_SC_MCU_VOTEDIS			(AO_CTRL_BASE + 0x934)
    150 #define AO_SC_MCU_VOTESTAT			(AO_CTRL_BASE + 0x938)
    151 #define AO_SC_MCU_VOTE_MSK0			(AO_CTRL_BASE + 0x940)
    152 #define AO_SC_MCU_VOTE_MSK1			(AO_CTRL_BASE + 0x944)
    153 #define AO_SC_MCU_VOTESTAT0_MSK			(AO_CTRL_BASE + 0x948)
    154 #define AO_SC_MCU_VOTESTAT1_MSK			(AO_CTRL_BASE + 0x94C)
    155 #define AO_SC_MCU_VOTE1EN			(AO_CTRL_BASE + 0x960)
    156 #define AO_SC_MCU_VOTE1DIS			(AO_CTRL_BASE + 0x964)
    157 #define AO_SC_MCU_VOTE1STAT			(AO_CTRL_BASE + 0x968)
    158 #define AO_SC_MCU_VOTE1_MSK0			(AO_CTRL_BASE + 0x970)
    159 #define AO_SC_MCU_VOTE1_MSK1			(AO_CTRL_BASE + 0x974)
    160 #define AO_SC_MCU_VOTE1STAT0_MSK		(AO_CTRL_BASE + 0x978)
    161 #define AO_SC_MCU_VOTE1STAT1_MSK		(AO_CTRL_BASE + 0x97C)
    162 #define AO_SC_MCU_VOTE2EN			(AO_CTRL_BASE + 0x980)
    163 #define AO_SC_MCU_VOTE2DIS			(AO_CTRL_BASE + 0x984)
    164 #define AO_SC_MCU_VOTE2STAT			(AO_CTRL_BASE + 0x988)
    165 #define AO_SC_MCU_VOTE2_MSK0			(AO_CTRL_BASE + 0x990)
    166 #define AO_SC_MCU_VOTE2_MSK1			(AO_CTRL_BASE + 0x994)
    167 #define AO_SC_MCU_VOTE2STAT0_MSK		(AO_CTRL_BASE + 0x998)
    168 #define AO_SC_MCU_VOTE2STAT1_MSK		(AO_CTRL_BASE + 0x99C)
    169 #define AO_SC_VOTE_CTRL				(AO_CTRL_BASE + 0x9A0)
    170 #define AO_SC_VOTE_STAT				(AO_CTRL_BASE + 0x9A4)
    171 #define AO_SC_ECONUM				(AO_CTRL_BASE + 0xF00)
    172 #define AO_SCCHIPID				(AO_CTRL_BASE + 0xF10)
    173 #define AO_SCSOCID				(AO_CTRL_BASE + 0xF1C)
    174 #define AO_SC_SOC_FPGA_RTL_DEF			(AO_CTRL_BASE + 0xFE0)
    175 #define AO_SC_SOC_FPGA_PR_DEF			(AO_CTRL_BASE + 0xFE4)
    176 #define AO_SC_SOC_FPGA_RES_DEF0			(AO_CTRL_BASE + 0xFE8)
    177 #define AO_SC_SOC_FPGA_RES_DEF1			(AO_CTRL_BASE + 0xFEC)
    178 #define AO_SC_XTAL_CTRL0			(AO_CTRL_BASE + 0x102)
    179 #define AO_SC_XTAL_CTRL1			(AO_CTRL_BASE + 0x102)
    180 #define AO_SC_XTAL_CTRL3			(AO_CTRL_BASE + 0x103)
    181 #define AO_SC_XTAL_CTRL5			(AO_CTRL_BASE + 0x103)
    182 #define AO_SC_XTAL_STAT0			(AO_CTRL_BASE + 0x106)
    183 #define AO_SC_XTAL_STAT1			(AO_CTRL_BASE + 0x107)
    184 #define AO_SC_EFUSE_CHIPID0			(AO_CTRL_BASE + 0x108)
    185 #define AO_SC_EFUSE_CHIPID1			(AO_CTRL_BASE + 0x108)
    186 #define AO_SC_EFUSE_SYS_CTRL			(AO_CTRL_BASE + 0x108)
    187 #define AO_SC_DEBUG_CTRL1			(AO_CTRL_BASE + 0x128)
    188 #define AO_SC_DBG_STAT				(AO_CTRL_BASE + 0x12B)
    189 #define AO_SC_ARM_DBG_KEY0			(AO_CTRL_BASE + 0x12B)
    190 #define AO_SC_RESERVED31			(AO_CTRL_BASE + 0x13A)
    191 #define AO_SC_RESERVED32			(AO_CTRL_BASE + 0x13A)
    192 #define AO_SC_RESERVED33			(AO_CTRL_BASE + 0x13A)
    193 #define AO_SC_RESERVED34			(AO_CTRL_BASE + 0x13A)
    194 #define AO_SC_RESERVED35			(AO_CTRL_BASE + 0x13B)
    195 #define AO_SC_RESERVED36			(AO_CTRL_BASE + 0x13B)
    196 #define AO_SC_RESERVED37			(AO_CTRL_BASE + 0x13B)
    197 #define AO_SC_RESERVED38			(AO_CTRL_BASE + 0x13B)
    198 #define AO_SC_ALWAYSON_SYS_CTRL0		(AO_CTRL_BASE + 0x148)
    199 #define AO_SC_ALWAYSON_SYS_CTRL1		(AO_CTRL_BASE + 0x148)
    200 #define AO_SC_ALWAYSON_SYS_CTRL2		(AO_CTRL_BASE + 0x148)
    201 #define AO_SC_ALWAYSON_SYS_CTRL3		(AO_CTRL_BASE + 0x148)
    202 #define AO_SC_ALWAYSON_SYS_CTRL10		(AO_CTRL_BASE + 0x14A)
    203 #define AO_SC_ALWAYSON_SYS_CTRL11		(AO_CTRL_BASE + 0x14A)
    204 #define AO_SC_ALWAYSON_SYS_STAT0		(AO_CTRL_BASE + 0x14C)
    205 #define AO_SC_ALWAYSON_SYS_STAT1		(AO_CTRL_BASE + 0x14C)
    206 #define AO_SC_ALWAYSON_SYS_STAT2		(AO_CTRL_BASE + 0x14C)
    207 #define AO_SC_ALWAYSON_SYS_STAT3		(AO_CTRL_BASE + 0x14C)
    208 #define AO_SC_PWUP_TIME0			(AO_CTRL_BASE + 0x188)
    209 #define AO_SC_PWUP_TIME1			(AO_CTRL_BASE + 0x188)
    210 #define AO_SC_PWUP_TIME2			(AO_CTRL_BASE + 0x188)
    211 #define AO_SC_PWUP_TIME3			(AO_CTRL_BASE + 0x188)
    212 #define AO_SC_PWUP_TIME4			(AO_CTRL_BASE + 0x189)
    213 #define AO_SC_PWUP_TIME5			(AO_CTRL_BASE + 0x189)
    214 #define AO_SC_PWUP_TIME6			(AO_CTRL_BASE + 0x189)
    215 #define AO_SC_PWUP_TIME7			(AO_CTRL_BASE + 0x189)
    216 #define AO_SC_SECURITY_CTRL1			(AO_CTRL_BASE + 0x1C0)
    217 #define AO_SC_SYSTEST_SLICER_CNT0		(AO_CTRL_BASE + 0x890)
    218 #define AO_SC_SYSTEST_SLICER_CNT1		(AO_CTRL_BASE + 0x894)
    219 
    220 #define AO_SC_SYS_CTRL0_MODE_NORMAL				0x004
    221 #define AO_SC_SYS_CTRL0_MODE_MASK				0x007
    222 
    223 #define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG				(1 << 0)
    224 #define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM				(1 << 1)
    225 #define AO_SC_SYS_CTRL1_EFUSEC_REMAP				(1 << 2)
    226 #define AO_SC_SYS_CTRL1_EXT_PLL_SEL				(1 << 3)
    227 #define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG			(1 << 4)
    228 #define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG			(1 << 6)
    229 #define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG			(1 << 7)
    230 #define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG			(1 << 8)
    231 #define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG			(1 << 9)
    232 #define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG			(1 << 10)
    233 #define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1			(1 << 11)
    234 #define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT			(1 << 12)
    235 #define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT			(1 << 13)
    236 #define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG			(1 << 15)
    237 #define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK			(1 << 16)
    238 #define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK			(1 << 17)
    239 #define AO_SC_SYS_CTRL1_EFUSEC_REMAP_MSK			(1 << 18)
    240 #define AO_SC_SYS_CTRL1_EXT_PLL_SEL_MSK				(1 << 19)
    241 #define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK			(1 << 20)
    242 #define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK		(1 << 22)
    243 #define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK			(1 << 23)
    244 #define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK		(1 << 24)
    245 #define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK			(1 << 25)
    246 #define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK			(1 << 26)
    247 #define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK		(1 << 27)
    248 #define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK			(1 << 28)
    249 #define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK			(1 << 29)
    250 #define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK			(1 << 31)
    251 
    252 #define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR			(1 << 26)
    253 #define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR			(1 << 27)
    254 #define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR			(1 << 28)
    255 #define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR			(1 << 29)
    256 #define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR			(1 << 30)
    257 #define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR			(1 << 31)
    258 
    259 #define AO_SC_SYS_STAT0_MCU_RST_STAT				(1 << 25)
    260 #define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT			(1 << 26)
    261 #define AO_SC_SYS_STAT0_MCU_WDGRST_STAT				(1 << 27)
    262 #define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT			(1 << 28)
    263 #define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT			(1 << 29)
    264 #define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT			(1 << 30)
    265 #define AO_SC_SYS_STAT0_GLB_SRST_STAT				(1 << 31)
    266 
    267 #define AO_SC_SYS_STAT1_MODE_STATUS				(1 << 0)
    268 #define AO_SC_SYS_STAT1_BOOT_SEL_LOCK				(1 << 16)
    269 #define AO_SC_SYS_STAT1_FUNC_MODE_LOCK				(1 << 17)
    270 #define AO_SC_SYS_STAT1_BOOT_MODE_LOCK				(1 << 19)
    271 #define AO_SC_SYS_STAT1_FUN_JTAG_MODE_OUT			(1 << 20)
    272 #define AO_SC_SYS_STAT1_SECURITY_BOOT_FLG			(1 << 27)
    273 #define AO_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK			(1 << 28)
    274 #define AO_SC_SYS_STAT1_EFUSE_NAND_BITWIDE			(1 << 29)
    275 
    276 #define AO_SC_PERIPH_RSTDIS4_RESET_MCU_ECTR_N			(1 << 0)
    277 #define AO_SC_PERIPH_RSTDIS4_RESET_MCU_SYS_N			(1 << 1)
    278 #define AO_SC_PERIPH_RSTDIS4_RESET_MCU_POR_N			(1 << 2)
    279 #define AO_SC_PERIPH_RSTDIS4_RESET_MCU_DAP_N			(1 << 3)
    280 #define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER0_N		(1 << 4)
    281 #define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER1_N		(1 << 5)
    282 #define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT0_N			(1 << 6)
    283 #define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT1_N			(1 << 7)
    284 #define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_S_N			(1 << 8)
    285 #define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_NS_N			(1 << 9)
    286 #define AO_SC_PERIPH_RSTDIS4_PRESET_EFUSEC_N			(1 << 10)
    287 #define AO_SC_PERIPH_RSTDIS4_PRESET_WDT0_N			(1 << 12)
    288 #define AO_SC_PERIPH_RSTDIS4_PRESET_WDT1_N			(1 << 13)
    289 #define AO_SC_PERIPH_RSTDIS4_PRESET_WDT2_N			(1 << 14)
    290 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER0_N			(1 << 15)
    291 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER1_N			(1 << 16)
    292 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER2_N			(1 << 17)
    293 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER3_N			(1 << 18)
    294 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER4_N			(1 << 19)
    295 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER5_N			(1 << 20)
    296 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER6_N			(1 << 21)
    297 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER7_N			(1 << 22)
    298 #define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER8_N			(1 << 23)
    299 #define AO_SC_PERIPH_RSTDIS4_PRESET_UART0_N			(1 << 24)
    300 #define AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N			(1 << 25)
    301 #define AO_SC_PERIPH_RSTDIS4_RESET_RTC1_N			(1 << 26)
    302 #define AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N			(1 << 27)
    303 #define AO_SC_PERIPH_RSTDIS4_RESET_JTAG_AUTH_N			(1 << 28)
    304 #define AO_SC_PERIPH_RSTDIS4_RESET_CS_DAPB_ON_N			(1 << 29)
    305 #define AO_SC_PERIPH_RSTDIS4_MDM_SUBSYS_GLB			(1 << 30)
    306 
    307 #define AO_SC_PERIPH_CLKEN4_HCLK_MCU				(1 << 0)
    308 #define AO_SC_PERIPH_CLKEN4_CLK_MCU_DAP				(1 << 3)
    309 #define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER0			(1 << 4)
    310 #define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER1			(1 << 5)
    311 #define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT0			(1 << 6)
    312 #define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT1			(1 << 7)
    313 #define AO_SC_PERIPH_CLKEN4_HCLK_IPC_S				(1 << 8)
    314 #define AO_SC_PERIPH_CLKEN4_HCLK_IPC_NS				(1 << 9)
    315 #define AO_SC_PERIPH_CLKEN4_PCLK_EFUSEC				(1 << 10)
    316 #define AO_SC_PERIPH_CLKEN4_PCLK_TZPC				(1 << 11)
    317 #define AO_SC_PERIPH_CLKEN4_PCLK_WDT0				(1 << 12)
    318 #define AO_SC_PERIPH_CLKEN4_PCLK_WDT1				(1 << 13)
    319 #define AO_SC_PERIPH_CLKEN4_PCLK_WDT2				(1 << 14)
    320 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER0				(1 << 15)
    321 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER1				(1 << 16)
    322 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER2				(1 << 17)
    323 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER3				(1 << 18)
    324 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER4				(1 << 19)
    325 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER5				(1 << 20)
    326 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER6				(1 << 21)
    327 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER7				(1 << 22)
    328 #define AO_SC_PERIPH_CLKEN4_PCLK_TIMER8				(1 << 23)
    329 #define AO_SC_PERIPH_CLKEN4_CLK_UART0				(1 << 24)
    330 #define AO_SC_PERIPH_CLKEN4_CLK_RTC0				(1 << 25)
    331 #define AO_SC_PERIPH_CLKEN4_CLK_RTC1				(1 << 26)
    332 #define AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI				(1 << 27)
    333 #define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH			(1 << 28)
    334 #define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON			(1 << 29)
    335 #define AO_SC_PERIPH_CLKEN4_CLK_PDM				(1 << 30)
    336 #define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD				(1 << 31)
    337 
    338 #define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU			(1 << 0)
    339 #define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU			(1 << 1)
    340 #define AO_SC_PERIPH_CLKEN5_HCLK_IPC_CCPU			(1 << 2)
    341 #define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_CCPU			(1 << 3)
    342 #define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU			(1 << 16)
    343 #define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_MCU			(1 << 17)
    344 #define AO_SC_PERIPH_CLKEN5_HCLK_IPC_MCU			(1 << 18)
    345 #define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_MCU			(1 << 19)
    346 
    347 #define AO_SC_MCU_SUBSYS_CTRL3_RCLK_3				0x003
    348 #define AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK			0x007
    349 #define AO_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT			(1 << 3)
    350 #define AO_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG			(1 << 4)
    351 #define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1		(1 << 8)
    352 #define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0		(1 << 9)
    353 #define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD			(1 << 10)
    354 #define AO_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED	(1 << 11)
    355 
    356 #define PCLK_TIMER1						(1 << 16)
    357 #define PCLK_TIMER0						(1 << 15)
    358 
    359 #endif /* __HI6220_AO_H__ */
    360