| /external/clang/test/SemaTemplate/ |
| value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) {
6 return Cond? "honk" : N;
9 const char *f1(bool Cond) {
10 return Cond? N : "honk";
|
| /external/deqp/framework/delibs/decpp/ |
| deMeta.hpp | 33 template <typename T, bool Cond>
42 template <bool Cond>
47 Value = !Cond
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 118 SmallVectorImpl<MachineOperand> &Cond,
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
147 Cond.push_back(LastInst->getOperand(0));
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
166 Cond.push_back(SecondLastInst->getOperand(0));
189 const SmallVectorImpl<MachineOperand> &Cond,
193 assert((Cond.size() == 2 || Cond.size() == 0) &&
197 if (!Cond.empty())
198 Opc = (unsigned)Cond[0].getImm()
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 98 SmallVectorImpl<MachineOperand> &Cond,
112 Cond.push_back(MachineOperand::CreateImm(true));
113 Cond.push_back(MI.getOperand(1));
123 Cond.push_back(MachineOperand::CreateImm(false));
124 Cond.push_back(MI.getOperand(1));
167 ArrayRef<MachineOperand> Cond,
169 if (Cond.empty()) {
177 assert(Cond.size() == 2 && "Expected a flag and a successor block");
179 if (Cond[0].getImm()) {
180 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).addOperand(Cond[1])
[all...] |
| WebAssemblyInstrInfo.h | 49 SmallVectorImpl<MachineOperand> &Cond,
53 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
56 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| SPIRVError.h | 103 SPIRVErrorLog::checkError(bool Cond, SPIRVErrorCode ErrCode,
107 if (Cond)
108 return Cond;
111 return Cond;
121 return Cond;
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 73 SmallVectorImpl<MachineOperand> &Cond) const {
80 Cond.push_back(MachineOperand::CreateImm(Opc));
83 Cond.push_back(Inst->getOperand(i));
89 SmallVectorImpl<MachineOperand> &Cond,
92 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
99 ArrayRef<MachineOperand> Cond) const {
100 unsigned Opc = Cond[0].getImm();
104 for (unsigned i = 1; i < Cond.size(); ++i) {
105 if (Cond[i].isReg())
106 MIB.addReg(Cond[i].getReg())
[all...] |
| MipsInstrInfo.h | 55 SmallVectorImpl<MachineOperand> &Cond,
61 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
65 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
69 SmallVectorImpl<MachineOperand> &Cond,
147 SmallVectorImpl<MachineOperand> &Cond) const;
150 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 189 SmallVectorImpl<MachineOperand> &Cond,
222 Cond.push_back(MachineOperand::CreateImm(BranchCode));
223 Cond.push_back(LastInst->getOperand(0));
244 Cond.push_back(MachineOperand::CreateImm(BranchCode));
245 Cond.push_back(SecondLastInst->getOperand(0));
277 const SmallVectorImpl<MachineOperand> &Cond,
281 assert((Cond.size() == 2 || Cond.size() == 0) &&
285 if (Cond.empty()) {
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm())
[all...] |
| XCoreInstrInfo.h | 54 SmallVectorImpl<MachineOperand> &Cond,
59 const SmallVectorImpl<MachineOperand> &Cond,
88 SmallVectorImpl<MachineOperand> &Cond) const;
|
| /prebuilts/go/darwin-x86/src/sync/ |
| cond.go | 12 // Cond implements a condition variable, a rendezvous point
16 // Each Cond has an associated Locker L (often a *Mutex or *RWMutex),
20 // A Cond can be created as part of other structures.
21 // A Cond must not be copied after first use.
22 type Cond struct {
32 // NewCond returns a new Cond with Locker l.
33 func NewCond(l Locker) *Cond {
34 return &Cond{L: l}
53 func (c *Cond) Wait() {
65 func (c *Cond) Signal()
[all...] |
| /prebuilts/go/linux-x86/src/sync/ |
| cond.go | 12 // Cond implements a condition variable, a rendezvous point
16 // Each Cond has an associated Locker L (often a *Mutex or *RWMutex),
20 // A Cond can be created as part of other structures.
21 // A Cond must not be copied after first use.
22 type Cond struct {
32 // NewCond returns a new Cond with Locker l.
33 func NewCond(l Locker) *Cond {
34 return &Cond{L: l}
53 func (c *Cond) Wait() {
65 func (c *Cond) Signal()
[all...] |
| /external/clang/test/SemaCXX/ |
| vector.cpp | 43 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e,
46 __typeof__(Cond? c16 : c16) *c16p1 = &c16;
47 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16;
48 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e;
49 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e;
52 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e;
53 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e;
54 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e;
55 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e;
58 (void)(Cond? c16 : ll16)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 90 const SmallVectorImpl<MachineOperand> &Cond,
93 assert((Cond.size() == 2 || Cond.size() == 0) &&
98 if (Cond.empty()) // Unconditional branch
101 if (isAlphaIntCondCode(Cond[0].getImm()))
103 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
106 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
111 if (isAlphaIntCondCode(Cond[0].getImm())
[all...] |
| AlphaInstrInfo.h | 43 const SmallVectorImpl<MachineOperand> &Cond,
63 SmallVectorImpl<MachineOperand> &Cond,
68 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.h | 49 SmallVectorImpl<MachineOperand> &Cond,
54 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 64 SmallVectorImpl<MachineOperand> &Cond,
68 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_emulate_loops.h | 12 struct rc_instruction * Cond;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrInfo.h | 145 SmallVectorImpl<MachineOperand> &Cond,
151 const SmallVectorImpl<MachineOperand>& Cond) const;
156 const SmallVectorImpl<MachineOperand> &Cond,
180 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 75 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
79 SmallVectorImpl<MachineOperand> &Cond,
84 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 70 SmallVectorImpl<MachineOperand> &Cond,
76 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
80 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 55 SmallVectorImpl<MachineOperand> &Cond,
59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
81 SmallVectorImpl<MachineOperand> &Cond) const override;
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.h | 68 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
72 SmallVectorImpl<MachineOperand> &Cond,
79 const SmallVectorImpl<MachineOperand> &Cond,
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 75 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
79 SmallVectorImpl<MachineOperand> &Cond,
85 const SmallVectorImpl<MachineOperand> &Cond,
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 85 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
90 SmallVectorImpl<MachineOperand> &Cond,
94 const SmallVectorImpl<MachineOperand> &Cond,
|
