1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of the TargetInstrInfo class. 11 // 12 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in 13 // order for MipsLongBranch pass to work correctly when the code has inline 14 // assembly. The returned value doesn't have to be the asm instruction's exact 15 // size in bytes; MipsLongBranch only expects it to be the correct upper bound. 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 20 21 #include "Mips.h" 22 #include "MipsRegisterInfo.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Target/TargetInstrInfo.h" 26 27 #define GET_INSTRINFO_HEADER 28 #include "MipsGenInstrInfo.inc" 29 30 namespace llvm { 31 class MipsSubtarget; 32 class MipsInstrInfo : public MipsGenInstrInfo { 33 virtual void anchor(); 34 protected: 35 const MipsSubtarget &Subtarget; 36 unsigned UncondBrOpc; 37 38 public: 39 enum BranchType { 40 BT_None, // Couldn't analyze branch. 41 BT_NoBranch, // No branches found. 42 BT_Uncond, // One unconditional branch. 43 BT_Cond, // One conditional branch. 44 BT_CondUncond, // A conditional branch followed by an unconditional branch. 45 BT_Indirect // One indirct branch. 46 }; 47 48 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); 49 50 static const MipsInstrInfo *create(MipsSubtarget &STI); 51 52 /// Branch Analysis 53 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 54 MachineBasicBlock *&FBB, 55 SmallVectorImpl<MachineOperand> &Cond, 56 bool AllowModify) const override; 57 58 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 59 60 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 61 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 62 const DebugLoc &DL) const override; 63 64 bool 65 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 66 67 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 68 MachineBasicBlock *&FBB, 69 SmallVectorImpl<MachineOperand> &Cond, 70 bool AllowModify, 71 SmallVectorImpl<MachineInstr *> &BranchInstrs) const; 72 73 /// Determine the opcode of a non-delay slot form for a branch if one exists. 74 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const; 75 76 /// Predicate to determine if an instruction can go in a forbidden slot. 77 bool SafeInForbiddenSlot(const MachineInstr &MI) const; 78 79 /// Predicate to determine if an instruction has a forbidden slot. 80 bool HasForbiddenSlot(const MachineInstr &MI) const; 81 82 /// Insert nop instruction when hazard condition is found 83 void insertNoop(MachineBasicBlock &MBB, 84 MachineBasicBlock::iterator MI) const override; 85 86 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 87 /// such, whenever a client has an instance of instruction info, it should 88 /// always be able to get register info as well (through this method). 89 /// 90 virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 91 92 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 93 94 /// Return the number of bytes of code the specified instruction may be. 95 unsigned GetInstSizeInBytes(const MachineInstr &MI) const; 96 97 void storeRegToStackSlot(MachineBasicBlock &MBB, 98 MachineBasicBlock::iterator MBBI, 99 unsigned SrcReg, bool isKill, int FrameIndex, 100 const TargetRegisterClass *RC, 101 const TargetRegisterInfo *TRI) const override { 102 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); 103 } 104 105 void loadRegFromStackSlot(MachineBasicBlock &MBB, 106 MachineBasicBlock::iterator MBBI, 107 unsigned DestReg, int FrameIndex, 108 const TargetRegisterClass *RC, 109 const TargetRegisterInfo *TRI) const override { 110 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); 111 } 112 113 virtual void storeRegToStack(MachineBasicBlock &MBB, 114 MachineBasicBlock::iterator MI, 115 unsigned SrcReg, bool isKill, int FrameIndex, 116 const TargetRegisterClass *RC, 117 const TargetRegisterInfo *TRI, 118 int64_t Offset) const = 0; 119 120 virtual void loadRegFromStack(MachineBasicBlock &MBB, 121 MachineBasicBlock::iterator MI, 122 unsigned DestReg, int FrameIndex, 123 const TargetRegisterClass *RC, 124 const TargetRegisterInfo *TRI, 125 int64_t Offset) const = 0; 126 127 virtual void adjustStackPtr(unsigned SP, int64_t Amount, 128 MachineBasicBlock &MBB, 129 MachineBasicBlock::iterator I) const = 0; 130 131 /// Create an instruction which has the same operands and memory operands 132 /// as MI but has a new opcode. 133 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, 134 MachineBasicBlock::iterator I) const; 135 136 protected: 137 bool isZeroImm(const MachineOperand &op) const; 138 139 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 140 unsigned Flag) const; 141 142 private: 143 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 144 145 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 146 MachineBasicBlock *&BB, 147 SmallVectorImpl<MachineOperand> &Cond) const; 148 149 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 150 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const; 151 }; 152 153 /// Create MipsInstrInfo objects. 154 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); 155 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); 156 157 } 158 159 #endif 160
