1 /* 2 * Copyright (c) 2014, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __DWC_USB_H__ 33 #define __DWC_USB_H__ 34 35 #define USB_DMA 36 37 #define DWC_OTG_BASE 0xF72C0000 38 39 #define USB_NUM_ENDPOINTS 2 40 #define MAX_EPS_CHANNELS 16 41 42 #define BULK_OUT_EP 1 43 #define BULK_IN_EP 1 44 45 #define RX_REQ_LEN 512 46 #define MAX_PACKET_LEN 512 47 48 #define DATA_FIFO_CONFIG (0x780 << GDFIFOCFG_EPINFOBASE_SHIFT |\ 49 0x800 << GDFIFOCFG_GDFIFOCFG_SHIFT) 50 /* RX FIFO: 2048 bytes */ 51 #define RX_SIZE 0x00000200 52 /* Non-periodic TX FIFO: 128 bytes. start address: 0x200 * 4. */ 53 #define ENDPOINT_TX_SIZE 0x00200200 54 55 /* EP1 TX FIFO: 1024 bytes. start address: 0x220 * 4. */ 56 /* EP2 TX FIFO: 1024 bytes. start address: 0x320 * 4. */ 57 /* EP3 TX FIFO: 1024 bytes. start address: 0x420 * 4. */ 58 /* EP4 TX FIFO: 1024 bytes. start address: 0x520 * 4. */ 59 /* EP5 TX FIFO: 128 bytes. start address: 0x620 * 4. */ 60 /* EP6 TX FIFO: 128 bytes. start address: 0x640 * 4. */ 61 /* EP7 TX FIFO: 128 bytes. start address: 0x660 * 4. */ 62 /* EP8 TX FIFO: 128 bytes. start address: 0x680 * 4. */ 63 /* EP9 TX FIFO: 128 bytes. start address: 0x6a0 * 4. */ 64 /* EP10 TX FIFO: 128 bytes. start address: 0x6c0 * 4. */ 65 /* EP11 TX FIFO: 128 bytes. start address: 0x6e0 * 4. */ 66 /* EP12 TX FIFO: 128 bytes. start address: 0x700 * 4. */ 67 /* EP13 TX FIFO: 128 bytes. start address: 0x720 * 4. */ 68 /* EP14 TX FIFO: 128 bytes. start address: 0x740 * 4. */ 69 /* EP15 TX FIFO: 128 bytes. start address: 0x760 * 4. */ 70 71 #define DATA_IN_ENDPOINT_TX_FIFO1 0x01000220 72 #define DATA_IN_ENDPOINT_TX_FIFO2 0x01000320 73 #define DATA_IN_ENDPOINT_TX_FIFO3 0x01000420 74 #define DATA_IN_ENDPOINT_TX_FIFO4 0x01000520 75 #define DATA_IN_ENDPOINT_TX_FIFO5 0x00200620 76 #define DATA_IN_ENDPOINT_TX_FIFO6 0x00200640 77 #define DATA_IN_ENDPOINT_TX_FIFO7 0x00200660 78 #define DATA_IN_ENDPOINT_TX_FIFO8 0x00200680 79 #define DATA_IN_ENDPOINT_TX_FIFO9 0x002006a0 80 #define DATA_IN_ENDPOINT_TX_FIFO10 0x002006c0 81 #define DATA_IN_ENDPOINT_TX_FIFO11 0x002006e0 82 #define DATA_IN_ENDPOINT_TX_FIFO12 0x00200700 83 #define DATA_IN_ENDPOINT_TX_FIFO13 0x00200720 84 #define DATA_IN_ENDPOINT_TX_FIFO14 0x00200740 85 #define DATA_IN_ENDPOINT_TX_FIFO15 0x00200760 86 87 typedef struct { 88 unsigned char type; 89 unsigned char request; 90 unsigned short value; 91 unsigned short index; 92 unsigned short length; 93 } setup_packet; 94 95 struct ept_queue_item { 96 unsigned int next; 97 unsigned int info; 98 }; 99 100 struct usb_request { 101 struct ept_queue_item *item; 102 void *buf; 103 unsigned int length; 104 void (*complete)(unsigned int actual, int status); 105 void *context; 106 }; 107 108 /*DWC_OTG regsiter descriptor*/ 109 /*Global CSR MAP*/ 110 #define GLOBAL_CSR_BASE (DWC_OTG_BASE) 111 /*Device mode CSR MAP*/ 112 #define DEVICE_CSR_BASE (DWC_OTG_BASE+0x800) 113 /*Device mode CSR MAP*/ 114 #define DEVICE_INEP_BASE (DWC_OTG_BASE+0x900) 115 /*Device mode CSR MAP*/ 116 #define DEVICE_OUTEP_BASE (DWC_OTG_BASE+0xB00) 117 118 /*** OTG LINK CORE REGISTERS ***/ 119 /* Core Global Registers */ 120 #define GOTGCTL (DWC_OTG_BASE + 0x000) 121 #define GOTGINT (DWC_OTG_BASE + 0x004) 122 #define GOTGINT_DBNCE_DONE (1 << 19) 123 #define GOTGINT_A_DEV_TOUT_CHG (1 << 18) 124 #define GOTGINT_HST_NEG_DET (1 << 17) 125 #define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9) 126 #define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8) 127 #define GOTGINT_SES_END_DET (1 << 2) 128 129 #define GAHBCFG (DWC_OTG_BASE + 0x008) 130 #define GAHBCFG_P_TXF_EMP_LVL (1 << 8) 131 #define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) 132 #define GAHBCFG_DMA_EN (1 << 5) 133 #define GAHBCFG_GLBL_INTR_EN (1 << 0) 134 #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ 135 GAHBCFG_NP_TXF_EMP_LVL | \ 136 GAHBCFG_DMA_EN | \ 137 GAHBCFG_GLBL_INTR_EN) 138 139 #define GUSBCFG (DWC_OTG_BASE + 0x00C) 140 #define GRSTCTL (DWC_OTG_BASE + 0x010) 141 #define GRSTCTL_AHBIDLE (1 << 31) 142 #define GRSTCTL_CSFTRST (1 << 0) 143 144 #define GINTSTS (DWC_OTG_BASE + 0x014) 145 #define GINTMSK (DWC_OTG_BASE + 0x018) 146 #define GINTSTS_WKUPINT (1 << 31) 147 #define GINTSTS_SESSREQINT (1 << 30) 148 #define GINTSTS_DISCONNINT (1 << 29) 149 #define GINTSTS_CONIDSTSCHNG (1 << 28) 150 #define GINTSTS_LPMTRANRCVD (1 << 27) 151 #define GINTSTS_PTXFEMP (1 << 26) 152 #define GINTSTS_HCHINT (1 << 25) 153 #define GINTSTS_PRTINT (1 << 24) 154 #define GINTSTS_RESETDET (1 << 23) 155 #define GINTSTS_FET_SUSP (1 << 22) 156 #define GINTSTS_INCOMPL_IP (1 << 21) 157 #define GINTSTS_INCOMPL_SOIN (1 << 20) 158 #define GINTSTS_OEPINT (1 << 19) 159 #define GINTSTS_IEPINT (1 << 18) 160 #define GINTSTS_EPMIS (1 << 17) 161 #define GINTSTS_RESTOREDONE (1 << 16) 162 #define GINTSTS_EOPF (1 << 15) 163 #define GINTSTS_ISOUTDROP (1 << 14) 164 #define GINTSTS_ENUMDONE (1 << 13) 165 #define GINTSTS_USBRST (1 << 12) 166 #define GINTSTS_USBSUSP (1 << 11) 167 #define GINTSTS_ERLYSUSP (1 << 10) 168 #define GINTSTS_I2CINT (1 << 9) 169 #define GINTSTS_ULPI_CK_INT (1 << 8) 170 #define GINTSTS_GOUTNAKEFF (1 << 7) 171 #define GINTSTS_GINNAKEFF (1 << 6) 172 #define GINTSTS_NPTXFEMP (1 << 5) 173 #define GINTSTS_RXFLVL (1 << 4) 174 #define GINTSTS_SOF (1 << 3) 175 #define GINTSTS_OTGINT (1 << 2) 176 #define GINTSTS_MODEMIS (1 << 1) 177 #define GINTSTS_CURMODE_HOST (1 << 0) 178 179 #define GRXSTSR (DWC_OTG_BASE + 0x01C) 180 #define GRXSTSP (DWC_OTG_BASE + 0x020) 181 #define GRXFSIZ (DWC_OTG_BASE + 0x024) 182 #define GNPTXFSIZ (DWC_OTG_BASE + 0x028) 183 #define GNPTXSTS (DWC_OTG_BASE + 0x02C) 184 185 #define GHWCFG1 (DWC_OTG_BASE + 0x044) 186 #define GHWCFG2 (DWC_OTG_BASE + 0x048) 187 #define GHWCFG3 (DWC_OTG_BASE + 0x04c) 188 #define GHWCFG4 (DWC_OTG_BASE + 0x050) 189 #define GLPMCFG (DWC_OTG_BASE + 0x054) 190 191 #define GDFIFOCFG (DWC_OTG_BASE + 0x05c) 192 #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) 193 #define GDFIFOCFG_EPINFOBASE_SHIFT 16 194 #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) 195 #define GDFIFOCFG_GDFIFOCFG_SHIFT 0 196 197 198 #define HPTXFSIZ (DWC_OTG_BASE + 0x100) 199 #define DIEPTXF(x) (DWC_OTG_BASE + 0x100 + 4 * (x)) 200 #define DIEPTXF1 (DWC_OTG_BASE + 0x104) 201 #define DIEPTXF2 (DWC_OTG_BASE + 0x108) 202 #define DIEPTXF3 (DWC_OTG_BASE + 0x10C) 203 #define DIEPTXF4 (DWC_OTG_BASE + 0x110) 204 #define DIEPTXF5 (DWC_OTG_BASE + 0x114) 205 #define DIEPTXF6 (DWC_OTG_BASE + 0x118) 206 #define DIEPTXF7 (DWC_OTG_BASE + 0x11C) 207 #define DIEPTXF8 (DWC_OTG_BASE + 0x120) 208 #define DIEPTXF9 (DWC_OTG_BASE + 0x124) 209 #define DIEPTXF10 (DWC_OTG_BASE + 0x128) 210 #define DIEPTXF11 (DWC_OTG_BASE + 0x12C) 211 #define DIEPTXF12 (DWC_OTG_BASE + 0x130) 212 #define DIEPTXF13 (DWC_OTG_BASE + 0x134) 213 #define DIEPTXF14 (DWC_OTG_BASE + 0x138) 214 #define DIEPTXF15 (DWC_OTG_BASE + 0x13C) 215 216 /*** HOST MODE REGISTERS ***/ 217 /* Host Global Registers */ 218 #define HCFG (DWC_OTG_BASE + 0x400) 219 #define HFIR (DWC_OTG_BASE + 0x404) 220 #define HFNUM (DWC_OTG_BASE + 0x408) 221 #define HPTXSTS (DWC_OTG_BASE + 0x410) 222 #define HAINT (DWC_OTG_BASE + 0x414) 223 #define HAINTMSK (DWC_OTG_BASE + 0x418) 224 225 /* Host Port Control and Status Registers */ 226 #define HPRT (DWC_OTG_BASE + 0x440) 227 228 /* Host Channel-Specific Registers */ 229 #define HCCHAR(x) (DWC_OTG_BASE + 0x500 + 0x20 * (x)) 230 #define HCSPLT(x) (DWC_OTG_BASE + 0x504 + 0x20 * (x)) 231 #define HCINT(x) (DWC_OTG_BASE + 0x508 + 0x20 * (x)) 232 #define HCINTMSK(x) (DWC_OTG_BASE + 0x50C + 0x20 * (x)) 233 #define HCTSIZ(x) (DWC_OTG_BASE + 0x510 + 0x20 * (x)) 234 #define HCDMA(x) (DWC_OTG_BASE + 0x514 + 0x20 * (x)) 235 #define HCCHAR0 (DWC_OTG_BASE + 0x500) 236 #define HCSPLT0 (DWC_OTG_BASE + 0x504) 237 #define HCINT0 (DWC_OTG_BASE + 0x508) 238 #define HCINTMSK0 (DWC_OTG_BASE + 0x50C) 239 #define HCTSIZ0 (DWC_OTG_BASE + 0x510) 240 #define HCDMA0 (DWC_OTG_BASE + 0x514) 241 #define HCCHAR1 (DWC_OTG_BASE + 0x520) 242 #define HCSPLT1 (DWC_OTG_BASE + 0x524) 243 #define HCINT1 (DWC_OTG_BASE + 0x528) 244 #define HCINTMSK1 (DWC_OTG_BASE + 0x52C) 245 #define HCTSIZ1 (DWC_OTG_BASE + 0x530) 246 #define HCDMA1 (DWC_OTG_BASE + 0x534) 247 #define HCCHAR2 (DWC_OTG_BASE + 0x540) 248 #define HCSPLT2 (DWC_OTG_BASE + 0x544) 249 #define HCINT2 (DWC_OTG_BASE + 0x548) 250 #define HCINTMSK2 (DWC_OTG_BASE + 0x54C) 251 #define HCTSIZ2 (DWC_OTG_BASE + 0x550) 252 #define HCDMA2 (DWC_OTG_BASE + 0x554) 253 #define HCCHAR3 (DWC_OTG_BASE + 0x560) 254 #define HCSPLT3 (DWC_OTG_BASE + 0x564) 255 #define HCINT3 (DWC_OTG_BASE + 0x568) 256 #define HCINTMSK3 (DWC_OTG_BASE + 0x56C) 257 #define HCTSIZ3 (DWC_OTG_BASE + 0x570) 258 #define HCDMA3 (DWC_OTG_BASE + 0x574) 259 #define HCCHAR4 (DWC_OTG_BASE + 0x580) 260 #define HCSPLT4 (DWC_OTG_BASE + 0x584) 261 #define HCINT4 (DWC_OTG_BASE + 0x588) 262 #define HCINTMSK4 (DWC_OTG_BASE + 0x58C) 263 #define HCTSIZ4 (DWC_OTG_BASE + 0x590) 264 #define HCDMA4 (DWC_OTG_BASE + 0x594) 265 #define HCCHAR5 (DWC_OTG_BASE + 0x5A0) 266 #define HCSPLT5 (DWC_OTG_BASE + 0x5A4) 267 #define HCINT5 (DWC_OTG_BASE + 0x5A8) 268 #define HCINTMSK5 (DWC_OTG_BASE + 0x5AC) 269 #define HCTSIZ5 (DWC_OTG_BASE + 0x5B0) 270 #define HCDMA5 (DWC_OTG_BASE + 0x5B4) 271 #define HCCHAR6 (DWC_OTG_BASE + 0x5C0) 272 #define HCSPLT6 (DWC_OTG_BASE + 0x5C4) 273 #define HCINT6 (DWC_OTG_BASE + 0x5C8) 274 #define HCINTMSK6 (DWC_OTG_BASE + 0x5CC) 275 #define HCTSIZ6 (DWC_OTG_BASE + 0x5D0) 276 #define HCDMA6 (DWC_OTG_BASE + 0x5D4) 277 #define HCCHAR7 (DWC_OTG_BASE + 0x5E0) 278 #define HCSPLT7 (DWC_OTG_BASE + 0x5E4) 279 #define HCINT7 (DWC_OTG_BASE + 0x5E8) 280 #define HCINTMSK7 (DWC_OTG_BASE + 0x5EC) 281 #define HCTSIZ7 (DWC_OTG_BASE + 0x5F0) 282 #define HCDMA7 (DWC_OTG_BASE + 0x5F4) 283 #define HCCHAR8 (DWC_OTG_BASE + 0x600) 284 #define HCSPLT8 (DWC_OTG_BASE + 0x604) 285 #define HCINT8 (DWC_OTG_BASE + 0x608) 286 #define HCINTMSK8 (DWC_OTG_BASE + 0x60C) 287 #define HCTSIZ8 (DWC_OTG_BASE + 0x610) 288 #define HCDMA8 (DWC_OTG_BASE + 0x614) 289 #define HCCHAR9 (DWC_OTG_BASE + 0x620) 290 #define HCSPLT9 (DWC_OTG_BASE + 0x624) 291 #define HCINT9 (DWC_OTG_BASE + 0x628) 292 #define HCINTMSK9 (DWC_OTG_BASE + 0x62C) 293 #define HCTSIZ9 (DWC_OTG_BASE + 0x630) 294 #define HCDMA9 (DWC_OTG_BASE + 0x634) 295 #define HCCHAR10 (DWC_OTG_BASE + 0x640) 296 #define HCSPLT10 (DWC_OTG_BASE + 0x644) 297 #define HCINT10 (DWC_OTG_BASE + 0x648) 298 #define HCINTMSK10 (DWC_OTG_BASE + 0x64C) 299 #define HCTSIZ10 (DWC_OTG_BASE + 0x650) 300 #define HCDMA10 (DWC_OTG_BASE + 0x654) 301 #define HCCHAR11 (DWC_OTG_BASE + 0x660) 302 #define HCSPLT11 (DWC_OTG_BASE + 0x664) 303 #define HCINT11 (DWC_OTG_BASE + 0x668) 304 #define HCINTMSK11 (DWC_OTG_BASE + 0x66C) 305 #define HCTSIZ11 (DWC_OTG_BASE + 0x670) 306 #define HCDMA11 (DWC_OTG_BASE + 0x674) 307 #define HCCHAR12 (DWC_OTG_BASE + 0x680) 308 #define HCSPLT12 (DWC_OTG_BASE + 0x684) 309 #define HCINT12 (DWC_OTG_BASE + 0x688) 310 #define HCINTMSK12 (DWC_OTG_BASE + 0x68C) 311 #define HCTSIZ12 (DWC_OTG_BASE + 0x690) 312 #define HCDMA12 (DWC_OTG_BASE + 0x694) 313 #define HCCHAR13 (DWC_OTG_BASE + 0x6A0) 314 #define HCSPLT13 (DWC_OTG_BASE + 0x6A4) 315 #define HCINT13 (DWC_OTG_BASE + 0x6A8) 316 #define HCINTMSK13 (DWC_OTG_BASE + 0x6AC) 317 #define HCTSIZ13 (DWC_OTG_BASE + 0x6B0) 318 #define HCDMA13 (DWC_OTG_BASE + 0x6B4) 319 #define HCCHAR14 (DWC_OTG_BASE + 0x6C0) 320 #define HCSPLT14 (DWC_OTG_BASE + 0x6C4) 321 #define HCINT14 (DWC_OTG_BASE + 0x6C8) 322 #define HCINTMSK14 (DWC_OTG_BASE + 0x6CC) 323 #define HCTSIZ14 (DWC_OTG_BASE + 0x6D0) 324 #define HCDMA14 (DWC_OTG_BASE + 0x6D4) 325 #define HCCHAR15 (DWC_OTG_BASE + 0x6E0) 326 #define HCSPLT15 (DWC_OTG_BASE + 0x6E4) 327 #define HCINT15 (DWC_OTG_BASE + 0x6E8) 328 #define HCINTMSK15 (DWC_OTG_BASE + 0x6EC) 329 #define HCTSIZ15 (DWC_OTG_BASE + 0x6F0) 330 #define HCDMA15 (DWC_OTG_BASE + 0x6F4) 331 332 /*** DEVICE MODE REGISTERS ***/ 333 /* Device Global Registers */ 334 #define DCFG (DWC_OTG_BASE + 0x800) 335 #define DCFG_EPMISCNT_MASK (0x1f << 18) 336 #define DCFG_EPMISCNT_SHIFT 18 337 #define DCFG_NZ_STS_OUT_HSHK (1 << 2) 338 339 #define DCTL (DWC_OTG_BASE + 0x804) 340 #define DSTS (DWC_OTG_BASE + 0x808) 341 #define DIEPMSK (DWC_OTG_BASE + 0x810) 342 #define DOEPMSK (DWC_OTG_BASE + 0x814) 343 #define DAINT (DWC_OTG_BASE + 0x818) 344 #define DAINTMSK (DWC_OTG_BASE + 0x81C) 345 #define DAINT_OUTEP_SHIFT 16 346 #define DAINT_OUTEP(_x) (1 << ((_x) + 16)) 347 #define DAINT_INEP(_x) (1 << (_x)) 348 349 #define DTKNQR1 (DWC_OTG_BASE + 0x820) 350 #define DTKNQR2 (DWC_OTG_BASE + 0x824) 351 #define DVBUSDIS (DWC_OTG_BASE + 0x828) 352 #define DVBUSPULSE (DWC_OTG_BASE + 0x82C) 353 #define DTHRCTL (DWC_OTG_BASE + 0x830) 354 355 /* Device Logical IN Endpoint-Specific Registers */ 356 #define DIEPCTL(x) (DWC_OTG_BASE + 0x900 + 0x20 * (x)) 357 #define DIEPINT(x) (DWC_OTG_BASE + 0x908 + 0x20 * (x)) 358 #define DIEPTSIZ(x) (DWC_OTG_BASE + 0x910 + 0x20 * (x)) 359 #define DIEPDMA(x) (DWC_OTG_BASE + 0x914 + 0x20 * (x)) 360 #define DTXFSTS(x) (DWC_OTG_BASE + 0x918 + 0x20 * (x)) 361 362 #define DIEPCTL0 (DWC_OTG_BASE + 0x900) 363 #define DIEPINT0 (DWC_OTG_BASE + 0x908) 364 #define DIEPTSIZ0 (DWC_OTG_BASE + 0x910) 365 #define DIEPDMA0 (DWC_OTG_BASE + 0x914) 366 #define DIEPCTL1 (DWC_OTG_BASE + 0x920) 367 #define DIEPINT1 (DWC_OTG_BASE + 0x928) 368 #define DIEPTSIZ1 (DWC_OTG_BASE + 0x930) 369 #define DIEPDMA1 (DWC_OTG_BASE + 0x934) 370 #define DIEPCTL2 (DWC_OTG_BASE + 0x940) 371 #define DIEPINT2 (DWC_OTG_BASE + 0x948) 372 #define DIEPTSIZ2 (DWC_OTG_BASE + 0x950) 373 #define DIEPDMA2 (DWC_OTG_BASE + 0x954) 374 #define DIEPCTL3 (DWC_OTG_BASE + 0x960) 375 #define DIEPINT3 (DWC_OTG_BASE + 0x968) 376 #define DIEPTSIZ3 (DWC_OTG_BASE + 0x970) 377 #define DIEPDMA3 (DWC_OTG_BASE + 0x974) 378 #define DIEPCTL4 (DWC_OTG_BASE + 0x980) 379 #define DIEPINT4 (DWC_OTG_BASE + 0x988) 380 #define DIEPTSIZ4 (DWC_OTG_BASE + 0x990) 381 #define DIEPDMA4 (DWC_OTG_BASE + 0x994) 382 #define DIEPCTL5 (DWC_OTG_BASE + 0x9A0) 383 #define DIEPINT5 (DWC_OTG_BASE + 0x9A8) 384 #define DIEPTSIZ5 (DWC_OTG_BASE + 0x9B0) 385 #define DIEPDMA5 (DWC_OTG_BASE + 0x9B4) 386 #define DIEPCTL6 (DWC_OTG_BASE + 0x9C0) 387 #define DIEPINT6 (DWC_OTG_BASE + 0x9C8) 388 #define DIEPTSIZ6 (DWC_OTG_BASE + 0x9D0) 389 #define DIEPDMA6 (DWC_OTG_BASE + 0x9D4) 390 #define DIEPCTL7 (DWC_OTG_BASE + 0x9E0) 391 #define DIEPINT7 (DWC_OTG_BASE + 0x9E8) 392 #define DIEPTSIZ7 (DWC_OTG_BASE + 0x9F0) 393 #define DIEPDMA7 (DWC_OTG_BASE + 0x9F4) 394 #define DIEPCTL8 (DWC_OTG_BASE + 0xA00) 395 #define DIEPINT8 (DWC_OTG_BASE + 0xA08) 396 #define DIEPTSIZ8 (DWC_OTG_BASE + 0xA10) 397 #define DIEPDMA8 (DWC_OTG_BASE + 0xA14) 398 #define DIEPCTL9 (DWC_OTG_BASE + 0xA20) 399 #define DIEPINT9 (DWC_OTG_BASE + 0xA28) 400 #define DIEPTSIZ9 (DWC_OTG_BASE + 0xA30) 401 #define DIEPDMA9 (DWC_OTG_BASE + 0xA34) 402 #define DIEPCTL10 (DWC_OTG_BASE + 0xA40) 403 #define DIEPINT10 (DWC_OTG_BASE + 0xA48) 404 #define DIEPTSIZ10 (DWC_OTG_BASE + 0xA50) 405 #define DIEPDMA10 (DWC_OTG_BASE + 0xA54) 406 #define DIEPCTL11 (DWC_OTG_BASE + 0xA60) 407 #define DIEPINT11 (DWC_OTG_BASE + 0xA68) 408 #define DIEPTSIZ11 (DWC_OTG_BASE + 0xA70) 409 #define DIEPDMA11 (DWC_OTG_BASE + 0xA74) 410 #define DIEPCTL12 (DWC_OTG_BASE + 0xA80) 411 #define DIEPINT12 (DWC_OTG_BASE + 0xA88) 412 #define DIEPTSIZ12 (DWC_OTG_BASE + 0xA90) 413 #define DIEPDMA12 (DWC_OTG_BASE + 0xA94) 414 #define DIEPCTL13 (DWC_OTG_BASE + 0xAA0) 415 #define DIEPINT13 (DWC_OTG_BASE + 0xAA8) 416 #define DIEPTSIZ13 (DWC_OTG_BASE + 0xAB0) 417 #define DIEPDMA13 (DWC_OTG_BASE + 0xAB4) 418 #define DIEPCTL14 (DWC_OTG_BASE + 0xAC0) 419 #define DIEPINT14 (DWC_OTG_BASE + 0xAC8) 420 #define DIEPTSIZ14 (DWC_OTG_BASE + 0xAD0) 421 #define DIEPDMA14 (DWC_OTG_BASE + 0xAD4) 422 #define DIEPCTL15 (DWC_OTG_BASE + 0xAE0) 423 #define DIEPINT15 (DWC_OTG_BASE + 0xAE8) 424 #define DIEPTSIZ15 (DWC_OTG_BASE + 0xAF0) 425 #define DIEPDMA15 (DWC_OTG_BASE + 0xAF4) 426 427 /* Device Logical OUT Endpoint-Specific Registers */ 428 #define DOEPCTL(x) (DWC_OTG_BASE + 0xB00 + 0x20 * (x)) 429 #define DXEPCTL_EPENA (1 << 31) 430 #define DXEPCTL_EPDIS (1 << 30) 431 #define DXEPCTL_SETD1PID (1 << 29) 432 #define DXEPCTL_SETODDFR (1 << 29) 433 #define DXEPCTL_SETD0PID (1 << 28) 434 #define DXEPCTL_SETEVENFR (1 << 28) 435 #define DXEPCTL_SNAK (1 << 27) 436 #define DXEPCTL_CNAK (1 << 26) 437 #define DXEPCTL_NAKSTS (1 << 17) 438 #define DXEPCTL_DPID (1 << 16) 439 #define DXEPCTL_EOFRNUM (1 << 16) 440 #define DXEPCTL_USBACTEP (1 << 15) 441 #define DXEPCTL_NEXTEP_MASK (0xf << 11) 442 #define DXEPCTL_NEXTEP_SHIFT 11 443 #define DXEPCTL_NEXTEP_LIMIT 0xf 444 #define DXEPCTL_NEXTEP(_x) ((_x) << 11) 445 446 447 #define DOEPINT(x) (DWC_OTG_BASE + 0xB08 + 0x20 * (x)) 448 #define DXEPINT_INEPNAKEFF (1 << 6) 449 #define DXEPINT_BACK2BACKSETUP (1 << 6) 450 #define DXEPINT_INTKNEPMIS (1 << 5) 451 #define DXEPINT_INTKNTXFEMP (1 << 4) 452 #define DXEPINT_OUTTKNEPDIS (1 << 4) 453 #define DXEPINT_TIMEOUT (1 << 3) 454 #define DXEPINT_SETUP (1 << 3) 455 #define DXEPINT_AHBERR (1 << 2) 456 #define DXEPINT_EPDISBLD (1 << 1) 457 #define DXEPINT_XFERCOMPL (1 << 0) 458 459 #define DOEPTSIZ(x) (DWC_OTG_BASE + 0xB10 + 0x20 * (x)) 460 #define DXEPTSIZ_MC_MASK (0x3 << 29) 461 #define DXEPTSIZ_MC_SHIFT 29 462 #define DXEPTSIZ_MC_LIMIT 0x3 463 #define DXEPTSIZ_MC(_x) ((_x) << 29) 464 #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) 465 #define DXEPTSIZ_PKTCNT_SHIFT 19 466 #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff 467 #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) 468 #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) 469 #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) 470 #define DXEPTSIZ_XFERSIZE_SHIFT 0 471 #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff 472 #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) 473 #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) 474 475 #define DOEPDMA(x) (DWC_OTG_BASE + 0xB14 + 0x20 * (x)) 476 #define DOEPCTL0 (DWC_OTG_BASE + 0xB00) 477 #define DOEPINT0 (DWC_OTG_BASE + 0xB08) 478 #define DOEPTSIZ0 (DWC_OTG_BASE + 0xB10) 479 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) 480 #define DOEPTSIZ0_SUPCNT_SHIFT 29 481 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3 482 #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) 483 #define DOEPTSIZ0_PKTCNT (1 << 19) 484 #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 485 #define DOEPTSIZ0_XFERSIZE_SHIFT 0 486 487 #define DOEPDMA0 (DWC_OTG_BASE + 0xB14) 488 #define DOEPCTL1 (DWC_OTG_BASE + 0xB20) 489 #define DOEPINT1 (DWC_OTG_BASE + 0xB28) 490 #define DOEPTSIZ1 (DWC_OTG_BASE + 0xB30) 491 #define DOEPDMA1 (DWC_OTG_BASE + 0xB34) 492 #define DOEPCTL2 (DWC_OTG_BASE + 0xB40) 493 #define DOEPINT2 (DWC_OTG_BASE + 0xB48) 494 #define DOEPTSIZ2 (DWC_OTG_BASE + 0xB50) 495 #define DOEPDMA2 (DWC_OTG_BASE + 0xB54) 496 #define DOEPCTL3 (DWC_OTG_BASE + 0xB60) 497 #define DOEPINT3 (DWC_OTG_BASE + 0xB68) 498 #define DOEPTSIZ3 (DWC_OTG_BASE + 0xB70) 499 #define DOEPDMA3 (DWC_OTG_BASE + 0xB74) 500 #define DOEPCTL4 (DWC_OTG_BASE + 0xB80) 501 #define DOEPINT4 (DWC_OTG_BASE + 0xB88) 502 #define DOEPTSIZ4 (DWC_OTG_BASE + 0xB90) 503 #define DOEPDMA4 (DWC_OTG_BASE + 0xB94) 504 #define DOEPCTL5 (DWC_OTG_BASE + 0xBA0) 505 #define DOEPINT5 (DWC_OTG_BASE + 0xBA8) 506 #define DOEPTSIZ5 (DWC_OTG_BASE + 0xBB0) 507 #define DOEPDMA5 (DWC_OTG_BASE + 0xBB4) 508 #define DOEPCTL6 (DWC_OTG_BASE + 0xBC0) 509 #define DOEPINT6 (DWC_OTG_BASE + 0xBC8) 510 #define DOEPTSIZ6 (DWC_OTG_BASE + 0xBD0) 511 #define DOEPDMA6 (DWC_OTG_BASE + 0xBD4) 512 #define DOEPCTL7 (DWC_OTG_BASE + 0xBE0) 513 #define DOEPINT7 (DWC_OTG_BASE + 0xBE8) 514 #define DOEPTSIZ7 (DWC_OTG_BASE + 0xBF0) 515 #define DOEPDMA7 (DWC_OTG_BASE + 0xBF4) 516 #define DOEPCTL8 (DWC_OTG_BASE + 0xC00) 517 #define DOEPINT8 (DWC_OTG_BASE + 0xC08) 518 #define DOEPTSIZ8 (DWC_OTG_BASE + 0xC10) 519 #define DOEPDMA8 (DWC_OTG_BASE + 0xC14) 520 #define DOEPCTL9 (DWC_OTG_BASE + 0xC20) 521 #define DOEPINT9 (DWC_OTG_BASE + 0xC28) 522 #define DOEPTSIZ9 (DWC_OTG_BASE + 0xC30) 523 #define DOEPDMA9 (DWC_OTG_BASE + 0xC34) 524 #define DOEPCTL10 (DWC_OTG_BASE + 0xC40) 525 #define DOEPINT10 (DWC_OTG_BASE + 0xC48) 526 #define DOEPTSIZ10 (DWC_OTG_BASE + 0xC50) 527 #define DOEPDMA10 (DWC_OTG_BASE + 0xC54) 528 #define DOEPCTL11 (DWC_OTG_BASE + 0xC60) 529 #define DOEPINT11 (DWC_OTG_BASE + 0xC68) 530 #define DOEPTSIZ11 (DWC_OTG_BASE + 0xC70) 531 #define DOEPDMA11 (DWC_OTG_BASE + 0xC74) 532 #define DOEPCTL12 (DWC_OTG_BASE + 0xC80) 533 #define DOEPINT12 (DWC_OTG_BASE + 0xC88) 534 #define DOEPTSIZ12 (DWC_OTG_BASE + 0xC90) 535 #define DOEPDMA12 (DWC_OTG_BASE + 0xC94) 536 #define DOEPCTL13 (DWC_OTG_BASE + 0xCA0) 537 #define DOEPINT13 (DWC_OTG_BASE + 0xCA8) 538 #define DOEPTSIZ13 (DWC_OTG_BASE + 0xCB0) 539 #define DOEPDMA13 (DWC_OTG_BASE + 0xCB4) 540 #define DOEPCTL14 (DWC_OTG_BASE + 0xCC0) 541 #define DOEPINT14 (DWC_OTG_BASE + 0xCC8) 542 #define DOEPTSIZ14 (DWC_OTG_BASE + 0xCD0) 543 #define DOEPDMA14 (DWC_OTG_BASE + 0xCD4) 544 #define DOEPCTL15 (DWC_OTG_BASE + 0xCE0) 545 #define DOEPINT15 (DWC_OTG_BASE + 0xCE8) 546 #define DOEPTSIZ15 (DWC_OTG_BASE + 0xCF0) 547 #define DOEPDMA15 (DWC_OTG_BASE + 0xCF4) 548 549 /* Power and Clock Gating Register */ 550 #define PCGCCTL (DWC_OTG_BASE + 0xE00) 551 552 #define EP0FIFO (DWC_OTG_BASE + 0x1000) 553 554 #define PERI_CTRL16_PICOPHY_SIDDQ_BIT (1<<0) 555 #define PERI_CTRL16_PICOPHY_TXPREEMPHASISTUNE (1<<31) 556 #define PERI_CTRL15_HSICPHY_SIDDQ_BIT (1<<16) 557 #define PERI_CTRL14_NANOPHY_SIDDQ_BIT (1<<0) 558 #define PERI_CTRL0_USB2DVC_NANOPHY_BIT (1<<7) 559 #define NANOPHY_DMPULLDOWN (1 << 6) /* bit[6]nanophy_dmpulldown1'b0 */ 560 #define NANOPHY_DPPULLDOWN (1 << 5) /* bit[5]nanophy_dppulldown1'b0 */ 561 562 #define EN_LDO4_INT (1 << 4) 563 #define EN_LDO8_INT (1 << 4) 564 565 /* SCPEREN1/DIS1 */ 566 #define GT_CLK_USBHSICPHY480 (1<<26) 567 #define GT_CLK_USBHSICPHY (1<<25) 568 #define GT_CLK_USBPICOPHY (1<<24) 569 #define GT_CLK_USBNANOPHY (1<<23) 570 /* SCPEREN3/DIS3 */ 571 #define GT_CLK_USB2HST (1<<18) 572 #define GT_CLK_USB2DVC (1<<17) 573 /* SCPERRSTEN3 */ 574 #define IP_RST_PICOPHY_POR (1<<31) 575 #define IP_RST_HSICPHY_POR (1<<30) 576 #define IP_RST_NANOPHY_POR (1<<29) 577 #define IP_RST_USB2DVC_PHY (1<<28) 578 #define IP_RST_USB2H_UTMI1 (1<<21) 579 #define IP_RST_USB2H_UTMI0 (1<<20) 580 #define IP_RST_USB2H_PHY (1<<19) 581 #define IP_RST_USB2HST (1<<18) 582 #define IP_RST_USB2DVC (1<<17) 583 /* SCPERRSTEN1 */ 584 #define IP_RST_HSICPHY (1<<25) 585 #define IP_RST_PICOPHY (1<<24) 586 #define IP_RST_NANOPHY (1<<23) 587 588 /* 589 * USB directions 590 * 591 * This bit flag is used in endpoint descriptors' bEndpointAddress field. 592 * It's also one of three fields in control requests bRequestType. 593 */ 594 #define USB_DIR_OUT 0 /* to device */ 595 #define USB_DIR_IN 0x80 /* to host */ 596 597 /* 598 * Descriptor types ... USB 2.0 spec table 9.5 599 */ 600 #define USB_DT_DEVICE 0x01 601 #define USB_DT_CONFIG 0x02 602 #define USB_DT_STRING 0x03 603 #define USB_DT_INTERFACE 0x04 604 #define USB_DT_ENDPOINT 0x05 605 #define USB_DT_DEVICE_QUALIFIER 0x06 606 #define USB_DT_OTHER_SPEED_CONFIG 0x07 607 #define USB_DT_INTERFACE_POWER 0x08 608 /* these are from a minor usb 2.0 revision (ECN) */ 609 #define USB_DT_OTG 0x09 610 #define USB_DT_DEBUG 0x0a 611 #define USB_DT_INTERFACE_ASSOCIATION 0x0b 612 /* these are from the Wireless USB spec */ 613 #define USB_DT_SECURITY 0x0c 614 #define USB_DT_KEY 0x0d 615 #define USB_DT_ENCRYPTION_TYPE 0x0e 616 #define USB_DT_BOS 0x0f 617 #define USB_DT_DEVICE_CAPABILITY 0x10 618 #define USB_DT_WIRELESS_ENDPOINT_COMP 0x11 619 #define USB_DT_WIRE_ADAPTER 0x21 620 #define USB_DT_RPIPE 0x22 621 #define USB_DT_CS_RADIO_CONTROL 0x23 622 623 /* 624 * USB recipients, the third of three bRequestType fields 625 */ 626 #define USB_RECIP_MASK 0x1f 627 #define USB_RECIP_DEVICE 0x00 628 #define USB_RECIP_INTERFACE 0x01 629 #define USB_RECIP_ENDPOINT 0x02 630 #define USB_RECIP_OTHER 0x03 631 632 /* IN/OUT will STALL */ 633 #define USB_ENDPOINT_HALT 0 634 635 /* 636 * Endpoints 637 */ 638 #define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ 639 #define USB_ENDPOINT_DIR_MASK 0x80 640 641 #define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ 642 #define USB_ENDPOINT_XFER_CONTROL 0 643 #define USB_ENDPOINT_XFER_ISOC 1 644 #define USB_ENDPOINT_XFER_BULK 2 645 #define USB_ENDPOINT_XFER_INT 3 646 #define USB_ENDPOINT_MAX_ADJUSTABLE 0x80 647 648 /* 649 * Standard requests, for the bRequest field of a SETUP packet. 650 * 651 * These are qualified by the bRequestType field, so that for example 652 * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved 653 * by a GET_STATUS request. 654 */ 655 #define USB_REQ_GET_STATUS 0x00 656 #define USB_REQ_CLEAR_FEATURE 0x01 657 #define USB_REQ_SET_FEATURE 0x03 658 #define USB_REQ_SET_ADDRESS 0x05 659 #define USB_REQ_GET_DESCRIPTOR 0x06 660 #define USB_REQ_SET_DESCRIPTOR 0x07 661 #define USB_REQ_GET_CONFIGURATION 0x08 662 #define USB_REQ_SET_CONFIGURATION 0x09 663 #define USB_REQ_GET_INTERFACE 0x0A 664 #define USB_REQ_SET_INTERFACE 0x0B 665 #define USB_REQ_SYNCH_FRAME 0x0C 666 667 /* USB_DT_DEVICE: Device descriptor */ 668 struct usb_device_descriptor { 669 unsigned char bLength; 670 unsigned char bDescriptorType; 671 672 unsigned short bcdUSB; 673 unsigned char bDeviceClass; 674 unsigned char bDeviceSubClass; 675 unsigned char bDeviceProtocol; 676 unsigned char bMaxPacketSize0; 677 unsigned short idVendor; 678 unsigned short idProduct; 679 unsigned short bcdDevice; 680 unsigned char iManufacturer; 681 unsigned char iProduct; 682 unsigned char iSerialNumber; 683 unsigned char bNumConfigurations; 684 } __attribute__ ((packed)); 685 686 #define USB_DT_DEVICE_SIZE 18 687 688 /* 689 * Device and/or Interface Class codes 690 * as found in bDeviceClass or bInterfaceClass 691 * and defined by www.usb.org documents 692 */ 693 #define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ 694 #define USB_CLASS_AUDIO 1 695 #define USB_CLASS_COMM 2 696 #define USB_CLASS_HID 3 697 #define USB_CLASS_PHYSICAL 5 698 #define USB_CLASS_STILL_IMAGE 6 699 #define USB_CLASS_PRINTER 7 700 #define USB_CLASS_MASS_STORAGE 8 701 #define USB_CLASS_HUB 9 702 #define USB_CLASS_CDC_DATA 0x0a 703 #define USB_CLASS_CSCID 0x0b /* chip+ smart card */ 704 #define USB_CLASS_CONTENT_SEC 0x0d /* content security */ 705 #define USB_CLASS_VIDEO 0x0e 706 #define USB_CLASS_WIRELESS_CONTROLLER 0xe0 707 #define USB_CLASS_MISC 0xef 708 #define USB_CLASS_APP_SPEC 0xfe 709 #define USB_CLASS_VENDOR_SPEC 0xff 710 711 /*-------------------------------------------------------------------------*/ 712 713 /* USB_DT_CONFIG: Configuration descriptor information. 714 * 715 * USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the 716 * descriptor type is different. Highspeed-capable devices can look 717 * different depending on what speed they're currently running. Only 718 * devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG 719 * descriptors. 720 */ 721 struct usb_config_descriptor { 722 unsigned char bLength; 723 unsigned char bDescriptorType; 724 725 unsigned short wTotalLength; 726 unsigned char bNumInterfaces; 727 unsigned char bConfigurationValue; 728 unsigned char iConfiguration; 729 unsigned char bmAttributes; 730 unsigned char bMaxPower; 731 } __attribute__((packed)); 732 733 #define USB_DT_CONFIG_SIZE 9 734 735 /* from config descriptor bmAttributes */ 736 #define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */ 737 #define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */ 738 #define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */ 739 #define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */ 740 741 /*-------------------------------------------------------------------------*/ 742 743 /* USB_DT_STRING: String descriptor */ 744 struct usb_string_descriptor { 745 unsigned char bLength; 746 unsigned char bDescriptorType; 747 748 unsigned short wString[16]; /* UTF-16LE encoded */ 749 } __attribute__((packed)); 750 751 /*-------------------------------------------------------------------------*/ 752 /* USB_DT_INTERFACE: Interface descriptor */ 753 struct usb_interface_descriptor { 754 unsigned char bLength; 755 unsigned char bDescriptorType; 756 757 unsigned char bInterfaceNumber; 758 unsigned char bAlternateSetting; 759 unsigned char bNumEndpoints; 760 unsigned char bInterfaceClass; 761 unsigned char bInterfaceSubClass; 762 unsigned char bInterfaceProtocol; 763 unsigned char iInterface; 764 }; 765 766 #define USB_DT_INTERFACE_SIZE 9 767 768 /*-------------------------------------------------------------------------*/ 769 770 /* USB_DT_ENDPOINT: Endpoint descriptor */ 771 struct usb_endpoint_descriptor { 772 unsigned char bLength; 773 unsigned char bDescriptorType; 774 775 unsigned char bEndpointAddress; 776 unsigned char bmAttributes; 777 unsigned short wMaxPacketSize; 778 unsigned char bInterval; 779 } __attribute__ ((packed)); 780 781 #define USB_DT_ENDPOINT_SIZE 7 782 #define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ 783 784 extern int usb_need_reset; 785 786 /** 787 * This union represents the bit fields in the DMA Descriptor 788 * status quadlet. Read the quadlet into the <i>d32</i> member then 789 * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and 790 * <i>b_iso_in</i> elements. 791 */ 792 typedef union dev_dma_desc_sts { 793 /** raw register data */ 794 unsigned int d32; 795 /** quadlet bits */ 796 struct { 797 /** Received number of bytes */ 798 unsigned bytes:16; 799 /** NAK bit - only for OUT EPs */ 800 unsigned nak:1; 801 unsigned reserved17_22:6; 802 /** Multiple Transfer - only for OUT EPs */ 803 unsigned mtrf:1; 804 /** Setup Packet received - only for OUT EPs */ 805 unsigned sr:1; 806 /** Interrupt On Complete */ 807 unsigned ioc:1; 808 /** Short Packet */ 809 unsigned sp:1; 810 /** Last */ 811 unsigned l:1; 812 /** Receive Status */ 813 unsigned sts:2; 814 /** Buffer Status */ 815 unsigned bs:2; 816 } b; 817 818 //#ifdef DWC_EN_ISOC 819 /** iso out quadlet bits */ 820 struct { 821 /** Received number of bytes */ 822 unsigned rxbytes:11; 823 824 unsigned reserved11:1; 825 /** Frame Number */ 826 unsigned framenum:11; 827 /** Received ISO Data PID */ 828 unsigned pid:2; 829 /** Interrupt On Complete */ 830 unsigned ioc:1; 831 /** Short Packet */ 832 unsigned sp:1; 833 /** Last */ 834 unsigned l:1; 835 /** Receive Status */ 836 unsigned rxsts:2; 837 /** Buffer Status */ 838 unsigned bs:2; 839 } b_iso_out; 840 841 /** iso in quadlet bits */ 842 struct { 843 /** Transmited number of bytes */ 844 unsigned txbytes:12; 845 /** Frame Number */ 846 unsigned framenum:11; 847 /** Transmited ISO Data PID */ 848 unsigned pid:2; 849 /** Interrupt On Complete */ 850 unsigned ioc:1; 851 /** Short Packet */ 852 unsigned sp:1; 853 /** Last */ 854 unsigned l:1; 855 /** Transmit Status */ 856 unsigned txsts:2; 857 /** Buffer Status */ 858 unsigned bs:2; 859 } b_iso_in; 860 //#endif /* DWC_EN_ISOC */ 861 } dev_dma_desc_sts_t; 862 863 /** 864 * DMA Descriptor structure 865 * 866 * DMA Descriptor structure contains two quadlets: 867 * Status quadlet and Data buffer pointer. 868 */ 869 typedef struct dwc_otg_dev_dma_desc { 870 /** DMA Descriptor status quadlet */ 871 dev_dma_desc_sts_t status; 872 /** DMA Descriptor data buffer pointer */ 873 unsigned int buf; 874 } dwc_otg_dev_dma_desc_t; 875 876 extern void usb_reinit(void); 877 878 #endif /* __DWC_USB_H__*/ 879
