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    Searched refs:GPR64RegClass (Results 1 - 19 of 19) sorted by null

  /external/llvm/lib/Target/Mips/
MipsOptionRecord.h 47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
65 const MCRegisterClass *GPR64RegClass;
MipsMachineFunction.cpp 51 ? &Mips::GPR64RegClass
60 ? &Mips::GPR64RegClass
MipsSERegisterInfo.cpp 60 return &Mips::GPR64RegClass;
180 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsSubtarget.cpp 139 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
MipsSEInstrInfo.cpp 145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146 if (Mips::GPR64RegClass.contains(SrcReg))
155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
194 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
267 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
477 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsRegisterInfo.cpp 57 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MipsSEFrameLowering.cpp 396 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
696 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
    [all...]
MipsSEISelDAGToDAG.cpp 144 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
    [all...]
MipsISelLowering.cpp     [all...]
MipsSEISelLowering.cpp 45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
    [all...]
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsOptionRecord.cpp 80 GPR64RegClass->contains(CurrentSubReg))
  /external/llvm/lib/Target/AArch64/
AArch64CleanupLocalDynamicTLSPass.cpp 120 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
AArch64FrameLowering.cpp 264 for (unsigned Reg : AArch64::GPR64RegClass) {
    [all...]
AArch64FastISel.cpp 343 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
377 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
435 ResultReg = createResultReg(&AArch64::GPR64RegClass);
    [all...]
AArch64RegisterInfo.cpp 173 return &AArch64::GPR64RegClass;
179 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
402 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
AArch64AdvSIMDScalarPass.cpp 117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
118 return AArch64::GPR64RegClass.contains(Reg);
AArch64InstrInfo.cpp 494 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
495 RC = &AArch64::GPR64RegClass;
    [all...]
AArch64LoadStoreOptimizer.cpp     [all...]
AArch64ISelLowering.cpp     [all...]

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