| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 85 case HexagonII::HSIG_None:
88 case HexagonII::HSIG_L1:
89 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
90 case HexagonII::HSIG_L2:
91 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
92 Gb == HexagonII::HSIG_A);
93 case HexagonII::HSIG_S1:
94 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 |
[all...] |
| HexagonShuffler.cpp | 99 (*TUL)[HexagonII::TypeCVI_VA] =
101 (*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2);
102 (*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1);
103 (*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2);
104 (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
105 (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
106 (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
107 (*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1);
108 (*TUL)[HexagonII::TypeCVI_VM_LD] =
110 (*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0)
[all...] |
| HexagonMCInstrInfo.cpp | 137 HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR)
168 HexagonII::MemAccessSize
172 return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
173 HexagonII::MemAccesSizeMask));
179 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
186 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
252 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
[all...] |
| HexagonMCCompound.cpp | 81 // enum HexagonII::CompoundGroup
88 return HexagonII::HCG_None;
106 return HexagonII::HCG_A;
120 return HexagonII::HCG_A;
130 return HexagonII::HCG_A;
140 return HexagonII::HCG_A;
150 return HexagonII::HCG_A;
162 return HexagonII::HCG_B;
170 return HexagonII::HCG_C;
174 return HexagonII::HCG_None
[all...] |
| HexagonMCCodeEmitter.cpp | 48 return HexagonII::INST_PARSE_LOOP_END;
55 return HexagonII::INST_PARSE_LOOP_END;
60 return HexagonII::INST_PARSE_DUPLEX;
63 return HexagonII::INST_PARSE_PACKET_END;
64 return HexagonII::INST_PARSE_NOT_END;
126 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
203 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
300 if (insnType == HexagonII::TypePREFIX) {
389 case HexagonII::MemAccessSize::ByteAccess:
391 case HexagonII::MemAccessSize::HalfWordAccess
[all...] |
| HexagonAsmBackend.cpp | 526 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
528 HexagonII::TypeCOMPOUND &&
530 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
532 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
|
| HexagonBaseInfo.h | 26 /// HexagonII - This namespace holds all of the target specific flags that
29 namespace HexagonII {
301 } // End namespace HexagonII.
|
| HexagonMCChecker.cpp | 152 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD)
157 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD)
219 NewUses[N] = NewSense::Jmp(llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV);
469 if(llvm::HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) == HexagonII::TypeCVI_HIST) {
|
| HexagonMCInstrInfo.h | 28 namespace HexagonII {
93 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 46 case HexagonII::MO_PCREL:
49 case HexagonII::MO_GOT:
52 case HexagonII::MO_LO16:
55 case HexagonII::MO_HI16:
58 case HexagonII::MO_GPREL:
61 case HexagonII::MO_GDGOT:
64 case HexagonII::MO_GDPLT:
67 case HexagonII::MO_IE:
70 case HexagonII::MO_IEGOT:
73 case HexagonII::MO_TPREL
[all...] |
| HexagonInstrInfo.cpp | 204 case HexagonII::HSIG_None:
207 case HexagonII::HSIG_L1:
208 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
209 case HexagonII::HSIG_L2:
210 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
211 Gb == HexagonII::HSIG_A);
212 case HexagonII::HSIG_S1:
213 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 |
[all...] |
| HexagonOptAddrMode.cpp | 119 if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
122 else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
174 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
316 if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
326 } else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
373 if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
382 } else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
415 if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) {
445 assert(HII->getAddrMode(UseMI) == HexagonII::BaseImmOffset);
|
| HexagonBranchRelaxation.cpp | 205 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
|
| HexagonInstrInfo.h | 381 HexagonII::CompoundGroup
393 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
|
| HexagonRDFOpt.cpp | 207 if (HII.getAddrMode(MI) != HexagonII::PostInc)
|
| HexagonISelLowering.cpp | [all...] |
| HexagonISelDAGToDAG.cpp | 417 unsigned SizeBits = (F >> HexagonII::MemAccessSizePos) &
418 HexagonII::MemAccesSizeMask;
[all...] |
| HexagonCopyToCombine.cpp | 157 if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
|
| HexagonFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 200 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
201 HexagonII::INST_PARSE_LOOP_END) {
211 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
212 HexagonII::INST_PARSE_DUPLEX) {
221 IClassLow = HexagonII::HSIG_L1;
222 IClassHigh = HexagonII::HSIG_L1;
225 IClassLow = HexagonII::HSIG_L2;
226 IClassHigh = HexagonII::HSIG_L1;
229 IClassLow = HexagonII::HSIG_L2;
230 IClassHigh = HexagonII::HSIG_L2
[all...] |
