| /external/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 90 bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
92 bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
94 const MachineOperand &ImmOp, unsigned ImmOpNum);
304 bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
323 MIB.addOperand(ImmOp);
331 const GlobalValue *GV = ImmOp.getGlobal();
332 int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm();
334 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
348 MIB.addOperand(ImmOp);
362 bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 250 MCOperand ImmOp = MI.getOperand(ImmOpIndex);
251 if (ImmOp.isFPImm()) {
252 Value.f = ImmOp.getFPImm();
254 assert(ImmOp.isImm());
255 Value.i = ImmOp.getImm();
|
| /external/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.cpp | 385 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
392 ImmOp.ChangeToImmediate(ImmedOffset);
409 ImmOp.ChangeToImmediate(0);
413 ImmOp.ChangeToImmediate(ImmedOffset);
|
| Thumb2InstrInfo.cpp | 595 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
611 ImmOp.ChangeToImmediate(ImmedOffset);
629 ImmOp.ChangeToImmediate(ImmedOffset);
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 282 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
283 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII);
|
| SIInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 521 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
537 ImmOp.ChangeToImmediate(ImmedOffset);
555 ImmOp.ChangeToImmediate(ImmedOffset);
|
| Thumb1RegisterInfo.cpp | 493 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
500 ImmOp.ChangeToImmediate(ImmedOffset);
517 ImmOp.ChangeToImmediate(0);
521 ImmOp.ChangeToImmediate(ImmedOffset);
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 48 struct ImmOp {
65 struct ImmOp Imm;
|
| X86AsmParser.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86MCInstLower.cpp | 232 unsigned ImmOp = Inst.getNumOperands() - 1;
233 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
244 MCOperand Saved = Inst.getOperand(ImmOp);
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 253 unsigned ImmOp = Inst.getNumOperands() - 1;
255 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
266 MCOperand Saved = Inst.getOperand(ImmOp);
[all...] |
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| LanaiAsmParser.cpp | 109 struct ImmOp {
123 struct ImmOp Imm;
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 206 struct ImmOp {
219 struct ImmOp Imm;
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 611 struct ImmOp {
627 struct ImmOp Imm;
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 193 struct ImmOp {
255 struct ImmOp Imm;
[all...] |
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 138 struct ImmOp {
155 ImmOp Imm;
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 504 struct ImmOp {
575 struct ImmOp Imm;
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 335 struct ImmOp {
350 struct ImmOp Imm;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | [all...] |
