| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 386 const MachineInstr &MI1,
388 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
570 MachineInstr *MI1 = nullptr;
573 MI1 = MRI.getUniqueVRegDef(Op1.getReg());
578 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
585 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
591 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
593 std::swap(MI1, MI2);
599 return MI1->getOpcode() == AssocOpcode &
[all...] |
| MachineInstr.cpp | 905 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
906 auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.h | 97 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
|
| HexagonVLIWPacketizer.cpp | 844 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
848 if (getPredicateSense(MI1, HII) == PK_Unknown ||
853 SUnit *SU = MIToSUnit[&MI1];
901 unsigned PReg1 = getPredicatedRegister(MI1, HII);
906 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
907 HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2);
[all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetInstrInfo.h | 242 const MachineInstr *MI1,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 251 MachineInstr &MI1 = *MII;
252 dbgs() << " " << MI1;
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| ARMBaseInstrInfo.h | 143 const MachineInstr *MI1,
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| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 246 /// \brief Returns the difference between addresses' displacements of \p MI1
249 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
362 // instructions \p MI1 and \p MI2. The numbers of the first memory operands are
364 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1,
367 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp);
|
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 319 MachineInstr &MI1 = *MII;
320 dbgs() << " " << MI1;
|
| ARMBaseInstrInfo.h | 205 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
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| ARMBaseInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| TargetInstrInfoImpl.cpp | 214 const MachineInstr *MI1,
216 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 440 const MachineInstr &MI1,
[all...] |
