| /toolchain/binutils/binutils-2.25/opcodes/ |
| cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
294 #define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
298 {NAME, 3, (OPC2+3), 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \
304 {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \
310 {NAME, 3, (OPC2+1), 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \
312 {NAME, 3, (OPC2+2), 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}}
319 #define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4)
[all...] |
| crx-opc.c | 87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
93 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}}
157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \
165 {NAME, 2, ((0x300+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
168 {NAME, 3, ((0x310+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \
356 {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP | REVERSE_MATCH, \
359 {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \
362 {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \
379 #define ST_REG_INST(NAME, OPC1, OPC2, DISP)
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeSPARC_common.c | 118 #define OPC2(opcode) ((opcode) << 22)
147 #define NOP (OPC1(0x0) | OPC2(0x04))
153 #define SETHI (OPC1(0x0) | OPC2(0x04))
172 #define BICC (OPC1(0x0) | OPC2(0x2))
173 #define FBFCC (OPC1(0x0) | OPC2(0x6))
[all...] |
