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Searched
refs:OPC3
(Results
1 - 2
of
2
) sorted by null
/external/pcre/dist2/src/sljit/
sljitNativeSPARC_common.c
119
#define
OPC3
(opcode) ((opcode) << 19)
120
#define SET_FLAGS
OPC3
(0x10)
122
#define ADD (OPC1(0x2) |
OPC3
(0x00))
123
#define ADDC (OPC1(0x2) |
OPC3
(0x08))
124
#define AND (OPC1(0x2) |
OPC3
(0x01))
125
#define ANDN (OPC1(0x2) |
OPC3
(0x05))
127
#define FABSS (OPC1(0x2) |
OPC3
(0x34) | DOP(0x09))
128
#define FADDD (OPC1(0x2) |
OPC3
(0x34) | DOP(0x42))
129
#define FADDS (OPC1(0x2) |
OPC3
(0x34) | DOP(0x41))
130
#define FCMPD (OPC1(0x2) |
OPC3
(0x35) | DOP(0x52)
[
all
...]
/toolchain/binutils/binutils-2.25/opcodes/
cr16-opc.c
294
#define CSTBIT_INST_B(NAME, OP, OPC1, OPC2,
OPC3
, OPC4) \
296
{NAME, 2, (
OPC3
+1), 23, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
306
{NAME, 1,
OPC3
-2, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \
308
{NAME, 2,
OPC3
, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \
319
#define CSTBIT_INST_W(NAME, OP, OPC1, OPC2,
OPC3
, OPC4) \
325
{NAME, 2,
OPC3
, 25, CSTBIT_INS, {{OP,20}, {rindex8_abs20,0}}}, \
350
#define LD_REG_INST(NAME, OPC1, OPC2,
OPC3
, OPC4, OPC5, OP_S, OP_D) \
352
{NAME, 2,
OPC3
, 24, LD_STOR_INS, {{abs20,0}, {OP_D,20}}}, \
381
#define ST_REG_INST(NAME, OPC1, OPC2,
OPC3
, OPC4, OPC5, OP_D, OP_S) \
383
{NAME, 2,
OPC3
, 24, LD_STOR_INS, {{OP_S,20}, {abs20,0}}},
[
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...]
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