| /external/swiftshader/third_party/LLVM/include/llvm/Analysis/ |
| ConstantsScanner.h | 28 unsigned OpIdx; // Operand index
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() &&
35 return isa<Constant>(InstI->getOperand(OpIdx));
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) {
47 : InstI(inst_end(F)), OpIdx(0) {
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperands && !isAtConstant())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 186 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
223 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
224 const MachineOperand &MO = MI.getOperand(OpIdx);
243 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
273 Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank);
288 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx)
[all...] |
| RegBankSelect.cpp | 365 for (unsigned OpIdx = 0, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx;
366 ++OpIdx) {
367 const MachineOperand &MO = MI.getOperand(OpIdx);
373 DEBUG(dbgs() << "Opd" << OpIdx);
375 InstrMapping.getOperandMapping(OpIdx);
384 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this,
391 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert));
482 unsigned OpIdx = RepairPt.getOpIdx();
483 MachineOperand &MO = MI.getOperand(OpIdx);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 101 unsigned OpIdx);
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
239 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
241 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
269 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
271 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
273 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
275 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
[all...] |
| ARMExpandPseudoInsts.cpp | 419 unsigned OpIdx = 0;
421 bool DstIsDead = MI.getOperand(OpIdx).isDead();
422 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
433 MIB.addOperand(MI.getOperand(OpIdx++));
436 MIB.addOperand(MI.getOperand(OpIdx++));
437 MIB.addOperand(MI.getOperand(OpIdx++));
440 MIB.addOperand(MI.getOperand(OpIdx++));
447 SrcOpIdx = OpIdx++;
450 MIB.addOperand(MI.getOperand(OpIdx++));
451 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ProcessImplicitDefs.h | 34 unsigned OpIdx,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AddressTypePromotion.cpp | 208 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) {
209 return !(isa<SelectInst>(Inst) && OpIdx == 0);
311 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx;
312 ++OpIdx) {
313 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n');
314 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() ||
315 !shouldSExtOperand(Inst, OpIdx)) {
320 Value *Opnd = Inst->getOperand(OpIdx);
323 Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType()
[all...] |
| AArch64PromoteConstant.cpp | 245 /// Check if the given use (Instruction + OpIdx) of Cst should be converted into
251 unsigned OpIdx) {
254 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2)
258 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0)
262 if (isa<const InsertValueInst>(Instr) && OpIdx > 1)
265 if (isa<const AllocaInst>(Instr) && OpIdx > 0)
269 if (isa<const LoadInst>(Instr) && OpIdx > 0)
273 if (isa<const StoreInst>(Instr) && OpIdx > 1)
277 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0)
439 DEBUG(dbgs() << "Considered use, opidx " << OpNo << ":\n")
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeEmitterGen.cpp | 86 unsigned OpIdx;
87 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
89 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
90 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
113 OpIdx = NumberedOp++;
116 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
127 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
133 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
192 unsigned OpIdx;
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeEmitterGen.cpp | 107 unsigned OpIdx;
108 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
110 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
111 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
118 OpIdx = NumberedOp++;
121 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
132 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
139 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
|
| CodeGenInstruction.cpp | 135 unsigned OpIdx;
136 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
142 /// given name. If so, return true and set OpIdx to the index of the
144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
148 OpIdx = i;
171 unsigned OpIdx = getOperandNamed(OpName);
175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
181 return std::make_pair(OpIdx, 0U);
185 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo
[all...] |
| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegisterBankInfo.h | 164 /// Set the operand mapping for the \p OpIdx-th operand.
168 void setOperandMapping(unsigned OpIdx, unsigned MaskSize,
194 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
195 /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
211 /// values for the \p OpIdx-th operand.
215 /// \pre getMI().getOperand(OpIdx).isReg()
217 getVRegsMem(unsigned OpIdx);
244 /// OpIdx-th operand.
248 /// \pre getMI().getOperand(OpIdx).isReg()
250 /// \post All the partial mapping of the \p OpIdx-th operand have bee
[all...] |
| RegBankSelect.h | 320 unsigned OpIdx;
332 /// Create a repairing placement for the \p OpIdx-th operand of
337 RepairingPlacement(MachineInstr &MI, unsigned OpIdx,
344 unsigned getOpIdx() const { return OpIdx; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 403 unsigned OpIdx = 0;
405 bool DstIsDead = MI.getOperand(OpIdx).isDead();
406 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
418 MIB.addOperand(MI.getOperand(OpIdx++));
421 MIB.addOperand(MI.getOperand(OpIdx++));
422 MIB.addOperand(MI.getOperand(OpIdx++));
425 MIB.addOperand(MI.getOperand(OpIdx++));
432 SrcOpIdx = OpIdx++;
435 MIB.addOperand(MI.getOperand(OpIdx++));
436 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.h | 39 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | [all...] |
| ExecutionDepsFix.cpp | 206 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
478 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
480 unsigned reg = MI->getOperand(OpIdx).getReg();
566 unsigned OpIdx = UndefReads.back().second;
573 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
574 TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI);
581 OpIdx = UndefReads.back().second;
|
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 170 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
171 ++OpIdx)
172 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
|
| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| LanaiInstPrinter.h | 49 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ProcessImplicitDefs.cpp | 49 unsigned Reg, unsigned OpIdx,
51 switch(OpIdx) {
263 unsigned OpIdx = Ops[j];
264 RMI->RemoveOperand(OpIdx-j);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 104 unsigned OpIdx, SDep& dep) const;
|
