1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains a pass that expands pseudo instructions into target 11 // instructions to allow proper scheduling, if-conversion, and other late 12 // optimizations. This pass should be run after register allocation but before 13 // the post-regalloc scheduling pass. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #define DEBUG_TYPE "arm-pseudo" 18 #include "ARM.h" 19 #include "ARMBaseInstrInfo.h" 20 #include "ARMBaseRegisterInfo.h" 21 #include "ARMMachineFunctionInfo.h" 22 #include "ARMRegisterInfo.h" 23 #include "MCTargetDesc/ARMAddressingModes.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/Target/TargetFrameLowering.h" 28 #include "llvm/Target/TargetRegisterInfo.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 31 using namespace llvm; 32 33 static cl::opt<bool> 34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 35 cl::desc("Verify machine code after expanding ARM pseudos")); 36 37 namespace { 38 class ARMExpandPseudo : public MachineFunctionPass { 39 public: 40 static char ID; 41 ARMExpandPseudo() : MachineFunctionPass(ID) {} 42 43 const ARMBaseInstrInfo *TII; 44 const TargetRegisterInfo *TRI; 45 const ARMSubtarget *STI; 46 ARMFunctionInfo *AFI; 47 48 virtual bool runOnMachineFunction(MachineFunction &Fn); 49 50 virtual const char *getPassName() const { 51 return "ARM pseudo instruction expansion pass"; 52 } 53 54 private: 55 void TransferImpOps(MachineInstr &OldMI, 56 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 57 bool ExpandMI(MachineBasicBlock &MBB, 58 MachineBasicBlock::iterator MBBI); 59 bool ExpandMBB(MachineBasicBlock &MBB); 60 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 61 void ExpandVST(MachineBasicBlock::iterator &MBBI); 62 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 63 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 64 unsigned Opc, bool IsExt, unsigned NumRegs); 65 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 66 MachineBasicBlock::iterator &MBBI); 67 }; 68 char ARMExpandPseudo::ID = 0; 69 } 70 71 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to 72 /// the instructions created from the expansion. 73 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 74 MachineInstrBuilder &UseMI, 75 MachineInstrBuilder &DefMI) { 76 const MCInstrDesc &Desc = OldMI.getDesc(); 77 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 78 i != e; ++i) { 79 const MachineOperand &MO = OldMI.getOperand(i); 80 assert(MO.isReg() && MO.getReg()); 81 if (MO.isUse()) 82 UseMI.addOperand(MO); 83 else 84 DefMI.addOperand(MO); 85 } 86 } 87 88 namespace { 89 // Constants for register spacing in NEON load/store instructions. 90 // For quad-register load-lane and store-lane pseudo instructors, the 91 // spacing is initially assumed to be EvenDblSpc, and that is changed to 92 // OddDblSpc depending on the lane number operand. 93 enum NEONRegSpacing { 94 SingleSpc, 95 EvenDblSpc, 96 OddDblSpc 97 }; 98 99 // Entries for NEON load/store information table. The table is sorted by 100 // PseudoOpc for fast binary-search lookups. 101 struct NEONLdStTableEntry { 102 unsigned PseudoOpc; 103 unsigned RealOpc; 104 bool IsLoad; 105 bool HasWriteBack; 106 NEONRegSpacing RegSpacing; 107 unsigned char NumRegs; // D registers loaded or stored 108 unsigned char RegElts; // elements per D register; used for lane ops 109 110 // Comparison methods for binary search of the table. 111 bool operator<(const NEONLdStTableEntry &TE) const { 112 return PseudoOpc < TE.PseudoOpc; 113 } 114 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 115 return TE.PseudoOpc < PseudoOpc; 116 } 117 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 118 const NEONLdStTableEntry &TE) { 119 return PseudoOpc < TE.PseudoOpc; 120 } 121 }; 122 } 123 124 static const NEONLdStTableEntry NEONLdStTable[] = { 125 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4}, 126 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4}, 127 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2}, 128 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2}, 129 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8}, 130 { ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8}, 131 132 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 }, 133 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 }, 134 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 }, 135 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 }, 136 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 }, 137 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 }, 138 139 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, 140 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, 141 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 }, 142 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 }, 143 144 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 }, 145 { ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 }, 146 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 }, 147 { ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 }, 148 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 }, 149 { ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 }, 150 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 }, 151 { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 }, 152 153 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4}, 154 { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4}, 155 { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2}, 156 { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2}, 157 { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8}, 158 { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8}, 159 160 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 }, 161 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 }, 162 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 }, 163 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 }, 164 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 }, 165 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 }, 166 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 }, 167 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 }, 168 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 }, 169 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 }, 170 171 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 }, 172 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 }, 173 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 }, 174 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 }, 175 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 }, 176 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 }, 177 178 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 }, 179 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 }, 180 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 }, 181 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 }, 182 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 }, 183 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 }, 184 185 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4}, 186 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4}, 187 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2}, 188 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2}, 189 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8}, 190 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8}, 191 192 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 }, 193 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 }, 194 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 }, 195 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 }, 196 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 }, 197 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 }, 198 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 }, 199 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 }, 200 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 }, 201 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 }, 202 203 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 }, 204 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 }, 205 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 }, 206 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 }, 207 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 }, 208 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 }, 209 210 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 }, 211 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, OddDblSpc, 3, 4 }, 212 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 }, 213 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 }, 214 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, OddDblSpc, 3, 2 }, 215 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 }, 216 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 }, 217 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, OddDblSpc, 3, 8 }, 218 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 }, 219 220 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4}, 221 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4}, 222 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2}, 223 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2}, 224 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8}, 225 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8}, 226 227 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 }, 228 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 }, 229 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 }, 230 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 }, 231 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 }, 232 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 }, 233 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 }, 234 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 }, 235 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 }, 236 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 }, 237 238 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 }, 239 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 }, 240 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 }, 241 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 }, 242 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 }, 243 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 }, 244 245 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 }, 246 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, OddDblSpc, 4, 4 }, 247 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 }, 248 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 }, 249 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, OddDblSpc, 4, 2 }, 250 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 }, 251 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 }, 252 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, OddDblSpc, 4, 8 }, 253 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 }, 254 255 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 }, 256 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 }, 257 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 }, 258 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 }, 259 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 }, 260 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 }, 261 262 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 }, 263 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 }, 264 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 }, 265 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 }, 266 267 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 }, 268 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 }, 269 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 }, 270 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 }, 271 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 }, 272 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 }, 273 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 }, 274 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 }, 275 276 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 }, 277 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 }, 278 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 }, 279 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 }, 280 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 }, 281 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 }, 282 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4}, 283 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4}, 284 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2}, 285 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2}, 286 287 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 }, 288 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 }, 289 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 }, 290 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 }, 291 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 }, 292 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 }, 293 294 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 }, 295 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 }, 296 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 }, 297 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 }, 298 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 }, 299 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 }, 300 301 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 }, 302 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 }, 303 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 }, 304 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 }, 305 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 }, 306 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 }, 307 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4}, 308 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4}, 309 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2}, 310 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2}, 311 312 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 }, 313 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 }, 314 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 }, 315 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 }, 316 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 }, 317 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 }, 318 319 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 }, 320 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, OddDblSpc, 3, 4 }, 321 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 }, 322 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 }, 323 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, OddDblSpc, 3, 2 }, 324 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 }, 325 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 }, 326 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, OddDblSpc, 3, 8 }, 327 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 }, 328 329 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 }, 330 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 }, 331 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 }, 332 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 }, 333 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 }, 334 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 }, 335 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4}, 336 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4}, 337 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2}, 338 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2}, 339 340 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 }, 341 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 }, 342 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 }, 343 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 }, 344 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 }, 345 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 }, 346 347 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 }, 348 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, OddDblSpc, 4, 4 }, 349 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 }, 350 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 }, 351 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, OddDblSpc, 4, 2 }, 352 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 }, 353 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 }, 354 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, OddDblSpc, 4, 8 }, 355 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 } 356 }; 357 358 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 359 /// load or store pseudo instruction. 360 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 361 unsigned NumEntries = array_lengthof(NEONLdStTable); 362 363 #ifndef NDEBUG 364 // Make sure the table is sorted. 365 static bool TableChecked = false; 366 if (!TableChecked) { 367 for (unsigned i = 0; i != NumEntries-1; ++i) 368 assert(NEONLdStTable[i] < NEONLdStTable[i+1] && 369 "NEONLdStTable is not sorted!"); 370 TableChecked = true; 371 } 372 #endif 373 374 const NEONLdStTableEntry *I = 375 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); 376 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) 377 return I; 378 return NULL; 379 } 380 381 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 382 /// corresponding to the specified register spacing. Not all of the results 383 /// are necessarily valid, e.g., a Q register only has 2 D subregisters. 384 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 385 const TargetRegisterInfo *TRI, unsigned &D0, 386 unsigned &D1, unsigned &D2, unsigned &D3) { 387 if (RegSpc == SingleSpc) { 388 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 389 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 390 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 391 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 392 } else if (RegSpc == EvenDblSpc) { 393 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 394 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 395 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 396 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 397 } else { 398 assert(RegSpc == OddDblSpc && "unknown register spacing"); 399 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 400 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 401 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 402 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 403 } 404 } 405 406 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 407 /// operands to real VLD instructions with D register operands. 408 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 409 MachineInstr &MI = *MBBI; 410 MachineBasicBlock &MBB = *MI.getParent(); 411 412 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 413 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 414 NEONRegSpacing RegSpc = TableEntry->RegSpacing; 415 unsigned NumRegs = TableEntry->NumRegs; 416 417 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 418 TII->get(TableEntry->RealOpc)); 419 unsigned OpIdx = 0; 420 421 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 422 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 423 unsigned D0, D1, D2, D3; 424 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 426 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 427 if (NumRegs > 2) 428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 429 if (NumRegs > 3) 430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 431 432 if (TableEntry->HasWriteBack) 433 MIB.addOperand(MI.getOperand(OpIdx++)); 434 435 // Copy the addrmode6 operands. 436 MIB.addOperand(MI.getOperand(OpIdx++)); 437 MIB.addOperand(MI.getOperand(OpIdx++)); 438 // Copy the am6offset operand. 439 if (TableEntry->HasWriteBack) 440 MIB.addOperand(MI.getOperand(OpIdx++)); 441 442 // For an instruction writing double-spaced subregs, the pseudo instruction 443 // has an extra operand that is a use of the super-register. Record the 444 // operand index and skip over it. 445 unsigned SrcOpIdx = 0; 446 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 447 SrcOpIdx = OpIdx++; 448 449 // Copy the predicate operands. 450 MIB.addOperand(MI.getOperand(OpIdx++)); 451 MIB.addOperand(MI.getOperand(OpIdx++)); 452 453 // Copy the super-register source operand used for double-spaced subregs over 454 // to the new instruction as an implicit operand. 455 if (SrcOpIdx != 0) { 456 MachineOperand MO = MI.getOperand(SrcOpIdx); 457 MO.setImplicit(true); 458 MIB.addOperand(MO); 459 } 460 // Add an implicit def for the super-register. 461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 462 TransferImpOps(MI, MIB, MIB); 463 464 // Transfer memoperands. 465 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 466 467 MI.eraseFromParent(); 468 } 469 470 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 471 /// operands to real VST instructions with D register operands. 472 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 473 MachineInstr &MI = *MBBI; 474 MachineBasicBlock &MBB = *MI.getParent(); 475 476 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 477 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 478 NEONRegSpacing RegSpc = TableEntry->RegSpacing; 479 unsigned NumRegs = TableEntry->NumRegs; 480 481 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 482 TII->get(TableEntry->RealOpc)); 483 unsigned OpIdx = 0; 484 if (TableEntry->HasWriteBack) 485 MIB.addOperand(MI.getOperand(OpIdx++)); 486 487 // Copy the addrmode6 operands. 488 MIB.addOperand(MI.getOperand(OpIdx++)); 489 MIB.addOperand(MI.getOperand(OpIdx++)); 490 // Copy the am6offset operand. 491 if (TableEntry->HasWriteBack) 492 MIB.addOperand(MI.getOperand(OpIdx++)); 493 494 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 495 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 496 unsigned D0, D1, D2, D3; 497 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 498 MIB.addReg(D0).addReg(D1); 499 if (NumRegs > 2) 500 MIB.addReg(D2); 501 if (NumRegs > 3) 502 MIB.addReg(D3); 503 504 // Copy the predicate operands. 505 MIB.addOperand(MI.getOperand(OpIdx++)); 506 MIB.addOperand(MI.getOperand(OpIdx++)); 507 508 if (SrcIsKill) // Add an implicit kill for the super-reg. 509 MIB->addRegisterKilled(SrcReg, TRI, true); 510 TransferImpOps(MI, MIB, MIB); 511 512 // Transfer memoperands. 513 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 514 515 MI.eraseFromParent(); 516 } 517 518 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 519 /// register operands to real instructions with D register operands. 520 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 521 MachineInstr &MI = *MBBI; 522 MachineBasicBlock &MBB = *MI.getParent(); 523 524 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 525 assert(TableEntry && "NEONLdStTable lookup failed"); 526 NEONRegSpacing RegSpc = TableEntry->RegSpacing; 527 unsigned NumRegs = TableEntry->NumRegs; 528 unsigned RegElts = TableEntry->RegElts; 529 530 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 531 TII->get(TableEntry->RealOpc)); 532 unsigned OpIdx = 0; 533 // The lane operand is always the 3rd from last operand, before the 2 534 // predicate operands. 535 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 536 537 // Adjust the lane and spacing as needed for Q registers. 538 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 539 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 540 RegSpc = OddDblSpc; 541 Lane -= RegElts; 542 } 543 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 544 545 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 546 unsigned DstReg = 0; 547 bool DstIsDead = false; 548 if (TableEntry->IsLoad) { 549 DstIsDead = MI.getOperand(OpIdx).isDead(); 550 DstReg = MI.getOperand(OpIdx++).getReg(); 551 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 552 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 553 if (NumRegs > 1) 554 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 555 if (NumRegs > 2) 556 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 557 if (NumRegs > 3) 558 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 559 } 560 561 if (TableEntry->HasWriteBack) 562 MIB.addOperand(MI.getOperand(OpIdx++)); 563 564 // Copy the addrmode6 operands. 565 MIB.addOperand(MI.getOperand(OpIdx++)); 566 MIB.addOperand(MI.getOperand(OpIdx++)); 567 // Copy the am6offset operand. 568 if (TableEntry->HasWriteBack) 569 MIB.addOperand(MI.getOperand(OpIdx++)); 570 571 // Grab the super-register source. 572 MachineOperand MO = MI.getOperand(OpIdx++); 573 if (!TableEntry->IsLoad) 574 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 575 576 // Add the subregs as sources of the new instruction. 577 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 578 getKillRegState(MO.isKill())); 579 MIB.addReg(D0, SrcFlags); 580 if (NumRegs > 1) 581 MIB.addReg(D1, SrcFlags); 582 if (NumRegs > 2) 583 MIB.addReg(D2, SrcFlags); 584 if (NumRegs > 3) 585 MIB.addReg(D3, SrcFlags); 586 587 // Add the lane number operand. 588 MIB.addImm(Lane); 589 OpIdx += 1; 590 591 // Copy the predicate operands. 592 MIB.addOperand(MI.getOperand(OpIdx++)); 593 MIB.addOperand(MI.getOperand(OpIdx++)); 594 595 // Copy the super-register source to be an implicit source. 596 MO.setImplicit(true); 597 MIB.addOperand(MO); 598 if (TableEntry->IsLoad) 599 // Add an implicit def for the super-register. 600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 601 TransferImpOps(MI, MIB, MIB); 602 MI.eraseFromParent(); 603 } 604 605 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 606 /// register operands to real instructions with D register operands. 607 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 608 unsigned Opc, bool IsExt, unsigned NumRegs) { 609 MachineInstr &MI = *MBBI; 610 MachineBasicBlock &MBB = *MI.getParent(); 611 612 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 613 unsigned OpIdx = 0; 614 615 // Transfer the destination register operand. 616 MIB.addOperand(MI.getOperand(OpIdx++)); 617 if (IsExt) 618 MIB.addOperand(MI.getOperand(OpIdx++)); 619 620 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 621 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 622 unsigned D0, D1, D2, D3; 623 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 624 MIB.addReg(D0).addReg(D1); 625 if (NumRegs > 2) 626 MIB.addReg(D2); 627 if (NumRegs > 3) 628 MIB.addReg(D3); 629 630 // Copy the other source register operand. 631 MIB.addOperand(MI.getOperand(OpIdx++)); 632 633 // Copy the predicate operands. 634 MIB.addOperand(MI.getOperand(OpIdx++)); 635 MIB.addOperand(MI.getOperand(OpIdx++)); 636 637 if (SrcIsKill) // Add an implicit kill for the super-reg. 638 MIB->addRegisterKilled(SrcReg, TRI, true); 639 TransferImpOps(MI, MIB, MIB); 640 MI.eraseFromParent(); 641 } 642 643 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 644 MachineBasicBlock::iterator &MBBI) { 645 MachineInstr &MI = *MBBI; 646 unsigned Opcode = MI.getOpcode(); 647 unsigned PredReg = 0; 648 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); 649 unsigned DstReg = MI.getOperand(0).getReg(); 650 bool DstIsDead = MI.getOperand(0).isDead(); 651 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 652 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 653 MachineInstrBuilder LO16, HI16; 654 655 if (!STI->hasV6T2Ops() && 656 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 657 // Expand into a movi + orr. 658 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 659 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 660 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 661 .addReg(DstReg); 662 663 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 664 unsigned ImmVal = (unsigned)MO.getImm(); 665 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 666 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 667 LO16 = LO16.addImm(SOImmValV1); 668 HI16 = HI16.addImm(SOImmValV2); 669 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 670 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 671 LO16.addImm(Pred).addReg(PredReg).addReg(0); 672 HI16.addImm(Pred).addReg(PredReg).addReg(0); 673 TransferImpOps(MI, LO16, HI16); 674 MI.eraseFromParent(); 675 return; 676 } 677 678 unsigned LO16Opc = 0; 679 unsigned HI16Opc = 0; 680 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 681 LO16Opc = ARM::t2MOVi16; 682 HI16Opc = ARM::t2MOVTi16; 683 } else { 684 LO16Opc = ARM::MOVi16; 685 HI16Opc = ARM::MOVTi16; 686 } 687 688 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 689 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 690 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 691 .addReg(DstReg); 692 693 if (MO.isImm()) { 694 unsigned Imm = MO.getImm(); 695 unsigned Lo16 = Imm & 0xffff; 696 unsigned Hi16 = (Imm >> 16) & 0xffff; 697 LO16 = LO16.addImm(Lo16); 698 HI16 = HI16.addImm(Hi16); 699 } else { 700 const GlobalValue *GV = MO.getGlobal(); 701 unsigned TF = MO.getTargetFlags(); 702 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 703 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 704 } 705 706 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 707 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 708 LO16.addImm(Pred).addReg(PredReg); 709 HI16.addImm(Pred).addReg(PredReg); 710 711 TransferImpOps(MI, LO16, HI16); 712 MI.eraseFromParent(); 713 } 714 715 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 716 MachineBasicBlock::iterator MBBI) { 717 MachineInstr &MI = *MBBI; 718 unsigned Opcode = MI.getOpcode(); 719 switch (Opcode) { 720 default: 721 return false; 722 case ARM::VMOVScc: 723 case ARM::VMOVDcc: { 724 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; 725 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 726 MI.getOperand(1).getReg()) 727 .addReg(MI.getOperand(2).getReg(), 728 getKillRegState(MI.getOperand(2).isKill())) 729 .addImm(MI.getOperand(3).getImm()) // 'pred' 730 .addReg(MI.getOperand(4).getReg()); 731 732 MI.eraseFromParent(); 733 return true; 734 } 735 case ARM::t2MOVCCr: 736 case ARM::MOVCCr: { 737 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 738 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 739 MI.getOperand(1).getReg()) 740 .addReg(MI.getOperand(2).getReg(), 741 getKillRegState(MI.getOperand(2).isKill())) 742 .addImm(MI.getOperand(3).getImm()) // 'pred' 743 .addReg(MI.getOperand(4).getReg()) 744 .addReg(0); // 's' bit 745 746 MI.eraseFromParent(); 747 return true; 748 } 749 case ARM::MOVCCsi: { 750 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 751 (MI.getOperand(1).getReg())) 752 .addReg(MI.getOperand(2).getReg(), 753 getKillRegState(MI.getOperand(2).isKill())) 754 .addImm(MI.getOperand(3).getImm()) 755 .addImm(MI.getOperand(4).getImm()) // 'pred' 756 .addReg(MI.getOperand(5).getReg()) 757 .addReg(0); // 's' bit 758 759 MI.eraseFromParent(); 760 return true; 761 } 762 763 case ARM::MOVCCsr: { 764 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 765 (MI.getOperand(1).getReg())) 766 .addReg(MI.getOperand(2).getReg(), 767 getKillRegState(MI.getOperand(2).isKill())) 768 .addReg(MI.getOperand(3).getReg(), 769 getKillRegState(MI.getOperand(3).isKill())) 770 .addImm(MI.getOperand(4).getImm()) 771 .addImm(MI.getOperand(5).getImm()) // 'pred' 772 .addReg(MI.getOperand(6).getReg()) 773 .addReg(0); // 's' bit 774 775 MI.eraseFromParent(); 776 return true; 777 } 778 case ARM::MOVCCi16: { 779 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16), 780 MI.getOperand(1).getReg()) 781 .addImm(MI.getOperand(2).getImm()) 782 .addImm(MI.getOperand(3).getImm()) // 'pred' 783 .addReg(MI.getOperand(4).getReg()); 784 785 MI.eraseFromParent(); 786 return true; 787 } 788 case ARM::t2MOVCCi: 789 case ARM::MOVCCi: { 790 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 791 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 792 MI.getOperand(1).getReg()) 793 .addImm(MI.getOperand(2).getImm()) 794 .addImm(MI.getOperand(3).getImm()) // 'pred' 795 .addReg(MI.getOperand(4).getReg()) 796 .addReg(0); // 's' bit 797 798 MI.eraseFromParent(); 799 return true; 800 } 801 case ARM::MVNCCi: { 802 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), 803 MI.getOperand(1).getReg()) 804 .addImm(MI.getOperand(2).getImm()) 805 .addImm(MI.getOperand(3).getImm()) // 'pred' 806 .addReg(MI.getOperand(4).getReg()) 807 .addReg(0); // 's' bit 808 809 MI.eraseFromParent(); 810 return true; 811 } 812 case ARM::Int_eh_sjlj_dispatchsetup: { 813 MachineFunction &MF = *MI.getParent()->getParent(); 814 const ARMBaseInstrInfo *AII = 815 static_cast<const ARMBaseInstrInfo*>(TII); 816 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 817 // For functions using a base pointer, we rematerialize it (via the frame 818 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 819 // for us. Otherwise, expand to nothing. 820 if (RI.hasBasePointer(MF)) { 821 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 822 unsigned FramePtr = RI.getFrameRegister(MF); 823 assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 824 "base pointer without frame pointer?"); 825 826 if (AFI->isThumb2Function()) { 827 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 828 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 829 } else if (AFI->isThumbFunction()) { 830 llvm::emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 831 FramePtr, -NumBytes, *TII, RI); 832 } else { 833 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 834 FramePtr, -NumBytes, ARMCC::AL, 0, 835 *TII); 836 } 837 // If there's dynamic realignment, adjust for it. 838 if (RI.needsStackRealignment(MF)) { 839 MachineFrameInfo *MFI = MF.getFrameInfo(); 840 unsigned MaxAlign = MFI->getMaxAlignment(); 841 assert (!AFI->isThumb1OnlyFunction()); 842 // Emit bic r6, r6, MaxAlign 843 unsigned bicOpc = AFI->isThumbFunction() ? 844 ARM::t2BICri : ARM::BICri; 845 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 846 TII->get(bicOpc), ARM::R6) 847 .addReg(ARM::R6, RegState::Kill) 848 .addImm(MaxAlign-1))); 849 } 850 851 } 852 MI.eraseFromParent(); 853 return true; 854 } 855 856 case ARM::MOVsrl_flag: 857 case ARM::MOVsra_flag: { 858 // These are just fancy MOVs insructions. 859 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 860 MI.getOperand(0).getReg()) 861 .addOperand(MI.getOperand(1)) 862 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? 863 ARM_AM::lsr : ARM_AM::asr), 864 1))) 865 .addReg(ARM::CPSR, RegState::Define); 866 MI.eraseFromParent(); 867 return true; 868 } 869 case ARM::RRX: { 870 // This encodes as "MOVs Rd, Rm, rrx 871 MachineInstrBuilder MIB = 872 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi), 873 MI.getOperand(0).getReg()) 874 .addOperand(MI.getOperand(1)) 875 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 876 .addReg(0); 877 TransferImpOps(MI, MIB, MIB); 878 MI.eraseFromParent(); 879 return true; 880 } 881 case ARM::tTPsoft: 882 case ARM::TPsoft: { 883 MachineInstrBuilder MIB = 884 BuildMI(MBB, MBBI, MI.getDebugLoc(), 885 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL)) 886 .addExternalSymbol("__aeabi_read_tp", 0); 887 888 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 889 TransferImpOps(MI, MIB, MIB); 890 MI.eraseFromParent(); 891 return true; 892 } 893 case ARM::tLDRpci_pic: 894 case ARM::t2LDRpci_pic: { 895 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 896 ? ARM::tLDRpci : ARM::t2LDRpci; 897 unsigned DstReg = MI.getOperand(0).getReg(); 898 bool DstIsDead = MI.getOperand(0).isDead(); 899 MachineInstrBuilder MIB1 = 900 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 901 TII->get(NewLdOpc), DstReg) 902 .addOperand(MI.getOperand(1))); 903 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 904 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 905 TII->get(ARM::tPICADD)) 906 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 907 .addReg(DstReg) 908 .addOperand(MI.getOperand(2)); 909 TransferImpOps(MI, MIB1, MIB2); 910 MI.eraseFromParent(); 911 return true; 912 } 913 914 case ARM::MOV_ga_dyn: 915 case ARM::MOV_ga_pcrel: 916 case ARM::MOV_ga_pcrel_ldr: 917 case ARM::t2MOV_ga_dyn: 918 case ARM::t2MOV_ga_pcrel: { 919 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 920 unsigned LabelId = AFI->createPICLabelUId(); 921 unsigned DstReg = MI.getOperand(0).getReg(); 922 bool DstIsDead = MI.getOperand(0).isDead(); 923 const MachineOperand &MO1 = MI.getOperand(1); 924 const GlobalValue *GV = MO1.getGlobal(); 925 unsigned TF = MO1.getTargetFlags(); 926 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn); 927 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn); 928 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 929 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 930 unsigned LO16TF = isPIC 931 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY; 932 unsigned HI16TF = isPIC 933 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY; 934 unsigned PICAddOpc = isARM 935 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 936 : ARM::tPICADD; 937 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 938 TII->get(LO16Opc), DstReg) 939 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 940 .addImm(LabelId); 941 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 942 TII->get(HI16Opc), DstReg) 943 .addReg(DstReg) 944 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 945 .addImm(LabelId); 946 if (!isPIC) { 947 TransferImpOps(MI, MIB1, MIB2); 948 MI.eraseFromParent(); 949 return true; 950 } 951 952 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 953 TII->get(PICAddOpc)) 954 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 955 .addReg(DstReg).addImm(LabelId); 956 if (isARM) { 957 AddDefaultPred(MIB3); 958 if (Opcode == ARM::MOV_ga_pcrel_ldr) 959 MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 960 } 961 TransferImpOps(MI, MIB1, MIB3); 962 MI.eraseFromParent(); 963 return true; 964 } 965 966 case ARM::MOVi32imm: 967 case ARM::MOVCCi32imm: 968 case ARM::t2MOVi32imm: 969 case ARM::t2MOVCCi32imm: 970 ExpandMOV32BitImm(MBB, MBBI); 971 return true; 972 973 case ARM::VLDMQIA: { 974 unsigned NewOpc = ARM::VLDMDIA; 975 MachineInstrBuilder MIB = 976 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 977 unsigned OpIdx = 0; 978 979 // Grab the Q register destination. 980 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 981 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 982 983 // Copy the source register. 984 MIB.addOperand(MI.getOperand(OpIdx++)); 985 986 // Copy the predicate operands. 987 MIB.addOperand(MI.getOperand(OpIdx++)); 988 MIB.addOperand(MI.getOperand(OpIdx++)); 989 990 // Add the destination operands (D subregs). 991 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 992 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 993 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 994 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 995 996 // Add an implicit def for the super-register. 997 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 998 TransferImpOps(MI, MIB, MIB); 999 MI.eraseFromParent(); 1000 return true; 1001 } 1002 1003 case ARM::VSTMQIA: { 1004 unsigned NewOpc = ARM::VSTMDIA; 1005 MachineInstrBuilder MIB = 1006 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1007 unsigned OpIdx = 0; 1008 1009 // Grab the Q register source. 1010 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 1011 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 1012 1013 // Copy the destination register. 1014 MIB.addOperand(MI.getOperand(OpIdx++)); 1015 1016 // Copy the predicate operands. 1017 MIB.addOperand(MI.getOperand(OpIdx++)); 1018 MIB.addOperand(MI.getOperand(OpIdx++)); 1019 1020 // Add the source operands (D subregs). 1021 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 1022 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 1023 MIB.addReg(D0).addReg(D1); 1024 1025 if (SrcIsKill) // Add an implicit kill for the Q register. 1026 MIB->addRegisterKilled(SrcReg, TRI, true); 1027 1028 TransferImpOps(MI, MIB, MIB); 1029 MI.eraseFromParent(); 1030 return true; 1031 } 1032 case ARM::VDUPfqf: 1033 case ARM::VDUPfdf:{ 1034 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : 1035 ARM::VDUPLN32d; 1036 MachineInstrBuilder MIB = 1037 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1038 unsigned OpIdx = 0; 1039 unsigned SrcReg = MI.getOperand(1).getReg(); 1040 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1; 1041 unsigned DReg = TRI->getMatchingSuperReg(SrcReg, 1042 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, 1043 &ARM::DPR_VFP2RegClass); 1044 // The lane is [0,1] for the containing DReg superregister. 1045 // Copy the dst/src register operands. 1046 MIB.addOperand(MI.getOperand(OpIdx++)); 1047 MIB.addReg(DReg); 1048 ++OpIdx; 1049 // Add the lane select operand. 1050 MIB.addImm(Lane); 1051 // Add the predicate operands. 1052 MIB.addOperand(MI.getOperand(OpIdx++)); 1053 MIB.addOperand(MI.getOperand(OpIdx++)); 1054 1055 TransferImpOps(MI, MIB, MIB); 1056 MI.eraseFromParent(); 1057 return true; 1058 } 1059 1060 case ARM::VLD1q8Pseudo: 1061 case ARM::VLD1q16Pseudo: 1062 case ARM::VLD1q32Pseudo: 1063 case ARM::VLD1q64Pseudo: 1064 case ARM::VLD1q8Pseudo_UPD: 1065 case ARM::VLD1q16Pseudo_UPD: 1066 case ARM::VLD1q32Pseudo_UPD: 1067 case ARM::VLD1q64Pseudo_UPD: 1068 case ARM::VLD2d8Pseudo: 1069 case ARM::VLD2d16Pseudo: 1070 case ARM::VLD2d32Pseudo: 1071 case ARM::VLD2q8Pseudo: 1072 case ARM::VLD2q16Pseudo: 1073 case ARM::VLD2q32Pseudo: 1074 case ARM::VLD2d8Pseudo_UPD: 1075 case ARM::VLD2d16Pseudo_UPD: 1076 case ARM::VLD2d32Pseudo_UPD: 1077 case ARM::VLD2q8Pseudo_UPD: 1078 case ARM::VLD2q16Pseudo_UPD: 1079 case ARM::VLD2q32Pseudo_UPD: 1080 case ARM::VLD3d8Pseudo: 1081 case ARM::VLD3d16Pseudo: 1082 case ARM::VLD3d32Pseudo: 1083 case ARM::VLD1d64TPseudo: 1084 case ARM::VLD3d8Pseudo_UPD: 1085 case ARM::VLD3d16Pseudo_UPD: 1086 case ARM::VLD3d32Pseudo_UPD: 1087 case ARM::VLD1d64TPseudo_UPD: 1088 case ARM::VLD3q8Pseudo_UPD: 1089 case ARM::VLD3q16Pseudo_UPD: 1090 case ARM::VLD3q32Pseudo_UPD: 1091 case ARM::VLD3q8oddPseudo: 1092 case ARM::VLD3q16oddPseudo: 1093 case ARM::VLD3q32oddPseudo: 1094 case ARM::VLD3q8oddPseudo_UPD: 1095 case ARM::VLD3q16oddPseudo_UPD: 1096 case ARM::VLD3q32oddPseudo_UPD: 1097 case ARM::VLD4d8Pseudo: 1098 case ARM::VLD4d16Pseudo: 1099 case ARM::VLD4d32Pseudo: 1100 case ARM::VLD1d64QPseudo: 1101 case ARM::VLD4d8Pseudo_UPD: 1102 case ARM::VLD4d16Pseudo_UPD: 1103 case ARM::VLD4d32Pseudo_UPD: 1104 case ARM::VLD1d64QPseudo_UPD: 1105 case ARM::VLD4q8Pseudo_UPD: 1106 case ARM::VLD4q16Pseudo_UPD: 1107 case ARM::VLD4q32Pseudo_UPD: 1108 case ARM::VLD4q8oddPseudo: 1109 case ARM::VLD4q16oddPseudo: 1110 case ARM::VLD4q32oddPseudo: 1111 case ARM::VLD4q8oddPseudo_UPD: 1112 case ARM::VLD4q16oddPseudo_UPD: 1113 case ARM::VLD4q32oddPseudo_UPD: 1114 case ARM::VLD1DUPq8Pseudo: 1115 case ARM::VLD1DUPq16Pseudo: 1116 case ARM::VLD1DUPq32Pseudo: 1117 case ARM::VLD1DUPq8Pseudo_UPD: 1118 case ARM::VLD1DUPq16Pseudo_UPD: 1119 case ARM::VLD1DUPq32Pseudo_UPD: 1120 case ARM::VLD2DUPd8Pseudo: 1121 case ARM::VLD2DUPd16Pseudo: 1122 case ARM::VLD2DUPd32Pseudo: 1123 case ARM::VLD2DUPd8Pseudo_UPD: 1124 case ARM::VLD2DUPd16Pseudo_UPD: 1125 case ARM::VLD2DUPd32Pseudo_UPD: 1126 case ARM::VLD3DUPd8Pseudo: 1127 case ARM::VLD3DUPd16Pseudo: 1128 case ARM::VLD3DUPd32Pseudo: 1129 case ARM::VLD3DUPd8Pseudo_UPD: 1130 case ARM::VLD3DUPd16Pseudo_UPD: 1131 case ARM::VLD3DUPd32Pseudo_UPD: 1132 case ARM::VLD4DUPd8Pseudo: 1133 case ARM::VLD4DUPd16Pseudo: 1134 case ARM::VLD4DUPd32Pseudo: 1135 case ARM::VLD4DUPd8Pseudo_UPD: 1136 case ARM::VLD4DUPd16Pseudo_UPD: 1137 case ARM::VLD4DUPd32Pseudo_UPD: 1138 ExpandVLD(MBBI); 1139 return true; 1140 1141 case ARM::VST1q8Pseudo: 1142 case ARM::VST1q16Pseudo: 1143 case ARM::VST1q32Pseudo: 1144 case ARM::VST1q64Pseudo: 1145 case ARM::VST1q8Pseudo_UPD: 1146 case ARM::VST1q16Pseudo_UPD: 1147 case ARM::VST1q32Pseudo_UPD: 1148 case ARM::VST1q64Pseudo_UPD: 1149 case ARM::VST2d8Pseudo: 1150 case ARM::VST2d16Pseudo: 1151 case ARM::VST2d32Pseudo: 1152 case ARM::VST2q8Pseudo: 1153 case ARM::VST2q16Pseudo: 1154 case ARM::VST2q32Pseudo: 1155 case ARM::VST2d8Pseudo_UPD: 1156 case ARM::VST2d16Pseudo_UPD: 1157 case ARM::VST2d32Pseudo_UPD: 1158 case ARM::VST2q8Pseudo_UPD: 1159 case ARM::VST2q16Pseudo_UPD: 1160 case ARM::VST2q32Pseudo_UPD: 1161 case ARM::VST3d8Pseudo: 1162 case ARM::VST3d16Pseudo: 1163 case ARM::VST3d32Pseudo: 1164 case ARM::VST1d64TPseudo: 1165 case ARM::VST3d8Pseudo_UPD: 1166 case ARM::VST3d16Pseudo_UPD: 1167 case ARM::VST3d32Pseudo_UPD: 1168 case ARM::VST1d64TPseudo_UPD: 1169 case ARM::VST3q8Pseudo_UPD: 1170 case ARM::VST3q16Pseudo_UPD: 1171 case ARM::VST3q32Pseudo_UPD: 1172 case ARM::VST3q8oddPseudo: 1173 case ARM::VST3q16oddPseudo: 1174 case ARM::VST3q32oddPseudo: 1175 case ARM::VST3q8oddPseudo_UPD: 1176 case ARM::VST3q16oddPseudo_UPD: 1177 case ARM::VST3q32oddPseudo_UPD: 1178 case ARM::VST4d8Pseudo: 1179 case ARM::VST4d16Pseudo: 1180 case ARM::VST4d32Pseudo: 1181 case ARM::VST1d64QPseudo: 1182 case ARM::VST4d8Pseudo_UPD: 1183 case ARM::VST4d16Pseudo_UPD: 1184 case ARM::VST4d32Pseudo_UPD: 1185 case ARM::VST1d64QPseudo_UPD: 1186 case ARM::VST4q8Pseudo_UPD: 1187 case ARM::VST4q16Pseudo_UPD: 1188 case ARM::VST4q32Pseudo_UPD: 1189 case ARM::VST4q8oddPseudo: 1190 case ARM::VST4q16oddPseudo: 1191 case ARM::VST4q32oddPseudo: 1192 case ARM::VST4q8oddPseudo_UPD: 1193 case ARM::VST4q16oddPseudo_UPD: 1194 case ARM::VST4q32oddPseudo_UPD: 1195 ExpandVST(MBBI); 1196 return true; 1197 1198 case ARM::VLD1LNq8Pseudo: 1199 case ARM::VLD1LNq16Pseudo: 1200 case ARM::VLD1LNq32Pseudo: 1201 case ARM::VLD1LNq8Pseudo_UPD: 1202 case ARM::VLD1LNq16Pseudo_UPD: 1203 case ARM::VLD1LNq32Pseudo_UPD: 1204 case ARM::VLD2LNd8Pseudo: 1205 case ARM::VLD2LNd16Pseudo: 1206 case ARM::VLD2LNd32Pseudo: 1207 case ARM::VLD2LNq16Pseudo: 1208 case ARM::VLD2LNq32Pseudo: 1209 case ARM::VLD2LNd8Pseudo_UPD: 1210 case ARM::VLD2LNd16Pseudo_UPD: 1211 case ARM::VLD2LNd32Pseudo_UPD: 1212 case ARM::VLD2LNq16Pseudo_UPD: 1213 case ARM::VLD2LNq32Pseudo_UPD: 1214 case ARM::VLD3LNd8Pseudo: 1215 case ARM::VLD3LNd16Pseudo: 1216 case ARM::VLD3LNd32Pseudo: 1217 case ARM::VLD3LNq16Pseudo: 1218 case ARM::VLD3LNq32Pseudo: 1219 case ARM::VLD3LNd8Pseudo_UPD: 1220 case ARM::VLD3LNd16Pseudo_UPD: 1221 case ARM::VLD3LNd32Pseudo_UPD: 1222 case ARM::VLD3LNq16Pseudo_UPD: 1223 case ARM::VLD3LNq32Pseudo_UPD: 1224 case ARM::VLD4LNd8Pseudo: 1225 case ARM::VLD4LNd16Pseudo: 1226 case ARM::VLD4LNd32Pseudo: 1227 case ARM::VLD4LNq16Pseudo: 1228 case ARM::VLD4LNq32Pseudo: 1229 case ARM::VLD4LNd8Pseudo_UPD: 1230 case ARM::VLD4LNd16Pseudo_UPD: 1231 case ARM::VLD4LNd32Pseudo_UPD: 1232 case ARM::VLD4LNq16Pseudo_UPD: 1233 case ARM::VLD4LNq32Pseudo_UPD: 1234 case ARM::VST1LNq8Pseudo: 1235 case ARM::VST1LNq16Pseudo: 1236 case ARM::VST1LNq32Pseudo: 1237 case ARM::VST1LNq8Pseudo_UPD: 1238 case ARM::VST1LNq16Pseudo_UPD: 1239 case ARM::VST1LNq32Pseudo_UPD: 1240 case ARM::VST2LNd8Pseudo: 1241 case ARM::VST2LNd16Pseudo: 1242 case ARM::VST2LNd32Pseudo: 1243 case ARM::VST2LNq16Pseudo: 1244 case ARM::VST2LNq32Pseudo: 1245 case ARM::VST2LNd8Pseudo_UPD: 1246 case ARM::VST2LNd16Pseudo_UPD: 1247 case ARM::VST2LNd32Pseudo_UPD: 1248 case ARM::VST2LNq16Pseudo_UPD: 1249 case ARM::VST2LNq32Pseudo_UPD: 1250 case ARM::VST3LNd8Pseudo: 1251 case ARM::VST3LNd16Pseudo: 1252 case ARM::VST3LNd32Pseudo: 1253 case ARM::VST3LNq16Pseudo: 1254 case ARM::VST3LNq32Pseudo: 1255 case ARM::VST3LNd8Pseudo_UPD: 1256 case ARM::VST3LNd16Pseudo_UPD: 1257 case ARM::VST3LNd32Pseudo_UPD: 1258 case ARM::VST3LNq16Pseudo_UPD: 1259 case ARM::VST3LNq32Pseudo_UPD: 1260 case ARM::VST4LNd8Pseudo: 1261 case ARM::VST4LNd16Pseudo: 1262 case ARM::VST4LNd32Pseudo: 1263 case ARM::VST4LNq16Pseudo: 1264 case ARM::VST4LNq32Pseudo: 1265 case ARM::VST4LNd8Pseudo_UPD: 1266 case ARM::VST4LNd16Pseudo_UPD: 1267 case ARM::VST4LNd32Pseudo_UPD: 1268 case ARM::VST4LNq16Pseudo_UPD: 1269 case ARM::VST4LNq32Pseudo_UPD: 1270 ExpandLaneOp(MBBI); 1271 return true; 1272 1273 case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); return true; 1274 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); return true; 1275 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); return true; 1276 case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); return true; 1277 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); return true; 1278 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); return true; 1279 } 1280 1281 return false; 1282 } 1283 1284 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 1285 bool Modified = false; 1286 1287 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 1288 while (MBBI != E) { 1289 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI); 1290 Modified |= ExpandMI(MBB, MBBI); 1291 MBBI = NMBBI; 1292 } 1293 1294 return Modified; 1295 } 1296 1297 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 1298 const TargetMachine &TM = MF.getTarget(); 1299 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo()); 1300 TRI = TM.getRegisterInfo(); 1301 STI = &TM.getSubtarget<ARMSubtarget>(); 1302 AFI = MF.getInfo<ARMFunctionInfo>(); 1303 1304 bool Modified = false; 1305 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1306 ++MFI) 1307 Modified |= ExpandMBB(*MFI); 1308 if (VerifyARMPseudo) 1309 MF.verify(this, "After expanding ARM pseudo instructions."); 1310 return Modified; 1311 } 1312 1313 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1314 /// expansion pass. 1315 FunctionPass *llvm::createARMExpandPseudoPass() { 1316 return new ARMExpandPseudo(); 1317 } 1318
