1 /* 2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __HI6220_PERI_H__ 33 #define __HI6220_PERI_H__ 34 35 #define PERI_BASE 0xF7030000 36 37 #define PERI_SC_PERIPH_CTRL1 (PERI_BASE + 0x000) 38 #define PERI_SC_PERIPH_CTRL2 (PERI_BASE + 0x004) 39 #define PERI_SC_PERIPH_CTRL3 (PERI_BASE + 0x008) 40 #define PERI_SC_PERIPH_CTRL4 (PERI_BASE + 0x00c) 41 #define PERI_SC_PERIPH_CTRL5 (PERI_BASE + 0x010) 42 #define PERI_SC_PERIPH_CTRL6 (PERI_BASE + 0x014) 43 #define PERI_SC_PERIPH_CTRL8 (PERI_BASE + 0x018) 44 #define PERI_SC_PERIPH_CTRL9 (PERI_BASE + 0x01c) 45 #define PERI_SC_PERIPH_CTRL10 (PERI_BASE + 0x020) 46 #define PERI_SC_PERIPH_CTRL12 (PERI_BASE + 0x024) 47 #define PERI_SC_PERIPH_CTRL13 (PERI_BASE + 0x028) 48 #define PERI_SC_PERIPH_CTRL14 (PERI_BASE + 0x02c) 49 50 #define PERI_SC_DDR_CTRL0 (PERI_BASE + 0x050) 51 #define PERI_SC_PERIPH_STAT1 (PERI_BASE + 0x094) 52 53 #define PERI_SC_PERIPH_CLKEN0 (PERI_BASE + 0x200) 54 #define PERI_SC_PERIPH_CLKDIS0 (PERI_BASE + 0x204) 55 #define PERI_SC_PERIPH_CLKSTAT0 (PERI_BASE + 0x208) 56 #define PERI_SC_PERIPH_CLKEN1 (PERI_BASE + 0x210) 57 #define PERI_SC_PERIPH_CLKDIS1 (PERI_BASE + 0x214) 58 #define PERI_SC_PERIPH_CLKSTAT1 (PERI_BASE + 0x218) 59 #define PERI_SC_PERIPH_CLKEN2 (PERI_BASE + 0x220) 60 #define PERI_SC_PERIPH_CLKDIS2 (PERI_BASE + 0x224) 61 #define PERI_SC_PERIPH_CLKSTAT2 (PERI_BASE + 0x228) 62 #define PERI_SC_PERIPH_CLKEN3 (PERI_BASE + 0x230) 63 #define PERI_SC_PERIPH_CLKDIS3 (PERI_BASE + 0x234) 64 #define PERI_SC_PERIPH_CLKSTAT3 (PERI_BASE + 0x238) 65 #define PERI_SC_PERIPH_CLKEN8 (PERI_BASE + 0x240) 66 #define PERI_SC_PERIPH_CLKDIS8 (PERI_BASE + 0x244) 67 #define PERI_SC_PERIPH_CLKSTAT8 (PERI_BASE + 0x248) 68 #define PERI_SC_PERIPH_CLKEN9 (PERI_BASE + 0x250) 69 #define PERI_SC_PERIPH_CLKDIS9 (PERI_BASE + 0x254) 70 #define PERI_SC_PERIPH_CLKSTAT9 (PERI_BASE + 0x258) 71 #define PERI_SC_PERIPH_CLKEN10 (PERI_BASE + 0x260) 72 #define PERI_SC_PERIPH_CLKDIS10 (PERI_BASE + 0x264) 73 #define PERI_SC_PERIPH_CLKSTAT10 (PERI_BASE + 0x268) 74 #define PERI_SC_PERIPH_CLKEN12 (PERI_BASE + 0x270) 75 #define PERI_SC_PERIPH_CLKDIS12 (PERI_BASE + 0x274) 76 #define PERI_SC_PERIPH_CLKSTAT12 (PERI_BASE + 0x278) 77 78 #define PERI_SC_PERIPH_RSTEN0 (PERI_BASE + 0x300) 79 #define PERI_SC_PERIPH_RSTDIS0 (PERI_BASE + 0x304) 80 #define PERI_SC_PERIPH_RSTSTAT0 (PERI_BASE + 0x308) 81 #define PERI_SC_PERIPH_RSTEN1 (PERI_BASE + 0x310) 82 #define PERI_SC_PERIPH_RSTDIS1 (PERI_BASE + 0x314) 83 #define PERI_SC_PERIPH_RSTSTAT1 (PERI_BASE + 0x318) 84 #define PERI_SC_PERIPH_RSTEN2 (PERI_BASE + 0x320) 85 #define PERI_SC_PERIPH_RSTDIS2 (PERI_BASE + 0x324) 86 #define PERI_SC_PERIPH_RSTSTAT2 (PERI_BASE + 0x328) 87 #define PERI_SC_PERIPH_RSTEN3 (PERI_BASE + 0x330) 88 #define PERI_SC_PERIPH_RSTDIS3 (PERI_BASE + 0x334) 89 #define PERI_SC_PERIPH_RSTSTAT3 (PERI_BASE + 0x338) 90 #define PERI_SC_PERIPH_RSTEN8 (PERI_BASE + 0x340) 91 #define PERI_SC_PERIPH_RSTDIS8 (PERI_BASE + 0x344) 92 #define PERI_SC_PERIPH_RSTSTAT8 (PERI_BASE + 0x338) 93 94 #define PERI_SC_CLK_SEL0 (PERI_BASE + 0x400) 95 #define PERI_SC_CLKCFG8BIT1 (PERI_BASE + 0x494) 96 #define PERI_SC_CLKCFG8BIT2 (PERI_BASE + 0x498) 97 #define PERI_SC_RESERVED8_ADDR (PERI_BASE + 0xd04) 98 99 /* PERI_SC_PERIPH_CTRL1 */ 100 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) 101 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) 102 #define PERI_CTRL1_HIFI_INT_MASK (1 << 1) 103 #define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) 104 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) 105 #define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) 106 #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) 107 108 /* PERI_SC_PERIPH_CTRL2 */ 109 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) 110 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) 111 #define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) 112 #define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) 113 #define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) 114 #define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) 115 #define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) 116 #define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) 117 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) 118 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) 119 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) 120 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) 121 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) 122 #define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) 123 124 /* PERI_SC_PERIPH_CTRL3 */ 125 #define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) 126 #define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) 127 #define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) 128 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) 129 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) 130 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) 131 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) 132 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) 133 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) 134 135 /* PERI_SC_PERIPH_CTRL4 */ 136 #define PERI_CTRL4_PICO_FSELV (1 << 0) 137 #define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) 138 #define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) 139 #define PERI_CTRL4_PICO_SIDDQ (1 << 6) 140 #define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) 141 #define PERI_CTRL4_PICO_OGDISABLE (1 << 8) 142 #define PERI_CTRL4_PICO_COMMONONN (1 << 9) 143 #define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) 144 #define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) 145 #define PERI_CTRL4_PICO_VATESTENB (1 << 12) 146 #define PERI_CTRL4_PICO_SUSPENDM (1 << 14) 147 #define PERI_CTRL4_PICO_SLEEPM (1 << 15) 148 #define PERI_CTRL4_BC11_C (1 << 16) 149 #define PERI_CTRL4_BC11_B (1 << 17) 150 #define PERI_CTRL4_BC11_A (1 << 18) 151 #define PERI_CTRL4_BC11_GND (1 << 19) 152 #define PERI_CTRL4_BC11_FLOAT (1 << 20) 153 #define PERI_CTRL4_OTG_PHY_SEL (1 << 21) 154 #define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) 155 #define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) 156 #define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) 157 #define PERI_CTRL4_OTG_IDPULLUP (1 << 26) 158 #define PERI_CTRL4_OTG_DRVBUS (1 << 27) 159 #define PERI_CTRL4_OTG_SESSEND (1 << 28) 160 #define PERI_CTRL4_OTG_BVALID (1 << 29) 161 #define PERI_CTRL4_OTG_AVALID (1 << 30) 162 #define PERI_CTRL4_OTG_VBUSVALID (1 << 31) 163 164 /* PERI_SC_PERIPH_CTRL5 */ 165 #define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) 166 #define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) 167 #define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) 168 #define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) 169 #define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) 170 #define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) 171 #define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) 172 #define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) 173 #define PERI_CTRL5_DBG_MUX (1 << 11) 174 175 /* PERI_SC_PERIPH_CTRL6 */ 176 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) 177 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) 178 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) 179 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) 180 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) 181 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) 182 183 /* PERI_SC_PERIPH_CTRL8 */ 184 #define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) 185 #define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) 186 #define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) 187 #define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) 188 #define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) 189 #define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) 190 #define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) 191 #define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) 192 #define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) 193 #define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) 194 195 /* PERI_SC_PERIPH_CTRL9 */ 196 #define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) 197 #define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) 198 #define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) 199 #define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) 200 201 /* 202 * PERI_SC_PERIPH_CLKEN0 203 * PERI_SC_PERIPH_CLKDIS0 204 * PERI_SC_PERIPH_CLKSTAT0 205 */ 206 #define PERI_CLK0_MMC0 (1 << 0) 207 #define PERI_CLK0_MMC1 (1 << 1) 208 #define PERI_CLK0_MMC2 (1 << 2) 209 #define PERI_CLK0_NANDC (1 << 3) 210 #define PERI_CLK0_USBOTG (1 << 4) 211 #define PERI_CLK0_PICOPHY (1 << 5) 212 #define PERI_CLK0_PLL (1 << 6) 213 214 /* 215 * PERI_SC_PERIPH_CLKEN1 216 * PERI_SC_PERIPH_CLKDIS1 217 * PERI_SC_PERIPH_CLKSTAT1 218 */ 219 #define PERI_CLK1_HIFI (1 << 0) 220 #define PERI_CLK1_DIGACODEC (1 << 5) 221 222 /* 223 * PERI_SC_PERIPH_CLKEN2 224 * PERI_SC_PERIPH_CLKDIS2 225 * PERI_SC_PERIPH_CLKSTAT2 226 */ 227 #define PERI_CLK2_IPF (1 << 0) 228 #define PERI_CLK2_SOCP (1 << 1) 229 #define PERI_CLK2_DMAC (1 << 2) 230 #define PERI_CLK2_SECENG (1 << 3) 231 #define PERI_CLK2_HPM0 (1 << 5) 232 #define PERI_CLK2_HPM1 (1 << 6) 233 #define PERI_CLK2_HPM2 (1 << 7) 234 #define PERI_CLK2_HPM3 (1 << 8) 235 236 /* 237 * PERI_SC_PERIPH_CLKEN3 238 * PERI_SC_PERIPH_CLKDIS3 239 * PERI_SC_PERIPH_CLKSTAT3 240 */ 241 #define PERI_CLK3_CSSYS (1 << 0) 242 #define PERI_CLK3_I2C0 (1 << 1) 243 #define PERI_CLK3_I2C1 (1 << 2) 244 #define PERI_CLK3_I2C2 (1 << 3) 245 #define PERI_CLK3_I2C3 (1 << 4) 246 #define PERI_CLK3_UART1 (1 << 5) 247 #define PERI_CLK3_UART2 (1 << 6) 248 #define PERI_CLK3_UART3 (1 << 7) 249 #define PERI_CLK3_UART4 (1 << 8) 250 #define PERI_CLK3_SSP (1 << 9) 251 #define PERI_CLK3_PWM (1 << 10) 252 #define PERI_CLK3_BLPWM (1 << 11) 253 #define PERI_CLK3_TSENSOR (1 << 12) 254 #define PERI_CLK3_GPS (1 << 15) 255 #define PERI_CLK3_TCXO_PAD0 (1 << 16) 256 #define PERI_CLK3_TCXO_PAD1 (1 << 17) 257 #define PERI_CLK3_DAPB (1 << 18) 258 #define PERI_CLK3_HKADC (1 << 19) 259 #define PERI_CLK3_CODEC_SSI (1 << 20) 260 #define PERI_CLK3_TZPC_DEP (1 << 21) 261 262 /* 263 * PERI_SC_PERIPH_CLKEN8 264 * PERI_SC_PERIPH_CLKDIS8 265 * PERI_SC_PERIPH_CLKSTAT8 266 */ 267 #define PERI_CLK8_RS0 (1 << 0) 268 #define PERI_CLK8_RS2 (1 << 1) 269 #define PERI_CLK8_RS3 (1 << 2) 270 #define PERI_CLK8_MS0 (1 << 3) 271 #define PERI_CLK8_MS2 (1 << 5) 272 #define PERI_CLK8_XG2RAM0 (1 << 6) 273 #define PERI_CLK8_X2SRAM (1 << 7) 274 #define PERI_CLK8_SRAM (1 << 8) 275 #define PERI_CLK8_ROM (1 << 9) 276 #define PERI_CLK8_HARQ (1 << 10) 277 #define PERI_CLK8_MMU (1 << 11) 278 #define PERI_CLK8_DDRC (1 << 12) 279 #define PERI_CLK8_DDRPHY (1 << 13) 280 #define PERI_CLK8_DDRPHY_REF (1 << 14) 281 #define PERI_CLK8_X2X_SYSNOC (1 << 15) 282 #define PERI_CLK8_X2X_CCPU (1 << 16) 283 #define PERI_CLK8_DDRT (1 << 17) 284 #define PERI_CLK8_DDRPACK_RS (1 << 18) 285 286 /* 287 * PERI_SC_PERIPH_CLKEN9 288 * PERI_SC_PERIPH_CLKDIS9 289 * PERI_SC_PERIPH_CLKSTAT9 290 */ 291 #define PERI_CLK9_CARM_DAP (1 << 0) 292 #define PERI_CLK9_CARM_ATB (1 << 1) 293 #define PERI_CLK9_CARM_LBUS (1 << 2) 294 #define PERI_CLK9_CARM_KERNEL (1 << 3) 295 296 /* 297 * PERI_SC_PERIPH_CLKEN10 298 * PERI_SC_PERIPH_CLKDIS10 299 * PERI_SC_PERIPH_CLKSTAT10 300 */ 301 #define PERI_CLK10_IPF_CCPU (1 << 0) 302 #define PERI_CLK10_SOCP_CCPU (1 << 1) 303 #define PERI_CLK10_SECENG_CCPU (1 << 2) 304 #define PERI_CLK10_HARQ_CCPU (1 << 3) 305 #define PERI_CLK10_IPF_MCU (1 << 16) 306 #define PERI_CLK10_SOCP_MCU (1 << 17) 307 #define PERI_CLK10_SECENG_MCU (1 << 18) 308 #define PERI_CLK10_HARQ_MCU (1 << 19) 309 310 /* 311 * PERI_SC_PERIPH_CLKEN12 312 * PERI_SC_PERIPH_CLKDIS12 313 * PERI_SC_PERIPH_CLKSTAT12 314 */ 315 #define PERI_CLK12_HIFI_SRC (1 << 0) 316 #define PERI_CLK12_MMC0_SRC (1 << 1) 317 #define PERI_CLK12_MMC1_SRC (1 << 2) 318 #define PERI_CLK12_MMC2_SRC (1 << 3) 319 #define PERI_CLK12_SYSPLL_DIV (1 << 4) 320 #define PERI_CLK12_TPIU_SRC (1 << 5) 321 #define PERI_CLK12_MMC0_HF (1 << 6) 322 #define PERI_CLK12_MMC1_HF (1 << 7) 323 #define PERI_CLK12_PLL_TEST_SRC (1 << 8) 324 #define PERI_CLK12_CODEC_SOC (1 << 9) 325 #define PERI_CLK12_MEDIA (1 << 10) 326 327 /* 328 * PERI_SC_PERIPH_RSTEN0 329 * PERI_SC_PERIPH_RSTDIS0 330 * PERI_SC_PERIPH_RSTSTAT0 331 */ 332 #define PERI_RST0_MMC0 (1 << 0) 333 #define PERI_RST0_MMC1 (1 << 1) 334 #define PERI_RST0_MMC2 (1 << 2) 335 #define PERI_RST0_NANDC (1 << 3) 336 #define PERI_RST0_USBOTG_BUS (1 << 4) 337 #define PERI_RST0_POR_PICOPHY (1 << 5) 338 #define PERI_RST0_USBOTG (1 << 6) 339 #define PERI_RST0_USBOTG_32K (1 << 7) 340 341 /* 342 * PERI_SC_PERIPH_RSTEN1 343 * PERI_SC_PERIPH_RSTDIS1 344 * PERI_SC_PERIPH_RSTSTAT1 345 */ 346 #define PERI_RST1_HIFI (1 << 0) 347 #define PERI_RST1_DIGACODEC (1 << 5) 348 349 /* 350 * PERI_SC_PERIPH_RSTEN2 351 * PERI_SC_PERIPH_RSTDIS2 352 * PERI_SC_PERIPH_RSTSTAT2 353 */ 354 #define PERI_RST2_IPF (1 << 0) 355 #define PERI_RST2_SOCP (1 << 1) 356 #define PERI_RST2_DMAC (1 << 2) 357 #define PERI_RST2_SECENG (1 << 3) 358 #define PERI_RST2_ABB (1 << 4) 359 #define PERI_RST2_HPM0 (1 << 5) 360 #define PERI_RST2_HPM1 (1 << 6) 361 #define PERI_RST2_HPM2 (1 << 7) 362 #define PERI_RST2_HPM3 (1 << 8) 363 364 /* 365 * PERI_SC_PERIPH_RSTEN3 366 * PERI_SC_PERIPH_RSTDIS3 367 * PERI_SC_PERIPH_RSTSTAT3 368 */ 369 #define PERI_RST3_CSSYS (1 << 0) 370 #define PERI_RST3_I2C0 (1 << 1) 371 #define PERI_RST3_I2C1 (1 << 2) 372 #define PERI_RST3_I2C2 (1 << 3) 373 #define PERI_RST3_I2C3 (1 << 4) 374 #define PERI_RST3_UART1 (1 << 5) 375 #define PERI_RST3_UART2 (1 << 6) 376 #define PERI_RST3_UART3 (1 << 7) 377 #define PERI_RST3_UART4 (1 << 8) 378 #define PERI_RST3_SSP (1 << 9) 379 #define PERI_RST3_PWM (1 << 10) 380 #define PERI_RST3_BLPWM (1 << 11) 381 #define PERI_RST3_TSENSOR (1 << 12) 382 #define PERI_RST3_DAPB (1 << 18) 383 #define PERI_RST3_HKADC (1 << 19) 384 #define PERI_RST3_CODEC (1 << 20) 385 386 /* 387 * PERI_SC_PERIPH_RSTEN8 388 * PERI_SC_PERIPH_RSTDIS8 389 * PERI_SC_PERIPH_RSTSTAT8 390 */ 391 #define PERI_RST8_RS0 (1 << 0) 392 #define PERI_RST8_RS2 (1 << 1) 393 #define PERI_RST8_RS3 (1 << 2) 394 #define PERI_RST8_MS0 (1 << 3) 395 #define PERI_RST8_MS2 (1 << 5) 396 #define PERI_RST8_XG2RAM0 (1 << 6) 397 #define PERI_RST8_X2SRAM_TZMA (1 << 7) 398 #define PERI_RST8_SRAM (1 << 8) 399 #define PERI_RST8_HARQ (1 << 10) 400 #define PERI_RST8_DDRC (1 << 12) 401 #define PERI_RST8_DDRC_APB (1 << 13) 402 #define PERI_RST8_DDRPACK_APB (1 << 14) 403 #define PERI_RST8_DDRT (1 << 17) 404 405 #endif /* __HI6220_PERI_H__ */ 406
