1 /** @file 2 Header file for QuarkSCSocId Ioh. 3 Copyright (c) 2013-2015 Intel Corporation. 4 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 14 **/ 15 #ifndef _IOH_H_ 16 #define _IOH_H_ 17 18 #ifndef BIT0 19 #define BIT0 0x01 20 #define BIT1 0x02 21 #define BIT2 0x04 22 #define BIT3 0x08 23 #define BIT4 0x10 24 #define BIT5 0x20 25 #define BIT6 0x40 26 #define BIT7 0x80 27 #define BIT8 0x100 28 #define BIT9 0x200 29 #define BIT00 0x00000001 30 #define BIT01 0x00000002 31 #define BIT02 0x00000004 32 #define BIT03 0x00000008 33 #define BIT04 0x00000010 34 #define BIT05 0x00000020 35 #define BIT06 0x00000040 36 #define BIT07 0x00000080 37 #define BIT08 0x00000100 38 #define BIT09 0x00000200 39 #define BIT10 0x00000400 40 #define BIT11 0x00000800 41 #define BIT12 0x00001000 42 #define BIT13 0x00002000 43 #define BIT14 0x00004000 44 #define BIT15 0x00008000 45 #define BIT16 0x00010000 46 #define BIT17 0x00020000 47 #define BIT18 0x00040000 48 #define BIT19 0x00080000 49 #define BIT20 0x00100000 50 #define BIT21 0x00200000 51 #define BIT22 0x00400000 52 #define BIT23 0x00800000 53 #define BIT24 0x01000000 54 #define BIT25 0x02000000 55 #define BIT26 0x04000000 56 #define BIT27 0x08000000 57 #define BIT28 0x10000000 58 #define BIT29 0x20000000 59 #define BIT30 0x40000000 60 #define BIT31 0x80000000 61 #endif 62 63 #define IOH_PCI_CFG_ADDRESS(bus,dev,func,reg) \ 64 ((UINT32) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \ 65 (((UINTN)func) << 8) + ((UINTN)reg) ))& 0x00000000ffffffff 66 67 //---------------------------------------------------------------------------- 68 69 #define INTEL_VENDOR_ID 0x8086 // Intel Vendor ID 70 71 //---------------------------------------------------------------------------- 72 // Pci Configuration Map Register Offsets 73 //---------------------------------------------------------------------------- 74 #define PCI_REG_VID 0x00 // Vendor ID Register 75 #define PCI_REG_DID 0x02 // Device ID Register 76 #define PCI_REG_PCICMD 0x04 // PCI Command Register 77 #define PCI_REG_PCISTS 0x06 // PCI Status Register 78 #define PCI_REG_RID 0x08 // PCI Revision ID Register 79 #define PCI_REG_PI 0x09 // Programming Interface 80 #define PCI_REG_SCC 0x0a // Sub Class Code Register 81 #define PCI_REG_BCC 0x0b // Base Class Code Register 82 #define PCI_REG_PMLT 0x0d // Primary Master Latnecy Timer 83 #define PCI_REG_HDR 0x0e // Header Type Register 84 #define PCI_REG_PBUS 0x18 // Primary Bus Number Register 85 #define PCI_REG_SBUS 0x19 // Secondary Bus Number Register 86 #define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register 87 #define PCI_REG_SMLT 0x1b // Secondary Master Latnecy Timer 88 #define PCI_REG_IOBASE 0x1c // I/O base Register 89 #define PCI_REG_IOLIMIT 0x1d // I/O Limit Register 90 #define PCI_REG_SECSTATUS 0x1e // Secondary Status Register 91 #define PCI_REG_MEMBASE 0x20 // Memory Base Register 92 #define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register 93 #define PCI_REG_PRE_MEMBASE 0x24 // Prefretchable memory Base register 94 #define PCI_REG_PRE_MEMLIMIT 0x26 // Prefretchable memory Limit register 95 #define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte 96 #define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte 97 #define PCI_REG_SID0 0x2e // Subsystem ID low byte 98 #define PCI_REG_SID1 0x2f // Subsystem ID high byte 99 #define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register 100 #define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register 101 #define PCI_REG_INTLINE 0x3c // Interrupt Line Register 102 #define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register 103 104 //--------------------------------------------------------------------------- 105 // QuarkSCSocId Packet Hub definitions 106 //--------------------------------------------------------------------------- 107 108 #define PCIE_BRIDGE_VID_DID 0x88008086 109 110 //--------------------------------------------------------------------------- 111 // Quark South Cluster definitions. 112 //--------------------------------------------------------------------------- 113 114 #define IOH_BUS 0 115 #define IOH_PCI_IOSF2AHB_0_DEV_NUM 0x14 116 #define IOH_PCI_IOSF2AHB_0_MAX_FUNCS 7 117 #define IOH_PCI_IOSF2AHB_1_DEV_NUM 0x15 118 #define IOH_PCI_IOSF2AHB_1_MAX_FUNCS 3 119 120 //--------------------------------------------------------------------------- 121 // Quark South Cluster USB definitions. 122 //--------------------------------------------------------------------------- 123 124 #define IOH_USB_BUS_NUMBER IOH_BUS 125 #define IOH_USB_CONTROLLER_MMIO_RANGE 0x1000 126 #define IOH_MAX_OHCI_USB_CONTROLLERS 1 127 #define IOH_MAX_EHCI_USB_CONTROLLERS 1 128 #define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1 129 130 #define R_IOH_USB_VENDOR_ID 0x00 131 #define V_IOH_USB_VENDOR_ID INTEL_VENDOR_ID 132 #define R_IOH_USB_DEVICE_ID 0x02 133 #define R_IOH_USB_COMMAND 0x04 134 #define B_IOH_USB_COMMAND_BME BIT2 135 #define B_IOH_USB_COMMAND_MSE BIT1 136 #define B_IOH_USB_COMMAND_ISE BIT0 137 #define R_IOH_USB_MEMBAR 0x10 138 #define B_IOH_USB_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12]. 139 #define R_IOH_USB_OHCI_HCCABAR 0x18 140 141 //--------------------------------------------------------------------------- 142 // Quark South Cluster OHCI definitions 143 //--------------------------------------------------------------------------- 144 #define IOH_USB_OHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM 145 #define IOH_OHCI_FUNCTION_NUMBER 0x04 146 147 //--------------------------------------------------------------------------- 148 // Quark South Cluster EHCI definitions 149 //--------------------------------------------------------------------------- 150 #define IOH_USB_EHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM 151 #define IOH_EHCI_FUNCTION_NUMBER 0x03 152 153 // 154 // EHCI memory mapped registers offset from memory BAR0. 155 // 156 #define R_IOH_EHCI_CAPLENGTH 0x00 157 #define R_IOH_EHCI_INSNREG01 0x94 158 #define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16) 159 #define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP) 160 #define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0) 161 #define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP) 162 163 // 164 // EHCI memory mapped registers offset from memory BAR0 + Cap length value. 165 // 166 #define R_IOH_EHCI_CONFIGFLAGS 0x40 167 168 //--------------------------------------------------------------------------- 169 // Quark South Cluster USB Device definitions 170 //--------------------------------------------------------------------------- 171 #define IOH_USBDEVICE_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM 172 #define IOH_USBDEVICE_FUNCTION_NUMBER 0x02 173 174 // 175 // USB Device memory mapped registers offset from memory BAR0. 176 // 177 #define R_IOH_USBDEVICE_D_INTR_UDC_REG 0x40c 178 #define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG 0x410 179 #define B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK 0xff 180 #define R_IOH_USBDEVICE_EP_INTR_UDC_REG 0x414 181 #define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG 0x418 182 #define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK 0x000f0000 183 #define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK 0x0000000f 184 185 //--------------------------------------------------------------------------- 186 // Quark South Cluster 10/100 Mbps Ethernet Device definitions. 187 //--------------------------------------------------------------------------- 188 #define IOH_MAC0_BUS_NUMBER IOH_BUS 189 #define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM 190 #define IOH_MAC0_FUNCTION_NUMBER 0x06 191 #define IOH_MAC1_BUS_NUMBER IOH_BUS 192 #define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM 193 #define IOH_MAC1_FUNCTION_NUMBER 0x07 194 195 // 196 // MAC Device PCI config registers. 197 // 198 #define R_IOH_MAC_DEVICE_ID 0x02 199 #define V_IOH_MAC_VENDOR_ID INTEL_VENDOR_ID 200 #define R_IOH_MAC_DEVICE_ID 0x02 201 #define V_IOH_MAC_DEVICE_ID 0x0937 202 #define R_IOH_MAC_COMMAND 0x04 203 #define B_IOH_MAC_COMMAND_BME BIT2 204 #define B_IOH_MAC_COMMAND_MSE BIT1 205 #define B_IOH_MAC_COMMAND_ISE BIT0 206 #define R_IOH_MAC_MEMBAR 0x10 207 #define B_IOH_MAC_MEMBAR_ADDRESS_MASK 0xFFFFF000 208 209 // 210 // LAN Device memory mapped registers offset from memory BAR0. 211 // 212 #define R_IOH_MAC_GMAC_REG_8 0x20 213 #define B_IOH_MAC_USERVER_MASK 0x0000FF00 214 #define B_IOH_MAC_SNPSVER_MASK 0x000000FF 215 #define R_IOH_MAC_GMAC_REG_16 0x40 216 #define B_IOH_MAC_ADDRHI_MASK 0x0000FFFF 217 #define B_IOH_MAC_AE BIT31 218 #define R_IOH_MAC_GMAC_REG_17 0x44 219 #define B_IOH_MAC_ADDRLO_MASK 0xFFFFFFFF 220 221 //--------------------------------------------------------------------------- 222 // Quark I2C / GPIO definitions 223 //--------------------------------------------------------------------------- 224 225 #define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID 226 #define V_IOH_I2C_GPIO_DEVICE_ID 0x0934 227 228 #define R_IOH_I2C_MEMBAR 0x10 229 #define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12]. 230 231 #define GPIO_SWPORTA_DR 0x00 232 #define GPIO_SWPORTA_DDR 0x04 233 #define GPIO_INTEN 0x30 234 #define GPIO_INTMASK 0x34 235 #define GPIO_INTTYPE_LEVEL 0x38 236 #define GPIO_INT_POLARITY 0x3C 237 #define GPIO_INTSTATUS 0x40 238 #define GPIO_RAW_INTSTATUS 0x44 239 #define GPIO_DEBOUNCE 0x48 240 #define GPIO_PORTA_EOI 0x4C 241 #define GPIO_EXT_PORTA 0x50 242 #define GPIO_EXT_PORTB 0x54 243 #define GPIO_LS_SYNC 0x60 244 #define GPIO_CONFIG_REG2 0x70 245 #define GPIO_CONFIG_REG1 0x74 246 247 //--------------------------------------------------------------------------- 248 // Quark South Cluster UART definitions. 249 //--------------------------------------------------------------------------- 250 251 #define R_IOH_UART_MEMBAR 0x10 252 #define B_IOH_UART_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12]. 253 254 #endif 255
