OpenGrok
Home
Sort by relevance
Sort by last modified time
Full Search
Definition
Symbol
File Path
History
|
|
Help
Searched
refs:RegUnit
(Results
1 - 13
of
13
) sorted by null
/external/llvm/lib/CodeGen/
RegisterPressure.cpp
75
dbgs() << PrintVRegOrUnit(P.
RegUnit
, TRI);
83
dbgs() << PrintVRegOrUnit(P.
RegUnit
, TRI);
112
void RegPressureTracker::increaseRegPressure(unsigned
RegUnit
,
118
PSetIterator PSetI = MRI->getPressureSets(
RegUnit
);
127
void RegPressureTracker::decreaseRegPressure(unsigned
RegUnit
,
130
decreaseSetPressure(CurrSetPressure, *MRI,
RegUnit
, PreviousMask, NewMask);
322
unsigned
RegUnit
= Pair.
RegUnit
;
323
if (TargetRegisterInfo::isVirtualRegister(
RegUnit
)
324
&& !RPTracker.hasUntiedDef(
RegUnit
))
[
all
...]
LiveRegMatrix.cpp
172
unsigned
RegUnit
) {
173
LiveIntervalUnion::Query &Q = Queries[
RegUnit
];
174
Q.init(UserTag, &VirtReg, &Matrix[
RegUnit
]);
MachineTraceMetrics.cpp
676
// Associate each
regunit
with an instruction operand. Depending on the
678
//
regunit
, or the highest operand to read the
regunit
.
681
unsigned
RegUnit
;
686
unsigned getSparseSetIndex() const { return
RegUnit
; }
688
LiveRegUnit(unsigned RU) :
RegUnit
(RU), Cycle(0), MI(nullptr), Op(0) {}
692
// Identify physreg dependencies for UseMI, and update the live
regunit
[
all
...]
MachineScheduler.cpp
[
all
...]
/external/llvm/include/llvm/CodeGen/
RegisterPressure.h
30
unsigned
RegUnit
; ///< Virtual register or register unit.
33
RegisterMaskPair(unsigned
RegUnit
, LaneBitmask LaneMask)
34
:
RegUnit
(
RegUnit
), LaneMask(LaneMask) {}
146
void addPressureChange(unsigned
RegUnit
, bool IsDec,
288
unsigned SparseIndex = getSparseIndexFromReg(Pair.
RegUnit
);
301
unsigned SparseIndex = getSparseIndexFromReg(Pair.
RegUnit
);
538
void increaseRegPressure(unsigned
RegUnit
, LaneBitmask PreviousMask,
540
void decreaseRegPressure(unsigned
RegUnit
, LaneBitmask PreviousMask,
551
LaneBitmask getLastUsedLanes(unsigned
RegUnit
, SlotIndex Pos) const
[
all
...]
LiveRegMatrix.h
19
// the virtual register is inserted into the LiveIntervalUnion for each
regunit
130
/// Check for
regunit
interference only.
139
LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned
RegUnit
);
141
/// Directly access the live interval unions per
regunit
.
142
/// This returns an array indexed by the
regunit
number.
MachineRegisterInfo.h
562
/// virtual register. If
RegUnit
is physical, it must be a register unit (from
564
PSetIterator getPressureSets(unsigned
RegUnit
) const;
[
all
...]
/external/llvm/include/llvm/MC/
MCRegisterInfo.h
162
const MCPhysReg (*RegUnitRoots)[2]; // Pointer to
regunit
root table.
189
/// differentially encoded register and
regunit
lists in DiffLists.
587
/// Returns a (
RegUnit
, LaneMask) pair.
617
MCRegUnitRootIterator(unsigned
RegUnit
, const MCRegisterInfo *MCRI) {
618
assert(
RegUnit
< MCRI->getNumRegUnits() && "Invalid register unit");
619
Reg0 = MCRI->RegUnitRoots[
RegUnit
][0];
620
Reg1 = MCRI->RegUnitRoots[
RegUnit
][1];
/external/llvm/utils/TableGen/
CodeGenRegisters.h
435
struct
RegUnit
{
436
// Weight assigned to this
RegUnit
for estimating register pressure.
441
// Each native
RegUnit
corresponds to one or two root registers. The full
450
RegUnit
() : Weight(0), RegClassUnitSetsIdx(0) {
499
SmallVector<
RegUnit
, 8> RegUnits;
513
// class's units and any inferred
RegUnit
supersets.
646
RegUnit
&getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
647
const
RegUnit
&getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
RegisterInfoEmitter.cpp
225
<< "getRegUnitWeight(unsigned
RegUnit
) const {\n"
226
<< " assert(
RegUnit
< " << RegBank.getNumNativeRegUnits()
232
const
RegUnit
&RU = RegBank.getRegUnit(UnitIdx);
233
assert(RU.Weight < 256 && "
RegUnit
too heavy");
237
<< " return RUWeightTable[
RegUnit
];\n";
322
<< "getRegUnitPressureSets(unsigned
RegUnit
) const {\n"
323
<< " assert(
RegUnit
< " << RegBank.getNumNativeRegUnits()
333
<< " return &RCSetsTable[RUSetStartTable[
RegUnit
]];\n"
577
// Differentially encoded register and
regunit
lists allow for better
[
all
...]
/external/llvm/include/llvm/Target/
TargetRegisterInfo.h
428
/// Returns true if Reg contains
RegUnit
.
429
bool hasRegUnit(unsigned Reg, unsigned
RegUnit
) const {
431
if (*Units ==
RegUnit
)
723
virtual unsigned getRegUnitWeight(unsigned
RegUnit
) const = 0;
743
virtual const int *getRegUnitPressureSets(unsigned
RegUnit
) const = 0;
[
all
...]
/external/llvm/lib/Target/AMDGPU/
SIMachineScheduler.h
465
InRegs.insert(RegMaskPair.
RegUnit
);
SIMachineScheduler.cpp
331
if (TargetRegisterInfo::isVirtualRegister(RegMaskPair.
RegUnit
))
332
LiveInRegs.insert(RegMaskPair.
RegUnit
);
358
unsigned Reg = RegMaskPair.
RegUnit
;
[
all
...]
Completed in 1252 milliseconds